AM29DL322C AMD | Alldatasheet

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 21534 Rev: C Amendment/ +1 Issue Date: January 1999 Refer to AMD’s Website (www.amd.com) for the latest information. Am29DL322C/Am29DL323C

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES n Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. — Zero latency between read and write operations n Multiple bank architectures — Two devices available with different bank sizes (refer to Table 3) n SecSi (Secured Silicon) Sector: Extra 64 KByte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed n Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. n Package options — 63-ball FBGA — 56-pin SSOP — 48-pin TSOP n Top or bottom boot block n Manufactured on 0.32 µm process technology n Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS n High performance — Access time as fast 90 ns — Program time: 7 µs/word typical utilizing Accelerate function n Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode n Minimum 1 million write cycles guaranteed per sector n 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES n Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations n Supports Common Flash Memory Interface (CFI) n Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank n Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles n Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES n Any combination of sectors can be erased n Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion n Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode n WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function provides accelerated program times n Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system

The Am29DL322C/Am29DL323C family consists of 32 megabit, 3.0 volt-only flash memory devices, orga- nized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 90 or 120 ns. The devices are offered in 56-pin SSOP , 48-pin TSOP , and 63-ball FBGA packages. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and si- multaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL16xC device family uses multiple bank architectures to provide flexibility for different applica- tions. Two devices are available with the following bank sizes: Am29DL322C/Am29DL323C Features The SecSi (Secured Silicon) Sector is an extra 64 Kbit sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is per- manently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL322 4 28 DL323 8 24

3 Am29DL322C/Am29DL323C

Part Number Am29DL322C/Am29DL323C Speed Option Standard Voltage Range: V CC = 2.7–3.6 V 90 120 Max Access Time (ns) 90 120 CE# Access (ns) 90 120 OE# Access (ns) 40 50 VCC VSS Upper Bank AddressA0–A20 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address Status Control A0–A20 A0–A20 A0–A20A0–A20 DQ0–DQ15 DQ0–DQ15 Mux Mux Mux 21534C-1

WE# RESET# NC WP#/ACC RY/BY# A17 A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# WP#/ACC A21 RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 XX DQ2 XX VSS NC DQ7 NC DQ6 NC NC DQ1 NC DQ0 OE# VSS CE# DQ5 NC DQ4 VCC NC DQ3 NC 48-Pin Standard TSOP 21534C-2 NC WP#/ACC RY/BY# A18 A17 NC NC NC NC CE# V SS OE# DQ0 DQ8 RESET# WE# A20 A19 A10 A11 A12 A13 A14 A15 NC NC NC NC A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 DQ6 DQ13 DQ5 DQ12 DQ4 V CC 21534C-3 56-Pin SSOP

5 Am29DL322C/Am29DL323C

Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC NCNC NC NC NC NC NC NC NC NCNC NC NC NC DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 63-Ball FBGA Top View, Balls Facing Down 21534C-4

A0–A20 = 21 Addresses DQ0–DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 21534C-5 16 or 8 DQ0–DQ15 (A-1) A0–A20 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am29DL322C/Am29DL323C

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Blank = Standard Processing B= B u r n - I n N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) E = Extended (-55 °C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) Z = 56-Pin Shrink Small Outline Package (SSO056) WD = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 14 mm package (FBD063) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector Am29DL322C/Am29DL323C 90 E IT Valid Combinations for TSOP and SSOP Packages AM29DL322CT90, AM29DL322CB90 EI, ZIAM29DL323CT90, AM29DL323CB90 AM29DL322CT120, AM29DL322CB120 EI, EE, ZI, ZEAM29DL323CT120, AM29DL323CB120 Valid Combinations for FBGA Packages Order Number Package Marking AM29DL322CT90, AM29DL322CB90 WDI D322CT90V, D322CB90V IAM29DL323CT90, AM29DL323CB90 D323CT90V, D323CB90V AM29DL322CT120, AM29DL322CB120 WDI, WDE D322CT12V, D322CB12V I, EAM29DL323CT120, AM29DL323CB120 D323CT12V, D323CB12V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29DL322C/Am29DL323C Device Bus Operations

  1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
  2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

  1. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

Protection and Unprotection”. If WP#/ACC = VHH , all sectors will be unprotected. used as an input for the LSB (A-1) address function. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z High-Z High-Z

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addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more in- formation. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 3–6 indicate the ad- dress space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V , the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables

data is latched and always available to the system. automatic sleep mode current specification. rameters and to Figure 14 for the timing diagram. Table 2. Am29DL322C/Am29DL323C Device Bank Divisions

64 Kbyte/32 Kword

11 Am29DL322C/Am29DL323C

Table 3. Sector Addresses for Top Boot Sector Devices

Am29DL322CT, A20 and A18 for Am29DL323CT. Table 4. Secure Sector Addresses for Top Boot Devices

13 Am29DL322C/Am29DL323C

Table 5. Sector Addresses for Bottom Boot Sector Devices

are A20–A17 for Am29DL322CB, A20 and A18 for Am29DL323CB. Table 6. Secure Sector Addresses for Bottom Boot Devices

15 Am29DL322C/Am29DL323C

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 7. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Table 7. Am29DL322C/Am29DL323C Autoselect Codes, (High Voltage Method)

Table 8. Top Boot Sector/Sector Block Addresses Table 9. Bottom Boot Sector/Sector Block

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equipment requires VID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD representative for details. a top-boot-configured device. in “Sector/Sector Block Protection and Unprotection”. Figure 1. Temporary Sector Unprotect Operation

  1. All protected sectors unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

  1. All previously protected sectors are protected once

Figure 2. In-System Sector Protect/Unprotect Algorithms

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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the Secure Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The cus- tomer-lockable version has the SecSi (Secured Sili- con) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents cus- tomer-lockable devices from being used to replace de- vices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the ad- dresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the fol- lowing: n A random, secure ESN only n Customer code through the ExpressFlash service n Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable mem- ory area at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at ad- dresses 1F8000h–1F8007h in word mode (or ad- dresses 3F0000h–3F000Fh in byte mode). Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the Secure Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The SecSi Sector can be read, pro- grammed, and erased as often as required. The SecSi Sector area can be protected using one of the following procedures: n Write the three-cycle Enter Secure Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the Secure Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Se- cure Sector. n Write the three-cycle Enter Secure Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection” sec- tion. Once the Secure Sector is locked and verified, the system must write the Exit Secure Sector Region com- mand sequence to return to reading and writing the re- mainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure avail- able for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than VLKO , the device does not ac- cept any write cycles. This protects data during VCC

or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. the system must write the reset command. device to the autoselect mode. tative for copies of these documents. Table 10. CFI Query Identification String

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Table 11. System Interface String Table 12. Device Geometry Definition

Table 13. Primary Vendor-Specific Extended Query The number of sectors in Bank 2 is device dependent. the device to reading array data.

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in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence: n A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. n A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. n A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 3–6 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. Table 14 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Table 14 shows the address and

25 Am29DL322C/Am29DL323C

erase. The system is not required to provide any con- trols or timings during these operations. Table 14 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the sta- tus of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 14 shows the ad- dress and data requirements for the sector erase com- mand sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written dur- ing the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro- duces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended.

mation on these status bits. just as in the standard Byte Program operation. Figure 4. Erase Operation

  1. See Table 14 for erase command sequence.
  2. See the section on DQ3 for information on the sector

27 Am29DL322C/Am29DL323C

Table 14. Am29DL322C/Am29DL323C Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15–DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A20–A11 are don’t cares.
  3. No unlock or command cycles required when bank is in read
  4. The Reset command is required to return to the read mode (or to

the bank is providing status information).

  1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

  1. The data is 80h for factory locked and 00h for not factory locked.
  2. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

  1. The Unlock Bypass command is required prior to the Unlock
  2. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

  1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

  1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

29 Am29DL322C/Am29DL323C

Table 15 shows the outputs for RY/BY#. complete, DQ6 stops toggling. lected sectors that are protected. whether a sector is actively erasing or is erase-suspended. vice enters the Erase Suspend mode, DQ6 stops toggling. Table 15 shows the outputs for Toggle Bit I on DQ6. subsection on DQ2: Toggle Bit II. Figure 6. Toggle Bit Algorithm

31 Am29DL322C/Am29DL323C

Table 15. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

33 Am29DL322C/Am29DL323C

Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max ; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC , VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4)VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = V IL, OE# = VIH 17 35 mA IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration V CC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC –0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

35 Am29DL322C/Am29DL323C

Table 16. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

  1. See Figure 11 and Table 16 for test specifications.

0 VRY/BY#

Figure 13. Read Operation Timings

37 Am29DL322C/Am29DL323C

Figure 14. Reset Timings

39 Am29DL322C/Am29DL323C

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

41 Am29DL322C/Am29DL323C

  1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” .
  2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

43 Am29DL322C/Am29DL323C

Figure 22. Toggle Bit Timings (During Embedded Algorithms) Figure 23. DQ2 vs. DQ6

Figure 24. Temporary Sector Unprotect Timing Diagram

45 Am29DL322C/Am29DL323C

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 ns tDVEH tDS Data Setup Time Min 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

47 Am29DL322C/Am29DL323C

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data.
  3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
  4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 49 sec Byte Program Time 9 300 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 7 210 µs Word Program Time 11 360 µs Chip Program Time (Note 3) Byte Mode 36 108 sec Word Mode 24 72 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 6 7.5 pF C OUT Output Capacitance V OUT = 0 8.5 12 pF C IN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

49 Am29DL322C/Am29DL323C

SSO056—56-Pin Shrink Small Outline Package (SSOP) (measured in millimeters) SEE DETAIL "G" SEE DETAIL "B"

0.20 M C

C A SS B 0.20 M C A SS B0.10 56 29 12 8 Index Area 13.10 13.50 15.70 16.30 16-038-SSO56-2_AB ES107 9.15.98 lv 23.40 24.00 SEATING PLANE

0.80 BSC

0.25 0.45 0.45 0.65 1.15 1.35 2.00 MAX GAUGE PLANE SEATING PLANE DETAIL "G" 0.60 1.00

0.09 Min

A A 0.25

0.40 BSC

X = D or F DETAIL "B" With Lead Finish 0.10 0.21 0.10 0.18 0.30 0.40 0.25 0.45 Base Metal SECTION A-A

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm (measured in millimeters) .25 .10 M ZAB M Z 0.20 (4X) 0.25 0.35 0.84 0.94 0.20 0.30 1.00 1.20 0.10 Z 0.25 Z 8.00 BSC

14.00 BSC

8.80 BSC

16-038-FBA-3_AA ET154 11.11.98 lv A B Z 0.80 BSC

5.60 BSC

0.40 BSC. 0.40 BSC.

51 Am29DL322C/Am29DL323C

TS 048—48-Pin Standard TSOP (measured in millimeters) 18.30 18.50 19.80 20.20 11.90 12.10 0.05 0.15

0.50 BSC

0.95 1.05 16-038-TS48-2 TS 048 DT95 8-8-96 lv Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.25MM (0.0098") BSC 0.08 0.20

Deleted the 90R and 120R speed options. Expanded the full voltage range to 2.7–3.6 V. Distinctive Characteristics Added 125°C to 20-year data retention bullet. Connection Diagrams Changed the FBGA diagram from bottom view to top view. Changed the FBGA ordering nomenclature to “YD.” The package designation is now FBD063. Device Bus Operations Accelerated Program Operation and Write Protect (WP#) sections: Added note to indicate that the WP#/ACC must not be left floating or unconnected. Command Definitions Unlock Bypass Command Sequence: Added note to indicate that the WP#/ACC must not be left floating or unconnected. DC Characteristics Changed maximum I LI current to ±3.0 µA. Erase and Programming Performance Replaced TBDs in table with actual values. Physical Dimensions Updated the FBGA drawing, table, and notes. The package designation is now FBD063. Deleted 40-pin TSOP drawing. Revision B+1 Valid Combinations table: Corrected combinations to indicate YD for the FBGA package. Sector Address table Corrected bank divisions for both sector address tables. Command Definitions table Added the term “sector block” to the notes where appropriate. DC Characteristics Changed maximum ILI current to ±1.0 µA. AC Characteristics Temporary Sector Unprotect: Moved the accelerated program timing diagram to follow the program opera- tions timings. Added the term “sector block” where appropriate elsewhere on the page. Revision C Global Changed data sheet title. Product Selector Guide Replaced “Full Voltage Range: VCC = 2.7–3.6 V” with “Standard Voltage Range: VCC = 2.7–3.3 V .” Removed 70R speed option. Added 90R and 120R speed options. Secured Silicon (SecSi) Sector Flash Memory Region Factory Locked: SecSi Sector Programmed and Pro- tected at the Factory: Corrected the address range of the ESN and distinguished between word and byte modes. Operating Ranges VCC Supply Voltages: Replaced full voltage range with standard voltage range. Revision C+1 Sector/Sector Block Protection and Unprotection Tables Changed the sector address range to A20—A12.Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.