D320GB12VI

AM29DL320G AMD | Alldatasheet

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Publication Number 25769 Revision C Amendment +3 Issue Date May 25, 2005 Am29DL320G Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede AM29DL320G as the factory-recommended migration path. Please refer to each respective datasheets for specifica- tions and ordering information. Availability of this document is retained for reference and historical purposes only. April 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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Publication# 25769 Rev: C Amendment/3 Issue Date: May 25, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29DL320G

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency between read and write operations „ Flexible BankTM architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. „ 256-byte SecSi™ (Secured Silicon) Sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: One time programmable. Once locked, data cannot be changed. „ Zero Power Operation — Sophisticated power mana gement circuits reduce power consumed during inactive periods to nearly zero „ Package options —6 3 - b a l l F B G A —4 8 - b a l l F B G A — 48-pin TSOP — 64-ball Fortified BGA „ Top or bottom boot blocks „ Manufactured on 0.17 µm process technology „ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS „ High performance — Access time as fast 70 ns — Program time: 4 µs/word typical utilizing Accelerate function „ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode „ Minimum 1 million write cycles guaranteed per sector „ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES „ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations „ Supports Common Flash Memory Interface (CFI) „ Erase Suspend/Erase Resume — Suspends erase operations to allow reading from other sectors in the same bank „ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles „ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES „ Any combination of sectors can be erased „ Ready/Busy# output (RY/BY#) — Hardware method for detec ting program or erase cycle completion „ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode „ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing „ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotec t allows changing data in protected sectors in-system This product has been retired and is not recommended for designs. For new and current designs, S29JL032H (for TSOP packages) an d S29PL032J (for FBGA packages) supersede AM29DL320G as the factory-recommended migration path. Please refe r to each respective datasheets for specifications and orderin g information. Availability of this document is re- tained for reference and historical purposes only.

2 Am29DL320G

The Am29DL320G is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 90, or 120 ns. The devices are offered in 48-pin TSOP , 48-ball or 63-ball FBGA packages, and 64-ball Forti- fied BGA. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus con- tention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 4 Mb banks with small and large sectors, and two 12 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device allows a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL320G can be organized as either a top or bottom boot sector configuration. Am29DL320G Features The SecSi TM (Secured Silicon) Sector is an 256 byte extra sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, cus- tomer lockable parts can never be used to replace a factory locked part. Note that some previous AMD

32 Mbit Am29DL32x devices had a larger SecSi

Sector. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. DMS (Data Management Software) allows systems to remove EEPROM devices. by simplifying system software: DMS performs all functions necessary to modify data in file structures, instead of using sin- gle-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage com- pared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify sys- tem design and software integration efforts. The device offers comple te compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 4 Mb Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Bank 2 12 Mb Twenty-four 64 Kbyte/32 Kword Bank 3 12 Mb Twenty-four 64 Kbyte/32 Kword Bank 4 4 Mb Eight 64 Kbyte/32 Kword

4 Am29DL320G

Speed Rating Standard Voltage Range: V CC = 2.7–3.6 V 70 90 120 Max Access Time (ns) 70 90 120 CE# Access (ns) 70 90 120 OE# Access (ns) 30 40 50 VCC VSS Bank 1 Address Bank 2 Address A20–A0 RESET# WE# CE# BYTE# DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# BYTE# DQ15–DQ0 Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. 63-Ball Fine-pitch BGA (8 x 14 mm) Top View, Balls Facing Down

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Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP , BGA, SSOP , PLCC, PDIP). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7 E7 F7 G7 H7 J7 K7 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 48-Ball Fine-pitch BGA (6 x 12 mm) Top View, Balls Facing Down B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 RFURFURFUVSSVIORFURFU VSSDQ15BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18WP#/ACC DQ1DQ9DQ8DQ0A5A6A17 RFU A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 RFURFUVIORFURFURFURFU RFU 64-Ball Fortified BGA (11 x 13 mm) Top View, Balls Facing Down

A20–A0 = 21 Addresses DQ14–DQ0 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 (A-1) A20–A0 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

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ORDERING INFORMATION

AMD standard products are available in several packages and o perating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Am29DL320G T 70 E I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free Package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) WD = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 14 mm package (FBD063) WM = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 12 mm package (FBD048) PC = 64-Ball Fortified-Pitch Ball Grid Array ( FBGA) 1.00 mm pitch, 11 x 13 mm package (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top boot sectors B = Bottom boot sectors DEVICE NUMBER/DESCRIPTION Am29DL320G

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages AM29DL320GT70, AM29DL320GB70 EI, EIN, EFAM29DL320GT90, AM29DL320GB90 AM29DL320GT120, AM29DL320GB120 Valid Combinations for FBGA Packages Order Number Package Marking AM29DL320GT70, AM29DL320GB70 WDI, WDIN, WDF , WDFN D320GT70V, D320GB70V I, FAM29DL320GT90, AM29DL320GB90 D320GT90V, D320GB90V AM29DL320GT120, AM29DL320GB120 D320GT12V, D320GB12V AM29DL320GT70, AM29DL320GB70 WMI, WMIN,” WMF , WMFN D320GT70U, D320GB70U I, FAM29DL320GT90, AM29DL320GB90 D320GT90U, D320GB90U AM29DL320GT120, AM29DL320GB120 D320GT12U, D320GB12U Valid Combinations for Fortified BGA Packages Order Number Package Marking AM29DL320GT70, AM29DL320GB70 PCI, PCF D320GT70P , D320GB70P I, FAM29DL320GT90, AM29DL320GB90 D320GT90P , D320GB90P AM29DL320GT120, AM29DL320GB120 D320GT12P , D320GB12P

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A20:A0 in word mode (BYTE# = V IH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. used as an input for the LSB (A-1) address function. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z High-Z High-Z

10 Am29DL320G

addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more in- formation. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits re- quired to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and I CC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. I CC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to VIH. ICC4 in the DC Characteristics table represents the reset current. Also refer to AC Characteristics tables for RESET# timing parameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

12 Am29DL320G

Table 2. Top Boot Sector Addresses

Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324. Table 3. Top Boot SecSi TM Sector Addresses Table 2. Top Boot Sector Addresses (Continued)

14 Am29DL320G

Table 4. Bottom Boot Sector Addresses

are A20–A18 for Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324. Table 5. Bottom Boot SecSi TM Sector Addresses Table 4. Bottom Boot Sector Addresses (Continued)

16 Am29DL320G

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 6. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Table 6. Autoselect Codes, (High Voltage Method)

1. The bank address bits are A20–A18.
2. The device ID must be read across three cycles.

Table 7. Top Boot Sector/Sector Block Addresses Table 8. Bottom Boot Sector/Sector Block

18 Am29DL320G

equipment requires V ID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD representative for details. a top-boot-configured device. in “Sector/Sector Block Protection and Unprotection”. Figure 25 shows the timing diagrams, for this feature. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = V IL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

Figure 2. In-System Sector Protection/

20 Am29DL320G

SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a 256-byte Flash memory region that enables perma- nent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lock- able version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi TM Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the ad- dresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the fol- lowing: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot de- vice the ESN will be at addresses 1FF000h–1FF007Fh in word mode (or addresses 3FE000h–3FE0FFh in byte mode). Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional 256-byte Flash mem- ory space, expanding the size of the available Flash array. Additionally, note the difference in the loca- tion of the ESN compared to previous Am29DL32x top boot factory locked devices. The SecSi Sector is one-time programmable, may not be erased, and can be locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure avail- able for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

Figure 3. SecSi Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. device to reading array data.

22 Am29DL320G

Table 9. CFI Query Identification String Table 10. System Interface String

Table 11. Device Geometry Definition Table 12. Primary Vendor-Specific Extended Query

24 Am29DL320G

Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 13 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 13 shows the address and data requirements. This method is an alternative to that shown in Table 6, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device Addresses (Word Mode) Addresses (Byte Mode) Data Description

mand sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence: ■ A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■ A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■ A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Table 2 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algo- rithm. Table 13 shows the address and data require- ments for both command sequences. See also “SecSi TM (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are unavail- able when the SecSi Sector is enabled. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Table 13 shows the address and data requirements for the byte program command se- quence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 13 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts

26 Am29DL320G

and Figure 18 for timing diagrams. Figure 4. Program Operation tion for information on these status bits. array data, to ensure data integrity. and Figure 20 section for timing diagrams. ings during these operations. Note: See Table 13 for program command sequence.

28 Am29DL320G

Table 13. Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A20–A11 are don’t cares.
3. No unlock or command cycles required when bank is reading
4. The Reset command is required to return to the read mode (or to

the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The device ID must be read across three cycles. The device ID is

00h for bottom boot devices, and 01h for top boot devices.

1. The data is 82h for factory locked and 02h for not factory locked.
2. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

30 Am29DL320G

Table 14 shows the outputs for RY/BY#. complete, DQ6 stops toggling. lected sectors that are protected. whether a sector is actively erasing or is erase-suspended. vice enters the Erase Suspend mode, DQ6 stops toggling. Table 14 shows the outputs for Toggle Bit I on DQ6. subsection on DQ2: Toggle Bit II. Figure 7. Toggle Bit Algorithm

32 Am29DL320G

Table 14. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status info rmation. Refer to the appropriate subsection for further
2. When reading write operation status bits , the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

34 Am29DL320G

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset# Input Load Current V CC = VCC max, RESET#= 12.5 V 35 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (Notes 2, 3) CE# = V IL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = V IL, OE# = VIH 17 35 mA IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

36 Am29DL320G

Table 15. Test Specifications Figure 12. Test Setup Figure 13. Input Waveforms and Measurement Levels

1. See Figure 12 and Table 15 for test specifications.

0 VRY/BY#

Figure 14. Read Operation Timings

38 Am29DL320G

Figure 15. Reset Timings

40 Am29DL320G

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 70 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 15 ns tWLAX tAH Address Hold Time Min 45 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

42 Am29DL320G

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

44 Am29DL320G

Figure 23. Toggle Bit Timings (During Embedded Algorithms) Figure 24. DQ2 vs. DQ6

Figure 25. Temporary Sector Unprotect Timing Diagram

46 Am29DL320G

Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 70 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 50 ns tDVEH tDS Data Setup Time Min 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 30 35 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

48 Am29DL320G

1. Figure indicates last two bus cycl es of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for regulated devices), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 28 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 4 120 µs Word Program Time 7 210 µs Chip Program Time (Note 3) Byte Mode 21 63 sec Word Mode 14 42 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

50 Am29DL320G

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm Dwg rev AF; 10/99

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm Dwg rev AG; 7/2000 FBD 048 6.00 mm x 12.00 mm PACKAGE 1.20 0.20 0.84 0.94

12.00 BSC

6.00 BSC

5.60 BSC

4.00 BSC

0.25 0.30 0.35

0.80 BSC

0.40 BSC

52 Am29DL320G

TS 048—Thin Small Outline Package Dwg rev AA; 10/99

LAA064—64-ball Fortified Ball Grid Array ( FBGA) 11 x 13 mm package

54 Am29DL320G

Revision A (December 6, 2001) Initial release. Revision A+1 (February 19, 2002) Corrected package marking for 6 x 12 mm FBGA package. Revision B (July 31, 2002) Global Added LAA064 package. Corrected package marking for FBGA. AC Characteristics Added 70 ns speed grade to Test Specifications and Read-Only Operations Revision C (October 13, 2003) Global Changed Advance Information datasheet status to Final. Removed standard products E temperature range, and EE & EEN from Valid Combinations for TSOP packages. Table 6 Autoselect Codes Changed SecSi Indicator Bit (DQ7) for BYTE# = V IL from X to 82, and DQ7 to Q10 to 82h (factory locked), 02h (not factory locked). Customer Lockable: SecSi Sector NOT Pro- grammed or Protected At the Factory Replaced second bullet, added the two paragraphs under bullet and Figure 3. Common Flash Memory Interface (CFI) Modified third and fourth paragraphs. Command Definitions Modified information for array data. Enter SecSi Sector/Exit SecSi Sector Command Sequence Added ACC function note to end of paragraph. Table 13 Command Definitions Changed fourth data from 81/01 to 82/02. Operating Ranges Removed extended (E) devices information. DC characteristics - CMOS Compatible Added I LR information. Trademarks Updated to 2003 standards. Revision C + 1 (May 27, 2004) Added Lead-free (Pb-free) options to the Temperature range breakout of the OPN Table and the Valid Combi- nations table. Revision C + 2 (September 27, 2004) Cover sheet and title page Added notation to superseding documents. Revision C + 3 (May 25, 2005) Cover sheet and title page Added notation to superseding documents.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

©2003 Advanced Micro Devices, Inc. Printed in USA One AMD Place, P .O. Box 3453,Sunnyvale, CA 94088-3453 408-732-2400 TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics.The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative.The company assumes no responsibility for the use of any circuits described herein. © Advanced Micro Devices, Inc. All rights reser ved. AMD, the AMD Arrow logo and combination thereof, are trademarks of Advanced Micro Devices, Inc. Other product names are for informational purposes only and may be trademarks of their respective companies. North America CALIFORNIA, FLORIDA, ILLINOIS, NEW JERSEY, TEXAS, International CHINA, GERMANY, JAPAN, UNITED KINGDOM, Representatives in U.S. and Canada ARIZONA, CALIFORNIA, CANADA, COLORADO, FLORIDA, GEORGIA, ILLINOIS, INDIANA, IOWA, KANSAS, MASSACHUSETTS, MICHIGAN, MINNESOTA, MISSOURI, NEW JERSEY, NEW YORK, NORTH CAROLINA, OHIO, OREGON, UTAH, VIRGINIA, WASHINGTON, WISCONSIN, Representatives in Latin America ARGENTINA, CHILE, COLUMBIA, MEXICO, PUERTO RICO, Sales Offices and Representatives es