D1721C-XXBS20

MSC23T OKI | Alldatasheet

Document overview

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Technical content

——— Eee SEEN MSC23T/D1721C-xxBS20 ee OES ENS aN 1,048,576-Word x 72-Bit DRAM MODULE : FAST PAGE MODE TYPE OO

DESCRIPTION

The OKI MSC23T/D1721C-xxBS20 is a fully decoded 1,048,576-word x 72-bit CMOS Dynamic Random Access Memory Module composed of sixteen 4-Mb DRAMs (1M x 4) and four 2-Mb DRAMs (1M x 2) in TSOP or SOJ packages mounted with twenty decoupling capacitors on an 168-pin glass epoxy dual-inline package supports any application where high density and large capacity of storage memory are required.

FEATURES

• 1-Meg x 72-bit (8 Byte Parity) organization * 4-Mb DRAMs package MSC23T1721C-»xBS20 : TSOP MSC23D1721C-x»xBS20 : SOJ * Single 5 V supply +10% tolerance * Access times : 60, 70, 80 ns «Input : TTL compatible * Output : TTL compatible, 3-state + Buffered inputs (except RAS, DQ's) | © 4 Byte interleave enabled, dual address 0 input (A0/BO) Refresh : 1024 cycles/16 ms * CAS before RAS refresh, CAS before RAS hidden refresh, ‘RAS-only refresh capability * Multi-bit test mode. capability * Fast Page Mode capability PRODUCT FAMILY , Power Dissipation Fi Cycle Time liad [teao[ tan [toro | toea| ein) Standby (Max) wiscasT/01721¢-608820__[é0ns|36 ne|20ns|20ns| 110ns | 11220 mW _| 143 mw Mscasti7a1c-708s20 _[70ns|41ns|26n6[25ns[ 190ns | _101z0mW | (0s eve scasT/oi721¢-208s20 [eons|46ns]25 ns]25ns] 150ns | _ 9020mW | ™ 351

MSC23T/D1721C-xxBS20 OKI Semiconductor eS KE Semiconductor PIN CONFIGURATION MSC23T1721C-xxBS20 133.35 20.13 4.04 Max : Vy 2 { 1888 : Al am) se ES] FP pom ono Speen gf] 508 Min. eagzoi3tl | 6 IT] 3693201 4 2-Rta01 1.2730. || 1.432013] | I 6.35 20.1 [ 30201311 35 “008 cL 101 20.1 0.25 Max. Seen 0.23 Min, 1.27 0.4 6.35 20.1 635 20.1 OETAILA DETAIL B DETAILC 352

OKI Semiconductor MSC231/D1721C-xxBS20 Se WlM-0— MSC 23T/D1721C-xxBS20 MSC23D1721C-xxBS20 133.35 20.13 9.3 Max. q VY kd 5 2-48 .204 aif pr fn \\ Gan eEETTTTTNTS gf} 6.08Min 8.89 20.13) _ 1.27404 11.49 20.13 ia 6.95 20.1 lh 2=R1 2041 3.020.131] 20 70.08, : cL 1.01 40.1

0.25 Max,

seaaeas 0.23 Min. 1.27 201 6.35 20.1 6.35 20.1 DETAIL A DETAIL B DETAIL G 353

MSC23T/D1721C-xxBS20 OKI Semiconductor MscesTioI7eIC-8520 eat Seiconcuctr Front Side Fa [PPP Po aaa Pe a Hato are eae 3 30 ZS A See 98 ag [ao ee Pare co | an | 10 [oor |e wes] ae Tate ee oor] ae | ee | as ee ene | Vs [as | ease || ease tenet et a a i a 16 [ oom | [afew er ber far |e [pate |e seve ; Back Side € RR Pin No Pinan a Won al [in i nl | Fn Won [Pn No Psa ee a | ose] as | poco [iar [-ooss}| ss bass a7 [pos [| ior_}-oast || et | a0 [iste | es oe ee [ose Iason] tee “no 1s] seo apa oto ea fae ie Peer art eT = [iar oose_| 156 | pase a] ooo Tos [ne [as Tne oT bae s@_|-ooat 108 [ne ta6} “60 ae vee pore es | 00 | “He Was | tar Wes tae tbo A a a areas Te [ne atone? iae [net sf eee a [00s [5] eI toe} Poets oon te

90007 Hb Vas 105 [Wee HT 150 bee tera

+00 [aoa [aera I etme eee tt ee CO 354

OKI Semiconductor MSC23T/D1721C-xxB$20 Presence Detect Pins Pin No. MSC28T/D1721C MSC23T/D1721C MSC23T/D1721C ia -60BS20 -70B820 ~80BS20 79 a Vou 163 a Vo Vo. 80 a Vou Vou 164 a Vou 81 a Vou 165 es Vou 82 a 166 a Vow 83 a No

167 CS Vss

Note: PDi - PD8 Buffered Output) sae 355

| | | . MSC231/D1721C-»x.BS20 OKI Semiconductor SSS OC KT Semiconciuctor BLOCK DIAGRAM D> bo —> MeA3 —> i > « > Ao rH HEP HH Ve _, Vox _V Sore HES se tH] A1-49 bal — as Hat ao bo poet com ar bas ri DOT pode tHe] a} oar ro a}— pass rot) roy [ LWW [ ov tit pa} ooe tad oo} oow TT] AL<A® 9a) oat HALAS pa} poss HEH HHH po CEL tise ra POT te [ [vic vs | Wea__v 1140 00}— nos t]A0 pal oss HAt-9 bal — dato rHat.ae 00|— coe to al oa HH a}— bow co ba bare to ba} pave ro ror | bie Vas [|e y, ‘ ust —> cates ators = TASS eee a/— ousz . To mr tJ 40 oal— vais tfAd—~ pa}— nose ie Ser tae tPBls* tat tas OER > THe Daf oaat = TAS tH 00} — bos Roseee [tH | (es ves [ Lee vs tala a}— boxe Hat as bol pase jan ay paz HH bal — baso ace ay oaas aaa a) 06+ eon E ro [ [ve Ves [ [ve Ves tfAd Bo} poss tH A9_ Dat— pose T1] AL-A9 00)— ass tJAL:A9 pal— port tH Hr Cr gise Cr gas? ror ance t-440 _—oa}— oozr tid Ga noes TI] Al-A9 pa}—~ poze Ho At-AS eal ~ ooes rH Dar baze th ‘ba }— cass arm ay 9030 ror 9a}— dass AT} carr Y 83 bass ge ace tS > i eat soe CAST > tof bare — (4 Mc $$ Vex Mis : ve ca cree C20 vss | 356

OKI Semiconductor MSG231/D1721C-xxBS20 OFSemiconductor 0 MS0287/D1721C-xxBS20

ELECTRICAL CHARACTERISTICS

Voltage on Any Pin Relative toVss |" Vw Vor [100070 |S Voage Vor SupplyRelatvetoVss | Veo | 100070 ~*~ Short Cireuit Output Curent | tos [SO SS*~*~*~CS*SCiA Power Dissipation a Operating Temperature [Ton [tw Sd Storage Temperature [tag [oto tas e Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions {Ta = 0°C to 70°C) Parameter | Symbol [ "Min. [Tye [Max [Unit Power Supply Votage [vee [45 [so [ss |v [ves [oo To Input High Vottage [vw ea as Input Low Vottage [om [0 [= os £ SARE pacitan Ca ee a= 25°C, t= 1 MHz) Parameter [Symbol [tye Max. ]unit Input Capacitance (A0~A9,80) [Gar [| St. S*dYSSCO Input Capactance (RASO,RASZ) | Gm [— —Ss| Sit —«dSSC Input Capacitance ; (CASO -CAST, WED, WE2, DEO, TED , WoCapactanes (oo0-Da71) |" Goo [S| St SC*dYS Note: Capacitance measured with Boonton Meter. 357

MSC231/01721C-xxBS20 OKI Semiconductor COKE Semiconductor DC Character: hay stics foo = 5 V £10%, Ta = 0°C to 70°C) 1S023T/D1721C|MSC23T/D1721CMSC23 r/01721C) Parameter [symbol -G0BS20_| -708S20 | -s08s20 Note OVSViS65V; Input Leakage Current All other pins not -100 under test = 0V Dour disable a CutoutHigh Vonage | Vow [ion=—60ma [24 | Ver | 24 | Woo | 24) Vel VI CuiputLowVotave [Vor fim =42ma_— [0 [04 | 0 [oa | 0 [oat vy] Average Power Supply Gurrent BK. GS cytng 1840 1640 | ma 1,2 (Operating) _ Power Supply cc Current (Standby) RAB, GA 1 - " 2Voe-~0.2V Average Power RAS cycling, Supply Current ‘cos | TAS = Vin, 1640 12 > (RAS-only Retresh) tac = Min. | . Average Power RAS cycling, Ed Supply Current TAS before RAS, 1940 1640 12 (CAS betore RAS Retresh) tac = Min, Average Power RAS = Vii, Supply Current TAS cycling, 1680 1,3 (Fast Page Mode) tec = Min. Notes: 1. Specified values are obtained with the output open. 2. Address can be changed once or less while RAZ Vi, 3. Address can be changed once or less while CAS=Vij. 358

| | OKI Semiconductor MSG231/D1721G-xxBS20 Q¥eESemiconducior MS C231/017216-xx8520 AC Characteristics (1/2) (ec =5V 210%, Ta=0°C to 70°C) Note 1,2.3,11,12 C23T/D1721C\\MSC23T/D1721C/MSC231/D17216| Parameter -70B820 | -808s20 Note Random Read or Write Cycle Time | tae | 110 | = [490 | — [150 | — [as | Read Modify Weite Cycle Time [awe [955 [= [105 [=| 205 [Tas | Fast Page Mode Cycle Time | we | 40 | — [4s | — Tf 50 | — | ns| Fast Page Mode Read Motty Write Cycle Time [tae] 84 | — [90 [— | 104 | — | ns | ‘Access Time trom RAS [ teas [= [60 | — [70 | — | 60 [os [asc Access Time trom CAS [ teas [ =" [20 | =| 2s | = as [as [as Access Time from Column Address | tua [= | 36 [ — Ta [— fa | sla Access Time from OE [ twee | = [20 [= | 2 [— | 25 [ns] 4 Access Time from CAS Precharge | toa | = [40 | — | as | = | 50 | os | 4 Output Low Impedance Time from GAS [tuz{o [—{of—|[o}—Tn| a Output Buffer Turn-off Delay Time [tor | 2 | 20 | 2 | 2 | 2 | 25 [ns] 7 ‘OE to Data Output Buffer Tum-off Delay Time pete tete tate tate Z ‘Transition Time 3 Retresh Period [ tree | = [te | = | 6 [— | 16 [ms/ RAS Precharge Timo He Capac ae pect ete ] RAS Putco Width [ tas [60 [ tox | 70 | 10K [ 80 | 10K | aS Pe wa Fst Page ode) [tg | 60 [one [70 10k 60 [00 | | 4 Sa RAS Hold Time [ teen | 20 | = [a5 | [25 [— Tos] RAS Hold Time referencedto OF | teow | 20 | =] 26 | — | 25 | — [os | TAB Precharge Time | ee | 10 | — [0 | — {10 | = [os] TAS Pulse Width [ teas | 15 | vox [20 | 10K [20 | 10K | ns | TAS Hold Time | tesa | 58 [ — [6s [— [78 | — Ts] GAS to RAS Precharge Time | tear | 70 {| — | 10 | = [10 | = [os] RAS to CAS Delay Time | taco | 18 | 40 | te [as | te | 35 | ns] 6 PAS to Column Address Delay Time | tay | 13 | 24 [ 13 | 20 | 19 | 34 | asl 6 Row Address Set-up Time [usa |" 6 | — [6 [—T 6 | —Trs| Row Address Hold Time {tau { a [Te [= s | — [os] Column Address Set-up Time [wee [2 [ — [2 [= 2 PT os] Column Address Hold Time [ tom | a7 | = Fo | — [af — os] Column Address Hold TimetromRAS | wa {90 | — | 6 | — | 60 | — | rs] Column AddresstoRAS Lead Time [tou | 36 | — | «1 | — | 46 | — | as] 359

| & | MSC237/D1721C-xBS20 OKI Semiconductor mmeeerateoesag OR Semiconductor AC Characteristics (2/2) (oo =5.V 10%, Ta= 0°C to 70°C) Note 1,2,3,11,12 pel ees | ns | tl Parameter Symbol} -60BS20 -70BS20 ~80BS20 Note [ tin. [Max | Min. | Max. | Min, [ Max. | Read Command Set-up Time - | twos [2 [2 | 2 T— Trl Read Command Hold Time [teen [2 [2 |e pl Read Command Hold Time referenced to RAS | ta [2 [= 2 | — 2 }— Tas | 8 Write Command Set-up Time [twos | 2 = [2 | — Pet Tae] 9 Wirita Command Hold Time [wen [92 [Pe 2 | Tas | Write Command Hold Time trom RAS [twen [48 | =F 50 [— 69 | — fos | Write Command Pulse Width | tw [10 [= | 10 | — 10 | — Tos | OE Command Hold Time [toe [7 P= | a2 [Fe [Ts | ‘Write Command to RAS Lead Time | tam |" 20 | = [es — Tas} — Tos | Write Command to CAS Lead Time He ae tee tte Data-in Set-up Time | 2 | = {2 [Ta] 10 Data-in Hold Time [ tow [20 | =F 20 | =| [= Fos b0 Data-in Hold Time trom FAS [toon [80 [ "(736 [ [0 — Tors | OE to Data-in Detay Time | toco [20 [Fas | [5 ts | GAS to WE Delay Time [tow [40 [= To [a [= Tost 9 > RAS to WE Delay Time [ tow {00 [= [95 | 05 P= Tas 19 Column Address to WE Dey Time | two [58 [= 6 | — [71 P— Tos] 9 | TAS Precharge to WE Delay Time [torwo [57 [= ler | — | 72 [— Tos] 9 {GAS Active Delay Time trom IAS Precharge [two [3 | =f 3 | — ls p— Toe] PAS to CAS Set-up Time (CAS before RAS)| [tesa | 10 | =F 10 | — P10 P— Tas | TRAS to GAS Hold Time (CAS betore RAS) [we [8 | = Ts [=e | — Tos] CAS Precharge Time (Refresh Counter Test) | teor [30 [= fas ao PT | WE ta RAS Precharge Timo (CAS before RAS) | twee [15 [= 45 = as PTs | WE Hold Time trom RAS (CRS before FAS) [wan [e | =e [= 8 | — Tos] RAS to WE Set-up Time (Test Mode) [wns [90 [P10 | =] 0 PTs J RAS to WE Hold Time (Test Mode) | wm [10 [10 | — 0 Pas | PDE to PD Data Output Delay Time [ wo | [10 [99 | — 0s | PDE to PO Data Output Buter fe] e [- [2 f-[e[- fo Turn-off Delay Time 360

~ OKI Semiconductor . MSG237/D1721C-xxBS20 ore. __ M8 0287/1721 C-xxBS20 Notes: 1. A startup delay of 200 is is required after power-up, followed by a minimum of eight initialization cycles GAS ony refresh or CHS before RAS refresh) before Proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. 2. AC mesurement assume ty = 5 ns. 3. Vi (Min.) and Vj, (Max.) are reference levels for measuring input timing signals. Transition times are measured between Vin and Vit. 4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100 pF. 5. Operation within the tpcp (Max.) limit ensures that trac (Max. can be met. tacp (Max. is specified as a reference point only. Iftacp is greater than the specified trop (Max,) limit, access time is controlled by tcac. 6. Operation within the trap (Max,) limit ensures that trac Max.) can be met. trap (Max.) is specified as areference pointonly. Iftrap is greater than thespecified trap (Max.) limit, access time is controlled by taa. 7. torr Max.) and topz (Max,) define the time at which the ‘output achieves an open circuit condition and are not referenced to output voltage levels. € coe | 8. trcH or tari must be satisfied for a read cycle. 9. twes, town. twp, tawp and tepwp are not restrictive operating parameters. They areincluded in the data sheet as electrical characteristics only. If twes2 twos (Min), the cycle is an early write cycle and the data output pin will remain in a high impedance state throughout the entire cycle. If tcwp 2 tewo (Min.), trwp = tRw> (in), tawo 2 tawp (Min.) and tepwp 2 tepwp (Min), the cycle is a read modify write cycle and the data output pin will contain data read from the selected cell. if neither conditions is satisfied, the data output logic state (at access time) is undefined. 10. These parameters are referenced to CAS leading edge in an early write cycle, and to WE leading edge in an OF control write cycle or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. Thetest modespecified in this datasheetisa2-bit parallel test function, CAVisnotused. Inaread cycle, ifall internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test: ‘modeis cleared and the memory device retumed to its normal operating state by performing a RAS- only refresh cycle or a CAS before RAS refresh cycle. 12, Ina test mode read cycle, the access time Parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. See ADDENDUM G for AC Timing Waveforms 361