AM29DL16XD_06 AMD | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 57

Technical content

The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29DL16xD Data Sheet Publication Number 21533 Revision E Amendment 5 Issue Date December 1, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21533 Rev: E Amendment: 5 Issue Date: December 1, 2006 Am29DL16xD

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations ■ Multiple bank architectures — Four devices available with different bank sizes (refer to Table 2) ■ Secured Silicon Sector — Current version of device has 64 Kbytes; future versions will have 256 bytes — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ■ Package options — 48-ball Very Thin Profile Fine-pitch BGA — 48-ball Fine-pitch BGA — 64-ball Fortified BGA — 48-pin TSOP ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology — Compatible with Am29DL16xC devices ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast 70 ns — Program time: 7 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 Year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system

6 Am29DL16xD 21533E5 December 1, 2006

The Am29DL16xD family consists of 16 megabit, 3.0 volt-only flash memory devices, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 90, or 120 ns. The devices are offered in 48-pin TSOP , 48-ball Fine-pitch BGA, 48-ball Very Thin Profile Fine-pitch BGA, and 64-ball Fortified BGA packages. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides si- multaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simulta- neously read from the other bank, with zero latency. This releases the system from waiting for the comple- tion of program or erase operations. The Am29DL16xD devices uses multiple bank archi- tectures to provide flexibility for different applications. Four devices are available with these bank sizes: Am29DL16xD Features The Secured Silicon Sector is an extra sector capa- ble of being permanently locked by AMD or customers. The Secured Silicon Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, cus- tomer lockable parts can never be used to replace a factory locked part. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. Factory locked parts provide several options. The Se- cured Silicon Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the Se- cured Silicon Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing re- moval of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or up- date a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, sta- tus, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to in- terface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command reg- ister using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector pro- tection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL161 0.5 Mb 15.5 Mb DL162 2 Mb 14 Mb DL163 4 Mb 12 Mb DL164 8 Mb 8 Mb

8 Am29DL16xD 21533E5 December 1, 2006

Speed Option Standard Voltage Range: V CC = 2.7–3.6 V 70 90 120 Max Access Time (ns) 70 90 120 CE# Access (ns) 70 90 120 OE# Access (ns) 30 40 50 VCC VSS Upper Bank AddressA0–A19 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# BYTE# Status Control A0–A19 A0–A19 A0–A19A0–A19 DQ0–DQ15 DQ0–DQ15

December 1, 2006 21533E5 Am29DL16xD 9 DATA SHEET CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 NC WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 48-Pin Standard TSOP 48-Ball Fine-pitch BGA Top View, Balls Facing Down

10 Am29DL16xD 21533E5 December 1, 2006

VSSDQ15/A-1BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19NCRESET# DQ3DQ11DQ10DQ2NCA18WP#/ACC DQ1DQ9DQ8DQ0A5A6A17 NC A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 NCNCNCNCNCNCNC NC 64-Ball Fortified BGA Top View, Balls Facing Down

December 1, 2006 21533E5 Am29DL16xD 11 DATA SHEET Special Package Handling Instructions Special handling is requir ed for Flash Memory prod- ucts in molded packages (BGA, TSOP , SO, PLCC, PDIP). The package and/or data integrity may be com- promised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 48-Ball Very Thin Profile Fine-pitch BGA Top View, Balls Facing Down

12 Am29DL16xD 21533E5 December 1, 2006

A0–A19 = 20 Addresses DQ0–DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A19 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

December 1, 2006 21533E5 Am29DL16xD 13 DATA SHEET

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29DL16xD T 70 E I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices TEMPERATURE RANGE F = Industrial (–40 °C to +85°C) with Pb-Free Package I = Industrial (–40 °C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) PC = 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) WC = 48-Ball Fine-Pitch Ball Grid Array 0.80 mm pitch, 8 x 9 mm package (FBC048) VR = 48-Ball Very Thin Profile Ball Grid Array 0.80 mm pitch, 8.15 x 6.15 mm package (VBF048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory, 3.0 Volt-only Read, Program, and Erase Valid Combinations for TSOP Packages Valid Combinations for FBGA Packages Order Number Order Number Package Marking AM29DL161DT70, AM29DL161DB70 EI, EF AM29DL161DT70, AM29DL161DB70 PCI, WCI, VRI, PCF , WCF , VRF D161DT70, D161DB70 PI, VI, UI, PF , VF , UF AM29DL162DT70, AM29DL162DB70 AM29DL162DT70, AM29DL162DB70 D162DT70, D162DB70 AM29DL163DT70, AM29DL163DB70 AM29DL163DT70, AM29DL163DB70 D163DT70, D163DB70 AM29DL164DT70, AM29DL164DB70 AM29DL164DT70, AM29DL164DB70 D164DT70, D164DB70 AM29DL161DT90, AM29DL161DB90 AM29DL161DT90, AM29DL161DB90 D161DT90, D161DB90 AM29DL162DT90, AM29DL162DB90 AM29DL162DT90, AM29DL162DB90 D162DT90, D162DB90 AM29DL163DT90, AM29DL163DB90 AM29DL163DT90, AM29DL163DB90 D163DT90, D163DB90 AM29DL164DT90, AM29DL164DB90 AM29DL164DT90, AM29DL164DB90 D164DT90, D164DB90 AM29DL161DT120, AM29DL161DB120 AM29DL161DT1 20, AM29DL161DB120 D161DT12, D161DB12 AM29DL162DT120, AM29DL162DB120 AM29DL162DT1 20, AM29DL162DB120 D162DT12, D162DB12 AM29DL163DT120, AM29DL163DB120 AM29DL163DT1 20, AM29DL163DB120 D163DT12, D163DB12 AM29DL164DT120, AM29DL164DB120 AM29DL164DT1 20, AM29DL164DB120 D164DT12, D164DB12 Note: Ordering numbers containing PCI are identified on device packages with PI. The same applies to WCI and VI, as well as VRI and UI.

14 Am29DL16xD 21533E5 December 1, 2006

each of these operations in further detail. Table 1. Am29DL16xD Device Bus Operations

  1. Addresses are A19:A0 in word mode (BYTE# = V

IH), A19:A-1 in byte mode (BYTE# = VIL).

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

  1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. used as an input for the LSB (A-1) address function. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z High-Z High-Z

December 1, 2006 21533E5 Am29DL16xD 15 DATA SHEET addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 3–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section cont ains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow fast er manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and I CC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC +

16 Am29DL16xD 21533E5 December 1, 2006

data is latched and always available to the system. automatic sleep mode current specification. rameters and to Figure 14 for the timing diagram. Table 2. Am29DL16xD Device Bank Divisions

64 Kbyte/32 Kword

Table 3. Sector Addresses for Top Boot Sector Devices Am29DL161DT, A19–A17 for Am29DL162DT, A19 and A18 for Am29DL163DT, and A19 for Am29DL164DT. Table 4. Secured Silicon ™ Sector Addresses for Top Boot Devices

18 Am29DL16xD 21533E5 December 1, 2006

Table 5. Sector Addresses for Bottom Boot Sector Devices Am29DL161DB, A19–A17 for Am29DL162DB, A19 and A18 for Am29DL163DB, and A19 for Am29DL164DB. Table 6. Secured Silicon ™ Addresses for Bottom Boot Devices

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 7. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Table 7. Am29DL16xD Autoselect Codes, (High Voltage Method) Sector Address, X = Don’t care.

20 Am29DL16xD 21533E5 December 1, 2006

Table 8. Top Boot Sector/Sector Block Addresses Table 9. Bottom Boot Sector/Sector Block ID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. contact an AMD representative to request a copy. The device is shipped with all sectors unprotected.

AMD representative for details. a top-boot-configured device. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection”. Figure 1. Temporary Sector Unprotect Operation

  1. All protected sectors unprotected (If WP#/ACC = V IL,

outermost boot sectors will remain protected).

  1. All previously protected sectors are protected once

22 Am29DL16xD 21533E5 December 1, 2006

Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protection and Unprotection Algorithms

December 1, 2006 21533E5 Am29DL16xD 23 DATA SHEET Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identifica- tion through an Electronic Serial Number (ESN). The Secured Silicon Sector uses an Indicator Bit (DQ7) to indicate whether or not the sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. AMD offers the device with the Secured Silicon Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable versio n is shipped with the unprotected, allowing customers to utilize the that sec- tor in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a “0.” Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are factory locked. The system accesses the Secured Silicon Sector through a command sequence (see “Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence”). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the ad- dresses normally occupied by the boot sectors. This mode of operation contin ues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device re- verts to sending commands to the boot sectors. Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the fac- tory. The Secured Silicon Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable mem- ory area at addresses 00000h–00007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses F8000h–F8007h in word mode (or 1F0000h–1F000Fh in byte mode). Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the Secured S ilicon Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory If the security feature is not required, the Secured S ili- con Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. The Secured Silicon Sector can be read, programmed, and erased as often as required. (Note that in upcoming versions of this device, the Secured Silicon Sector erase function will not be available. ) Note that the ac- celerated programming (ACC) and unlock bypass functions are not available when programming the Se- cured Silicon Sector. The Secured Silicon Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Fig- ure 2, except that RESET# may be at either V IH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. ■ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then use the alter- nate method of sector protection described in the “Sector/Sector Block Protection and Unprotection”. Once the Secured Silicon Sector is locked and veri- fied, the system must write the Exit Secured Silicon Sector Region command sequence to return to read- ing and writing the remainder of the array. The Secured Silicon Sector protection must be used with caution since, once pr otected, there is no proce- dure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection

24 Am29DL16xD 21533E5 December 1, 2006

and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to reading array data on power-up. interfaces for long-term compatibility. system must write the reset command. device to the autoselect mode. representative for copies of these documents. Table 10. CFI Query Identification String

Table 11. System Interface String Table 12. Device Geometry Definition

26 Am29DL16xD 21533E5 December 1, 2006

Table 13. Primary Vendor-Specific Extended Query The number of sectors in Bank 2 is device dependent.

December 1, 2006 21533E5 Am29DL16xD 27 DATA SHEET COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the bank to which the system was writin g to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an aut oselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: ■ A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■ A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■ A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 3–6 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

28 Am29DL16xD 21533E5 December 1, 2006

Enter Secured Silicon™ Sector/Exit Secured Silicon Sector Command Sequence The system can access the Secured Silicon Sector re- gion by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the sys- tem issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal op- eration. Table 14 shows the address and data requirements for both command sequences. See also “Secured Silicon Sector Flash Memory Region” for fur- ther information. Note that a hardware reset (RESET#=V IL) will reset the device to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initia ted by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 14 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The device then returns to reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

30 Am29DL16xD 21533E5 December 1, 2006

reading array data, to ensure data integrity. ters, and Figure 19 section for timing diagrams. period during the sector erase command sequence. imum of 20 µs to suspend the erase operation. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard Byte Program operation. Figure 4. Erase Operation

  1. See Table 14 for erase command sequence.
  2. See the section on DQ3 for information on the sector

Table 14. Am29DL16xD Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A19–A12 uniquely select any sector. in bypass mode, or is being erased.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15–DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A19–A11 are don’t cares.
  3. No unlock or command cycles required when bank is reading
  4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

  1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

  1. The data is 81h for factory locked and 01h for not factory locked.
  2. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

  1. The Unlock Bypass command is required prior to the Unlock
  2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

  1. The Erase Resume command is valid only during the Erase

32 Am29DL16xD 21533E5 December 1, 2006

gram or erase operation is complete or in progress. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 15 shows the outputs for Data# Polling on DQ7. Figure 5. Data# Polling Algorithm

  1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

34 Am29DL16xD 21533E5 December 1, 2006

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare out- puts for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ 6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When- ever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is th at the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previous paragraph. Alter natively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions , the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to det ermine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the status of DQ3 relative to the other status bits.

Table 15. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status in formation. Refer to the appropriate subsection for further
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

36 Am29DL16xD 21533E5 December 1, 2006

  1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V.

  1. Minimum DC input voltage on pins A9, OE#, RESET#,

overshoot to +12.0 V for periods up to 20 ns.

  1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. tionality of the device is guaranteed. Figure 7. Maximum Negative Figure 8. Maximum Positive

December 1, 2006 21533E5 Am29DL16xD 37 DATA SHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Te st Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (Notes 2, 3) CE# = V IL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = V IL, OE# = VIH 17 35 mA IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

38 Am29DL16xD 21533E5 December 1, 2006

Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical I CC1 vs. Frequency

40 Am29DL16xD 21533E5 December 1, 2006

  1. See Figure 11 and Table 16 for test specifications.
  2. Measurements performed by placing a 50-ohm termination on the data pin with a bias of V CC/2. The time from OE# high to

the data bus driven to VCC/2 is taken as tDF.

0 VRY/BY#

Figure 13. Read Operation Timings

Figure 14. Reset Timings

42 Am29DL16xD 21533E5 December 1, 2006

Figure 15. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

December 1, 2006 21533E5 Am29DL16xD 43 DATA SHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 70 80 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling M i n 1 51 51 51 5 n s tWLAX tAH A d d r e s s H o l d T i m e M i n 4 54 54 55 0 n s tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS D a t a S e t u p T i m e M i n 3 53 54 55 0 n s tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 20 20 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 30 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 30 30 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

44 Am29DL16xD 21533E5 December 1, 2006

Figure 18. Accelerated Program Timing Diagram

  1. PA = program address, PD = program data, D OUT is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

  1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
  2. These waveforms are for the word mode.

Figure 19. Chip/Sector Er ase Operation Timings

46 Am29DL16xD 21533E5 December 1, 2006

Figure 20. Back-to-back Read/Write Cycle Timings Figure 21. Data# Polling Timings (During Embedded Algorithms)

48 Am29DL16xD 21533E5 December 1, 2006

Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

50 Am29DL16xD 21533E5 December 1, 2006

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 70 80 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 45 50 ns tDVEH tDS Data Setup Time Min 35 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 30 30 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 30 30 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data.
  3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
  4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

52 Am29DL16xD 21533E5 December 1, 2006

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE AND PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 27 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Word Program Time 7 210 µs Accelerated Byte/Word Program Time 4 120 µs Chip Program Time (Note 3) Byte Mode 9 27 sec Word Mode 6 18 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP/SO 6 7.5 pF BGA 4.2 5 pF COUT Output Capacitance V OUT = 0 TSOP/SO 8.5 12 pF BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP/SO 7.5 9 pF BGA 3.9 4.7 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

December 1, 2006 21533E5 Am29DL16xD 53 DATA SHEET PHYSICAL DIMENSIONS FBC048—48-Ball Fine-Pitch Ball Grid Array 8 x 9 mm package Dwg rev AF; 10/99

54 Am29DL16xD 21533E5 December 1, 2006

LAA064—64-Ball Fortified Ball Grid Array, 13 x 11 mm package

December 1, 2006 21533E5 Am29DL16xD 55 DATA SHEET PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99

56 Am29DL16xD 21533E5 December 1, 2006

VBF048—48-Ball Very Thin Profil e Fine-Pitch Ball Grid Array

December 1, 2006 21533E5 Am29DL16xD 57 DATA SHEET REVISION SUMMARY Revision A (September 1998) Initial release. Revision B (October 1998) Global Deleted the 90R and 120R speed options. Expanded the full voltage range to 2.7–3.6 V. Distinctive Characteristics Added 125°C to 20-year data retention bullet. Connection Diagrams Changed the FBGA diagram from bottom view to top view. Changed the FBGA ordering nomenclature to “YC.” The package designation is now FBC048. Reverted to WC in Revision C. DC Characteristics Changed maximum I LI current to ±3.0 µA. Physical Dimensions Updated the FBGA drawing, table, and notes. The package designation is now FBC048. Deleted 40-pin TSOP drawing. Revision B+1 (October 1998) Command Definitions table Added the term “sector block” to the notes where appropriate. DC Characteristics Changed maximum ILI current to ±1.0 µA. AC Characteristics Temporary Sector Unprotect: Moved the accelerated program timing diagram to follow the program opera- tions timings. Added the term “sector block” where appropriate elsewhere on the page. Revision C (January 1998) Global Changed data sheet title. Product Selector Guide Replaced “Full Voltage Range: V CC = 2.7–3.6 V” with “Standard Voltage Range: VCC = 2.7–3.3 V.” Each part number now has a separate set of speed options. Added 70, 90R, and 120R speed options to the valid combination table. Reverted FBGA designator back to WC. Secured Silicon (Secured Silicon) Sector Flash Memory Region Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory: Corrected the address range of the ESN and distinguished between word and byte modes. Operating Ranges V CC Supply Voltages: Replaced single voltage range with voltage ranges for standard and regulated devices. Revision C+1 (March 19, 1999) Secured Silicon (Secured Silicon) Sector Flash Memory Region Customer Lockable subsection: In the bullets, text should refer to “Enter Se cured Silicon Sector Region command sequence.” Revision C+2 (June 14, 1999) Changed data sheet status to Preliminary. Revision C+3 (August 9, 1999) Global Added Am29DL164 specifications to the document. Added the 70R speed option for the DL163, deleted the SSOP for the DL162. Test Specifications table The 90 ns speed option is tested at 100 pF loading. Revision C+4 (August 23, 1999) Temperature Range: Added “C = Commercial (0°C to +70°C)”. Operating Ranges Added commercial device. Revision C+5 (October 18, 1999) Device Bus Operations Autoselect Mode: Added Am29DL164 device IDs to the Autoselect Codes table.

58 Am29DL16xD 21533E5 December 1, 2006

Revision D (February 22, 2000) Global The Am29DL16x family has migrated to a new 0.23 µm process technology, which is indicated by a “D” in the ordering part number. All references in this docu- ment have been changed to reflect the new process. Distinctive Characteristics Under “Performance Characteristics,” the typical accel- erated programming time was changed to match the AC tables. AC Characteristics Figure 17, Program Operations Timing; Figure 19, Chip/Sector Erase Operations: Deleted t GHWL and changed OE# waveform to start at high. Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table: Changed the typical and maximum specifications for programming time. Erase and Programming Performance In the table, changed the typical and maximum specifi- cations for programming time. The typical and maxi- mum chip programming times in both byte and word modes are reduced. Physical Dimensions Replaced figures with more detailed illustrations. Revision D+1 (June 21, 2000) Global Data sheet designation has changed from “Advance Information” to “Preliminary.” Deleted references to the 56-pin SSOP and the corre- sponding 70R speed option. Added valid combinations for the Am29DL164D device in TSOP . Added valid combinations for the Am29DL162D devices in TSOP and FBGA packages. Deleted valid combinations for the 80 ns Am29DL164D device in FBGA package. Device Bus Operations Table 3, Sector Addresses for Top Boot Sector De- vices: In note below table, corrected last device part number to top boot. Table 7, Autoselect Codes: The Secured Silicon Sec- tor Indicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. Command Definitions Table 14, Command Definitions: The Secured Silicon Sector Indicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. AC Characteristics Read-only Operations table: Changed parameter t DF to 16 ns for all speed options. Added Note 3. Revision D+2 (September 4, 2000) Deleted remaining references to 80 ns speed option, which was officially removed in Revision D+1. Cor- rected references to Am29DL16xC, which officially changed to Am29DL16xD in Revision D. Revision D+3 (November 22, 2000) Global Deleted Preliminary status from document. Added table of contents. Revision E (July 2, 2001) Added Am29DL161D device to data sheet. Deleted extended temperature range devices. Sector/Sector Block Protection and Unprotection Noted that sectors are unprotected in parallel. Secured Silicon Sector Flash Memory Region Noted changes for upcoming versions of these de- vices: reduced Secured Silicon Sector size and dele- tion of Secured Silicon Sector erase functionality. Current versions of these devices remain unaffected. Revision E+1 (July 29, 2002) Global Added 64-ball Fortified BGA package. Command Definitions Modified caution to state that incorrect command/se- quences may place device in unknown state, upon which device must be reset. Unlock Bypass Command Sequence; Command Definitions table Corrected table and description to indicated that bank address is not required for unlock bypass reset. Package Capacitance Added BGA capacitance specifications.

December 1, 2006 21533E5 Am29DL16xD 59 DATA SHEET Revision E + 2 (February 14, 2003) Global Added VBF048 package, Very Thin Profile Fine Pitch Ball Grid Array, to Distincti ve Characteristics, General Description, Ordering Information, Connection Dia- grams, and Physical Dimensions sections. Revision E+3 (February 25, 2004) AC Characteristics Corrected tSR/W in Figure 20, Back-to-back Read/Write Cycle Timings. Revision E+4 (May 26, 2004) Added Pb-Free OPNs. Revision E5 (December 1, 2006) Global Changed SecSi to Secured Silicon. Erase and Program Operations table Changed t BUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.