AM29DL16XD AMD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 57
Technical content
The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am29DL16xD Data Sheet Publication Number 21533 Revision E Amendment +4 Issue Date May 26, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21533 Rev: E Amendment/+4 Issue Date: May 26, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. Am29DL16xD
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations Multiple bank architectures — Four devices available with different bank sizes (refer to Table 2) SecSi™ (Secured Silicon) Sector — Current version of device has 64 Kbytes; future versions will have 256 bytes — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero Package options — 48-ball Very Thin Profile Fine-pitch BGA — 48-ball Fine-pitch BGA — 64-ball Fortified BGA — 48-pin TSOP Top or bottom boot block Manufactured on 0.23 µm process technology — Compatible with Am29DL16xC devices Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance — Access time as fast 70 ns — Program time: 7 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
— Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system
May 26, 2004 GENERAL DESCRIPTION The Am29DL16xD family consists of 16 megabit, 3.0 volt-only flash memory devices, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 90, or 120 ns. The devices are offered in 48-pin TSOP, 48-ball Fine-pitch BGA, 48-ball Very Thin Profile Fine-pitch BGA, and 64-ball Fortified BGA packages. Standard control pins—chip enable (CE#), write en- able (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. The Am29DL16xD devices uses multiple bank archi- tectures to provide flexibility for different applications. Four devices are available with these bank sizes: Am29DL16xD Features The SecSi™ (Secured Silicon) Sector is an extra sec- tor capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, cus- tomer lockable parts can never be used to replace a factory locked part. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- or y. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL161 0.5 Mb 15.5 Mb DL162 2 Mb 14 Mb DL163 4 Mb 12 Mb DL164 8 Mb 8 Mb
May 26, 2004 PRODUCT SELECTOR GUIDE BLOCK DIAGRAM Part Number Am29DL16xD Speed Option Standard Voltage Range: VCC = 2.7–3.6 V 120 Max Access Time (ns) 120 CE# Access (ns) 120 OE# Access (ns) VCC VSS Upper Bank Address A0–A19 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# BYTE# Status Control A0–A19 A0–A19 A0–A19 A0–A19 DQ0–DQ15 DQ0–DQ15
May 26, 2004 Am29DL16xD CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 NC WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ15/A-1 VSS BYTE# A16 A15 A14 A12 A13 DQ13 DQ6 DQ14 DQ7 A11 A10 VCC DQ4 DQ12 DQ5 A19 NC RESET# WE# DQ11 DQ3 DQ10 DQ2 NC A18 WP#/ACC RY/BY# DQ9 DQ1 DQ8 DQ0 A17 OE# VSS CE# 48-Pin Standard TSOP 48-Ball Fine-pitch BGA Top View, Balls Facing Down
May 26, 2004 CONNECTION DIAGRAMS NC NC NC VSS NC NC NC VSS DQ15/A-1 BYTE# A16 A15 A14 A12 DQ6 DQ13 DQ14 DQ7 A11 A10 DQ4 VCC DQ12 DQ5 A19 NC RESET# DQ3 DQ11 DQ10 DQ2 NC A18 WP#/ACC DQ1 DQ9 DQ8 DQ0 A17 NC A13 WE# RY/BY# VSS OE# CE# NC NC NC NC NC NC NC NC 64-Ball Fortified BGA Top View, Balls Facing Down
May 26, 2004 Am29DL16xD Special Package Handling Instructions Special handling is required for Flash Memory prod- ucts in molded packages (BGA, TSOP, SO, PLCC, PDIP). The package and/or data integrity may be com- promised if the package body is exposed to temperatures above 150°C for prolonged periods of time. DQ15/A-1 VSS BYTE# A16 A15 A14 A12 A13 DQ13 DQ6 DQ14 DQ7 A11 A10 VCC DQ4 DQ12 DQ5 A19 NC RESET# WE# DQ11 DQ3 DQ10 DQ2 NC A18 WP#/ACC RY/BY# DQ9 DQ1 DQ8 DQ0 A17 OE# VSS CE# 48-Ball Very Thin Profile Fine-pitch BGA Top View, Balls Facing Down
May 26, 2004 PIN DESCRIPTION A0–A19 = 20 Addresses DQ0–DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A19 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC
May 26, 2004 Am29DL16xD
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29DL16xD T E I OPTIONAL PROCESSING Blank = Standard Processing N 16-byte ESN devices TEMPERATURE RANGE F Industrial (–40°C to +85°C) with Pb-Free Package I Industrial (–40°C to +85°C) PACKAGE TYPE E 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) PC 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) WC 48-Ball Fine-Pitch Ball Grid Array 0.80 mm pitch, 8 x 9 mm package (FBC048) VR 48-Ball Very Thin Profile Ball Grid Array 0.80 mm pitch, 8.15 x 6.15 mm package (VBF048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T Top sector B Bottom sector DEVICE NUMBER/DESCRIPTION Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory, 3.0 Volt-only Read, Program, and Erase Valid Combinations for TSOP Packages Valid Combinations for FBGA Packages Order Number Order Number Package Marking AM29DL161DT70, AM29DL161DB70 EI, EF AM29DL161DT70, AM29DL161DB70 PCI, WCI, VRI, PCF, WCF, VRF D161DT70, D161DB70 PI, VI, UI, PF, VF, UF AM29DL162DT70, AM29DL162DB70 AM29DL162DT70, AM29DL162DB70 D162DT70, D162DB70 AM29DL163DT70, AM29DL163DB70 AM29DL163DT70, AM29DL163DB70 D163DT70, D163DB70 AM29DL164DT70, AM29DL164DB70 AM29DL164DT70, AM29DL164DB70 D164DT70, D164DB70 AM29DL161DT90, AM29DL161DB90 AM29DL161DT90, AM29DL161DB90 D161DT90, D161DB90 AM29DL162DT90, AM29DL162DB90 AM29DL162DT90, AM29DL162DB90 D162DT90, D162DB90 AM29DL163DT90, AM29DL163DB90 AM29DL163DT90, AM29DL163DB90 D163DT90, D163DB90 AM29DL164DT90, AM29DL164DB90 AM29DL164DT90, AM29DL164DB90 D164DT90, D164DB90 AM29DL161DT120, AM29DL161DB120 AM29DL161DT120, AM29DL161DB120 D161DT12, D161DB12 AM29DL162DT120, AM29DL162DB120 AM29DL162DT120, AM29DL162DB120 D162DT12, D162DB12 AM29DL163DT120, AM29DL163DB120 AM29DL163DT120, AM29DL163DB120 D163DT12, D163DB12 AM29DL164DT120, AM29DL164DB120 AM29DL164DT120, AM29DL164DB120 D164DT12, D164DB12 Note: Ordering numbers containing PCI are identified on device packages with PI. The same applies to WCI and VI, as well as VRI and UI.
May 26, 2004 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. The following subsections describe each of these operations in further detail. Table 1. Am29DL16xD Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con- figuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid Operation CE# OE# WE# RESET# WP#/ACC Addresses (Note 2) DQ0– DQ7 DQ8–DQ15 BYTE# = VIH BYTE# = VIL Read L L H H L/H AIN DOUT DOUT DQ8–DQ14 = High-Z, DQ15 = A-1 Write L H L H (Note 3) AIN DIN DIN Standby VCC ± 0.3 V X X VCC ± 0.3 V H X High-Z High-Z High-Z Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H X High-Z High-Z High-Z Sector Protect (Note 2) L H L VID L/H SA, A6 = L, A1 = H, A0 = L DIN X X Sector Unprotect (Note 2) L H L VID (Note 3) SA, A6 = H, A1 = H, A0 = L DIN X X Temporary Sector Unprotect X X X VID (Note 3) AIN DIN DIN High-Z
May 26, 2004 Am29DL16xD addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 3–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC +
May 26, 2004 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Am29DL16xD Device Bank Divisions Device Part Number Bank 1 Bank 2 Megabits Sector Sizes Megabits Sector Sizes Am29DL161D
0.5 Mbit
15.5 Mbit
64 Kbyte/32 Kword
2 Mbit
Eight 8 Kbyte/4 Kword, three 64 Kbyte/32 Kword
14 Mbit
4 Mbit
Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword
12 Mbit
8 Mbit
Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword
May 26, 2004 Am29DL16xD Table 3. Sector Addresses for Top Boot Sector Devices Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for Am29DL161DT, A19–A17 for Am29DL162DT, A19 and A18 for Am29DL163DT, and A19 for Am29DL164DT. Table 4. SecSi™ Sector Addresses for Top Boot Devices Am29DL164DT Am29DL163DT Am29DL162DT Am29DL161DT Sector Sector Address A19–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 2 Bank 2 Bank 2 Bank 2 SA0 00000xxx 000000h-00FFFFh 00000h–07FFFh SA1 00001xxx 010000h-01FFFFh 08000h–0FFFFh SA2 00010xxx 020000h-02FFFFh 10000h–17FFFh SA3 00011xxx 030000h-03FFFFh 18000h–1FFFFh SA4 00100xxx 040000h-04FFFFh 20000h–27FFFh SA5 00101xxx 050000h-05FFFFh 28000h–2FFFFh SA6 00110xxx 060000h-06FFFFh 30000h–37FFFh SA7 00111xxx 070000h-07FFFFh 38000h–3FFFFh SA8 01000xxx 080000h-08FFFFh 40000h–47FFFh SA9 01001xxx 090000h-09FFFFh 48000h–4FFFFh SA10 01010xxx 0A0000h-0AFFFFh 50000h–57FFFh SA11 01011xxx 0B0000h-0BFFFFh 58000h–5FFFFh SA12 01100xxx 0C0000h-0CFFFFh 60000h–67FFFh SA13 01101xxx 0D0000h-0DFFFFh 68000h–6FFFFh SA14 01110xxx 0E0000h-0EFFFFh 70000h–77FFFh SA15 01111xxx 0F0000h-0FFFFFh 78000h–7FFFFh Bank 1 SA16 10000xxx 100000h-10FFFFh 80000h–87FFFh SA17 10001xxx 110000h-11FFFFh 88000h–8FFFFh SA18 10010xxx 120000h-12FFFFh 90000h–97FFFh SA19 10011xxx 130000h-13FFFFh 98000h–9FFFFh SA20 10100xxx 140000h-14FFFFh A0000h–A7FFFh SA21 10101xxx 150000h-15FFFFh A8000h–AFFFFh SA22 10110xxx 160000h-16FFFFh B0000h–B7FFFh SA23 10111xxx 170000h-17FFFFh B8000h–BFFFFh Bank 1 SA24 11000xxx 180000h-18FFFFh C0000h–C7FFFh SA25 11001xxx 190000h-19FFFFh C8000h–CFFFFh SA26 11010xxx 1A0000h-1AFFFFh D0000h–D7FFFh SA27 11011xxx 1B0000h-1BFFFFh D8000h–DFFFFh Bank 1 SA28 11100xxx 1C0000h-1CFFFFh E0000h–E7FFFh SA29 11101xxx 1D0000h-1DFFFFh E8000h–EFFFFh SA30 11110xxx 1E0000h-1EFFFFh F0000h–F7FFFh Bank 1 SA31 11111000 1F0000h-1F1FFFh F8000h–F8FFFh SA32 11111001 1F2000h-1F3FFFh F9000h–F9FFFh SA33 11111010 1F4000h-1F5FFFh FA000h–FAFFFh SA34 11111011 1F6000h-1F7FFFh FB000h–FBFFFh SA35 11111100 1F8000h-1F9FFFh FC000h–FCFFFh SA36 11111101 1FA000h-1FBFFFh FD000h–FDFFFh SA37 11111110 1FC000h-1FDFFFh FE000h–FEFFFh SA38 11111111 1FE000h-1FFFFFh FF000h–FFFFFh Device Sector Address A19–A12 Sector Size (x8) Address Range (x16) Address Range Am29DL16xDT 11111xxx 1F0000h-1FFFFFh F8000h–FFFFFh
May 26, 2004 Table 5. Sector Addresses for Bottom Boot Sector Devices Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for Am29DL161DB, A19–A17 for Am29DL162DB, A19 and A18 for Am29DL163DB, and A19 for Am29DL164DB. Table 6. SecSi™ Addresses for Bottom Boot Devices Am29DL164DB Am29DL163DB Am29DL162DB Am29DL161DB Sector Sector Address A19–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 1 Bank 1 Bank 1 Bank 1 SA0 00000000 000000h-001FFFh 00000h-00FFFh SA1 00000001 002000h-003FFFh 01000h-01FFFh SA2 00000010 004000h-005FFFh 02000h-02FFFh SA3 00000011 006000h-007FFFh 03000h-03FFFh SA4 00000100 008000h-009FFFh 04000h-04FFFh SA5 00000101 00A000h-00BFFFh 05000h-05FFFh SA6 00000110 00C000h-00DFFFh 06000h-06FFFh SA7 00000111 00E000h-00FFFFh 07000h-07FFFh Bank 2 SA8 00001XXX 010000h-01FFFFh 08000h-0FFFFh SA9 00010XXX 020000h-02FFFFh 10000h-17FFFh SA10 00011XXX 030000h-03FFFFh 18000h-1FFFFh Bank 2 SA11 00100XXX 040000h-04FFFFh 20000h-27FFFh SA12 00101XXX 050000h-05FFFFh 28000h-2FFFFh SA13 00110XXX 060000h-06FFFFh 30000h-37FFFh SA14 00111XXX 070000h-07FFFFh 38000h-3FFFFh Bank 2 SA15 01000XXX 080000h-08FFFFh 40000h-47FFFh SA16 01001XXX 090000h-09FFFFh 48000h-4FFFFh SA17 01010XXX 0A0000h-0AFFFFh 50000h-57FFFh SA18 01011XXX 0B0000h-0BFFFFh 58000h-5FFFFh SA19 01100XXX 0C0000h-0CFFFFh 60000h-67FFFh SA20 01101XXX 0D0000h-0DFFFFh 68000h-6FFFFh SA21 01110XXX 0E0000h-0EFFFFh 70000h-77FFFh SA22 01111XXX 0F0000h-0FFFFFh 78000h-7FFFFh Bank 2 SA23 10000XXX 100000h-10FFFFh 80000h-87FFFh SA24 10001XXX 110000h-11FFFFh 88000h-8FFFFh SA25 10010XXX 120000h-12FFFFh 90000h-97FFFh SA26 10011XXX 130000h-13FFFFh 98000h-9FFFFh SA27 10100XXX 140000h-14FFFFh A0000h-A7FFFh SA28 10101XXX 150000h-15FFFFh A8000h-AFFFFh SA29 10110XXX 160000h-16FFFFh B0000h-B7FFFh SA30 10111XXX 170000h-17FFFFh B8000h-BFFFFh SA31 11000XXX 180000h-18FFFFh C0000h-C7FFFh SA32 11001XXX 190000h-19FFFFh C8000h-CFFFFh SA33 11010XXX 1A0000h-1AFFFFh D0000h-D7FFFh SA34 11011XXX 1B0000h-1BFFFFh D8000h-DFFFFh SA35 11100XXX 1C0000h-1CFFFFh E0000h-E7FFFh SA36 11101XXX 1D0000h-1DFFFFh E8000h-EFFFFh SA37 11110XXX 1E0000h-1EFFFFh F0000h-F7FFFh SA38 11111XXX 1F0000h-1FFFFFh F8000h-FFFFFh Device Sector Address A19–A12 Sector Size (x8) Address Range (x16) Address Range Am29DL16xDB 00000XXX 000000h-00FFFFh 00000h-07FFFh
May 26, 2004 Am29DL16xD Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be programmed with its corresponding programming al- gorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (8.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 7. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Sector Address, X = Don’t care.
Description
CE# OE# WE# A19 to A12 A11 to A10 to to DQ8 to DQ15 DQ7 to DQ0 BYTE# = VIH BYTE# = VIL Manufacturer ID: AMD L L H BA X VID X L X L L X X 01h Device ID: Am29DL161D L L H BA X VID X L X L H 22h X 36h (T), 39h (B) Device ID: Am29DL162D L L H BA X VID X L X L H 22h X 2Dh (T), 2Eh (B) Device ID: Am29DL163D L L H BA X VID X L X L H 22h X 28h (T), 2Bh (B) Device ID: Am29DL164D L L H BA X VID X L X L H 22h X 33h (T), 35h (B) Sector Protection Verification L L H SA X VID X L X H L X X 01h (protected), 00h (unprotected) SecSi™ Indicator Bit (DQ7) L L H BA X VID X L X H H X X 81h (factory locked), 01h (not factory locked)
May 26, 2004 Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be im- plemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algo- rithms and Figure 25 shows the timing diagram. This method uses standard microprocessor bus cycle tim- ing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be in- dividually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector/Sector Block Unprotect”. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 22243 contains further details; contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device Sector / Sector Block A19–A12 Sector / Sector Block Size SA0 00000XXX
64 Kbytes
00001XXX, 00010XXX, 00011XXX 192 (3x64) Kbytes SA4-SA7 001XXXXX 256 (4x64) Kbytes SA8-SA11 010XXXXX 256 (4x64) Kbytes SA12-SA15 011XXXXX 256 (4x64) Kbytes SA16-SA19 100XXXXX 256 (4x64) Kbytes SA20-SA23 101XXXXX 256 (4x64) Kbytes SA24-SA27 110XXXXX 256 (4x64) Kbytes SA28-SA30 11100XXX, 11101XXX, 11110XXX 192 (3x64) Kbytes SA31 11111000
8 Kbytes
A19–A12 Sector / Sector Block Size SA38 11111XXX 11110XXX, 11101XXX, 11100XXX 192 (3x64) Kbytes SA34-SA31 110XXXXX 256 (4x64) Kbytes SA30-SA27 101XXXXX 256 (4x64) Kbytes SA26-SA23 100XXXXX 256 (4x64) Kbytes SA22-SA19 011XXXXX 256 (4x64) Kbytes SA18-SA15 010XXXXX 256 (4x64) Kbytes SA14-SA11 001XXXXX 256 (4x64) Kbytes SA10-SA8 00001XXX, 00010XXX, 00011XXX 192 (3x64) Kbytes SA7 00000111
May 26, 2004 Am29DL16xD through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the de- vice disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the de- vice reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sec- tor/Sector Block Protection and Unprotection”. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin to VID (8.5 V – 12.5 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously pro- tected sectors are protected again. Figure 1 shows the algorithm, and Figure 24 shows the timing diagrams, for this feature. Figure 1. Temporary Sector Unprotect Operation START Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) RESET# = VID (Note 1) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again.
May 26, 2004 Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protection and Unprotection Algorithms Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Set up sector address Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Set up first sector address Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1
May 26, 2004 Am29DL16xD SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses an Indicator Bit (DQ7) to indicate whether or not the sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■A random, secure ESN only ■Customer code through the ExpressFlash service ■Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable mem- ory area at addresses 00000h–00007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses F8000h–F8007h in word mode (or 1F0000h–1F000Fh in byte mode). Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be consid- ered during system design. The SecSi Sector can be read, programmed, and erased as often as required. (Note that in upcoming versions of this device, the SecSi Sector erase function will not be available.) Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection”. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by
May 26, 2004 spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to reading array data on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The sys- tem can read CFI information at the addresses given in Tables 10–13. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10–13. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/over- view/cfi.html. Alternatively, contact an AMD representative for copies of these documents. Table 10. CFI Query Identification String Addresses (Word Mode) Addresses (Byte Mode) Data Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists)
May 26, 2004 Am29DL16xD Table 11. System Interface String Table 12. Device Geometry Definition Addresses (Word Mode) Addresses (Byte Mode) Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Addresses (Word Mode) Addresses (Byte Mode) Data Device Size = 2N byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of bytes in multi-byte write = 2N (00h = not supported) 2Ch 58h 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 001Eh 0000h 0000h 0001h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information
May 26, 2004 Table 13. Primary Vendor-Specific Extended Query Note: The number of sectors in Bank 2 is device dependent. Am29DL161 = 1Fh Am29DL162 = 1Ch Am29DL163 = 18h Am29DL164 = 10h Addresses (Word Mode) Addresses (Byte Mode) Data Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h 88h 0031h Minor version number, ASCII 45h 8Ah 0000h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 94h 00XXh (See Note) Simultaneous Operation 00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank) 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device
May 26, 2004 Am29DL16xD COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and re- quires VID on address pin A9. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: ■A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 3–6 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).
May 26, 2004 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. Table 14 shows the address and data requirements for both command sequences. See also “SecSi Sector Flash Memory Region” for further infor- mation. Note that a hardware reset (RESET#=VIL) will reset the device to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 14 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The device then returns to reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.
May 26, 2004 Am29DL16xD Command Definitions Table 14. Am29DL16xD Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A19–A11 are don’t cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. The data is 81h for factory locked and 01h for not factory locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. The Erase Resume command is valid only during the Erase Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) RA RD Reset (Note 7) XXX Autoselect (Note 8) Manufacturer ID Word 555 AA 2AA (BA)555 (BA)X00 Byte AAA 555 (BA)AAA Device ID Word 555 AA 2AA (BA)555 (BA)X01 (see Table 7) Byte AAA 555 (BA)AAA (BA)X02 SecSi™ Factory Protect (Note 9) Word 555 AA 2AA (BA)555 (BA)X03 Byte AAA 555 (BA)AAA (BA)X06 Sector Protect Verify (Note 10) Word 555 AA 2AA (BA)555 (SA)X02 Byte AAA 555 (BA)AAA (SA)X04 Enter SecSi Sector Region Word 555 AA 2AA 555 Byte AAA 555 AAA Exit SecSi Sector Region Word 555 AA 2AA 555 XXX Byte AAA 555 AAA Program Word 555 AA 2AA 555 PA PD Byte AAA 555 AAA Unlock Bypass Word 555 AA 2AA 555 Byte AAA 555 AAA Unlock Bypass Program (Note 11) XXX PA PD Unlock Bypass Reset (Note 12) XXX XXX Chip Erase Word 555 AA 2AA 555 555 AA 2AA 555 Byte AAA 555 AAA AAA 555 AAA Sector Erase Word 555 AA 2AA 555 555 AA 2AA SA Byte AAA 555 AAA AAA 555 Erase Suspend (Note 13) BA Erase Resume (Note 14) BA CFI Query (Note 15) Word Byte AA
May 26, 2004 Am29DL16xD Table 15. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A
May 26, 2004 Am29DL16xD DC CHARACTERISTICS CMOS Compatible Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode
5 MHz
1 MHz
CE# = VIL, OE# = VIH, Word Mode VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte mA Word ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte mA Word ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH mA IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH ACC pin mA VCC pin mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min
0.85 VCC
V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V
May 26, 2004 Am29DL16xD TEST CONDITIONS Table 16. Test Specifications Key To Switching Waveforms 2.7 kΩ CL 6.2 kΩ 3.3 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 11. Test Setup Test Condition 70, 80 90, 120 Unit Output Load
1 TTL gate
Output Load Capacitance, CL (including jig capacitance) 100 pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 12. Input Waveforms and Measurement Levels
May 26, 2004 AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications. 3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. Parameter Read Cycle Time (Note 1) Min 120 ns tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 120 ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns tOH tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 13. Read Operation Timings
May 26, 2004 Am29DL16xD AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 14. Reset Timings
May 26, 2004 Am29DL16xD AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Write Cycle Time (Note 1) Min 120 ns tAVWL tAS Address Setup Time Min ns tASO Address Setup Time to OE# low during toggle bit polling Min ns tWLAX tAH Address Hold Time Min ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEPH Output Enable High during toggle bit polling Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tELWL tCS CE# Setup Time Min ns tWHEH tCH CE# Hold Time Min ns tWLWH tWP Write Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ µs Word Typ tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min µs tRB Write Recovery Time from RY/BY# Min ns tBUSY Program/Erase Valid to RY/BY# Delay Min ns
May 26, 2004 Am29DL16xD AC CHARACTERISTICS OE# CE# Addresses VCC WE# Data 2AAh SA tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). These waveforms are for the word mode. Figure 19. Chip/Sector Erase Operation Timings
May 26, 2004 AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Note: Not 100% tested. Parameter All Speed Options JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector/Sector Block Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector/Sector Block Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE# WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram
May 26, 2004 Am29DL16xD AC CHARACTERISTICS Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs RESET# SA, A6, A1, A0 Data CE# WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector/Sector Block Protect or Unprotect Verify VID VIH * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram
May 26, 2004 AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Write Cycle Time (Note 1) Min 120 ns tAVWL tAS Address Setup Time Min ns tELAX tAH Address Hold Time Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE# Pulse Width Min ns tEHEL tCPH CE# Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ µs Word Typ tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
May 26, 2004 Am29DL16xD AC CHARACTERISTICS tGHEL tWS OE# CE# WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. PA = program address, SA = sector address, PD = program data. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings
May 26, 2004 ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE AND PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time sec Byte Program Time 150 µs Excludes system level overhead (Note 5) Word Program Time 210 µs Accelerated Byte/Word Program Time 120 µs Chip Program Time (Note 3) Byte Mode sec Word Mode Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 TSOP/SO 7.5 pF BGA 4.2 pF COUT Output Capacitance VOUT = 0 TSOP/SO 8.5 pF BGA 5.4 6.5 pF CIN2 Control Pin Capacitance VIN = 0 TSOP/SO 7.5 pF BGA 3.9 4.7 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years
May 26, 2004 Am29DL16xD PHYSICAL DIMENSIONS FBC048—48-Ball Fine-Pitch Ball Grid Array 8 x 9 mm package Dwg rev AF; 10/99
May 26, 2004 PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array, 13 x 11 mm package
May 26, 2004 Am29DL16xD PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99
May 26, 2004 PHYSICAL DIMENSIONS VBF048—48-Ball Very Thin Profile Fine-Pitch Ball Grid Array
May 26, 2004 Am29DL16xD REVISION SUMMARY Revision A (September 1998) Initial release. Revision B (October 1998) Global Deleted the 90R and 120R speed options. Expanded the full voltage range to 2.7–3.6 V. Distinctive Characteristics Added 125°C to 20-year data retention bullet. Connection Diagrams Changed the FBGA diagram from bottom view to top view. Changed the FBGA ordering nomenclature to “YC.” The package designation is now FBC048. Reverted to WC in Revision C. DC Characteristics Changed maximum ILI current to ±3.0 µA. Physical Dimensions Updated the FBGA drawing, table, and notes. The package designation is now FBC048. Deleted 40-pin TSOP drawing. Revision B+1 (October 1998) Command Definitions table Added the term “sector block” to the notes where appropriate. DC Characteristics Changed maximum ILI current to ±1.0 µA. AC Characteristics Temporary Sector Unprotect: Moved the accelerated program timing diagram to follow the program opera- tions timings. Added the term “sector block” where appropriate elsewhere on the page. Revision C (January 1998) Global Changed data sheet title. Product Selector Guide Replaced “Full Voltage Range: VCC = 2.7–3.6 V” with “Standard Voltage Range: VCC = 2.7–3.3 V.” Each part number now has a separate set of speed options. Added 70, 90R, and 120R speed options to the valid combination table. Reverted FBGA designator back to WC. SecSi (Secured Silicon) Sector Flash Memory Region Factory Locked: SecSi Sector Programmed and Pro- tected at the Factory: Corrected the address range of the ESN and distinguished between word and byte modes. Operating Ranges VCC Supply Voltages: Replaced single voltage range with voltage ranges for standard and regulated devices. Revision C+1 (March 19, 1999) SecSi (Secured Silicon) Sector Flash Memory Region Customer Lockable subsection: In the bullets, text should refer to “Enter SecSi Sector Region command sequence.” Revision C+2 (June 14, 1999) Changed data sheet status to Preliminary. Revision C+3 (August 9, 1999) Global Added Am29DL164 specifications to the document. Added the 70R speed option for the DL163, deleted the SSOP for the DL162. Test Specifications table The 90 ns speed option is tested at 100 pF loading. Revision C+4 (August 23, 1999) Temperature Range: Added “C = Commercial (0°C to +70°C)”. Operating Ranges Added commercial device. Revision C+5 (October 18, 1999) Device Bus Operations Autoselect Mode: Added Am29DL164 device IDs to the Autoselect Codes table.
May 26, 2004 Revision D (February 22, 2000) Global The Am29DL16x family has migrated to a new 0.23 µm process technology, which is indicated by a “D” in the ordering part number. All references in this docu- ment have been changed to reflect the new process. Distinctive Characteristics Under “Performance Characteristics,” the typical accel- erated programming time was changed to match the AC tables. AC Characteristics Figure 17, Program Operations Timing; Figure 19, Chip/Sector Erase Operations: Deleted tGHWL and changed OE# waveform to start at high. Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table: Changed the typical and maximum specifications for programming time. Erase and Programming Performance In the table, changed the typical and maximum specifi- cations for programming time. The typical and maxi- mum chip programming times in both byte and word modes are reduced. Physical Dimensions Replaced figures with more detailed illustrations. Revision D+1 (June 21, 2000) Global Data sheet designation has changed from “Advance Information” to “Preliminary.” Deleted references to the 56-pin SSOP and the corre- sponding 70R speed option. Added valid combinations for the Am29DL164D device in TSOP. Added valid combinations for the Am29DL162D devices in TSOP and FBGA packages. Deleted valid combinations for the 80 ns Am29DL164D device in FBGA package. Device Bus Operations Table 3, Sector Addresses for Top Boot Sector De- vices: In note below table, corrected last device part number to top boot. Table 7, Autoselect Codes: The SecSi Sector Indicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. Command Definitions Table 14, Command Definitions: The SecSi Sector In- dicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. AC Characteristics Read-only Operations table: Changed parameter tDF to 16 ns for all speed options. Added Note 3. Revision D+2 (September 4, 2000) Deleted remaining references to 80 ns speed option, which was officially removed in Revision D+1. Cor- rected references to Am29DL16xC, which officially changed to Am29DL16xD in Revision D. Revision D+3 (November 22, 2000) Global Deleted Preliminary status from document. Added table of contents. Revision E (July 2, 2001) Added Am29DL161D device to data sheet. Deleted extended temperature range devices. Sector/Sector Block Protection and Unprotection Noted that sectors are unprotected in parallel. SecSi‰ (Secured Silicon) Sector Flash Memory Region Noted changes for upcoming versions of these de- vices: reduced SecSi Sector size and deletion of SecSi Sector erase functionality. Current versions of these devices remain unaffected. Revision E+1 (July 29, 2002) Global Added 64-ball Fortified BGA package. Command Definitions Modified caution to state that incorrect command/se- quences may place device in unknown state, upon which device must be reset. Unlock Bypass Command Sequence; Command Definitions table Corrected table and description to indicated that bank address is not required for unlock bypass reset. Package Capacitance Added BGA capacitance specifications.
May 26, 2004 Am29DL16xD Revision E + 2 (February 14, 2003) Global Added VBF048 package, Very Thin Profile Fine Pitch Ball Grid Array, to Distinctive Characteristics, General Description, Ordering Information, Connection Dia- grams, and Physical Dimensions sections. Revision E+3 (February 25, 2004) AC Characteristics Corrected tSR/W in Figure 20, Back-to-back Read/Write Cycle Timings. Revision E+4 (May 26, 2004) Added Pb-Free OPNs. Trademarks Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.