CD4001B SS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 4
Technical content
www.siliconsupplies.com Die Size (Unsawn) 1050 x 1200 41 x 47 µm mils Minimum Bond Pad Size 100 x 100 3.94 x 3.94 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si CMOS High Voltage Logic – CD4001B Quad 2-Input NOR Gate Logic IC in bare die form High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1µA a t 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs. Rev 1.0 21/11/17 Features: Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request The CD4001B is fabricated using a 3µm 15CMOS process. The device has equal source and sink current capabilities and conforms to standard B series output drive. Device outputs are buffered which improves transfer characteristics by providing very high gain. The device is capable of driving x2 low power TTL loads or x1 LSTTL load.
Description
Ordering Information Die Dimensions in µm (mils) 1050 (41) 1200 (47) The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification A ll data sheet.com
d CMOS High Voltage Logic – CD4001B Rev 1.0 21/11/17 Pad Layout and Functions COORDINATES (mm) PAD FUNCTION X Y 1 1A 0.108 0.340 2 1B 0.165 0.108 3 1Y 0.362 0.108 4 2Y 0.566 0.108 5 2A 0.763 0.108 6 2B 0.820 0.340 7 VSS 0.785 0.542 8 3A 0.820 0.759 9 3B 0.763 0.991 10 3Y 0.566 0.991 11 4Y 0.362 0.991 12 4A 0.165 0.991 13 4B 0.108 0.759 14 VDD 0.108 0.548 CONNECT CHIP BACK TO VDD OR FLOAT Logic Diagram Pad 14 = VDD Pad 7 = VSS Truth Table INPUTS OUTPUT A B Y L L H H L H L H H L L L H = High level (steady state) L = Low level (steady state) 1050µm (41.34 mils) 11 10 9 1200µm (47.24 mils)
1 DIE ID
0,0
2 INPUT
www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com CMOS High Voltage Logic – CD4001B Rev 1.0 21/11/17 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VDD 3.0 18 V DC Input Voltage, Output Voltage VIN, VOUT 0 VDD V Operating Temperature Range TJ -55 +125 °C Recommended Operating Conditions3 (Voltages referenced to VSS) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to VSS) VDD -0.5 to +20 V DC Input or Output Voltage (Referenced to VSS) VIN, VOUT -0.5 to VDD+0.5 V Storage Temperature Range TSTG -65 to 150 °C Input Current or Output Current (per Pad) IIN, IOUT ±10 mA Power Dissipation in Still Air2 P D 750 mW LIMITS PARAMETER SYMBOL VDD CONDITIONS 25°C 85°C FULL RANGE4 UNITS 5V VOUT = 0.5V 3.5 3.5 3.5 10V VOUT = 1.0V 7 7 7 Minimum High-Level Input Voltage VIH 15V VOUT = 1.5V 11 11 11 V 10V VOUT = 0.5V or VDD -0.5V 3 3 3 Maximum Low-Level Input Voltage VIL 15V VOUT = 0.5V or VDD -0.5V 4 4 4 V 5V 4.95 4.95 4.95 10V 9.95 9.95 9.95 Minimum High-Level Output Voltage VOH 15V VIN = 0 or VDD 14.95 14.95 14.95 V 5V 0.05 0.05 0.05 10V 0.05 0.05 0.05 Maximum Low-Level Output Voltage VOL 15V VIN = VDD or 0 0.05 0.05 0.05 V Maximum Input Leakage Current IIN 18V VIN = VDD or VSS ±0.1 ±.0.1 ±1.0 µA 5V 0.25 7.5 7.5 10V 0.5 15 15 15V 1.0 30 30 Maximum Quiescent Supply Current IDD 20V VIN = VDD or VSS IOUT = 0µA 5.0 150 150 µA 3. This device contains protecti on circuitry against damage due to high static voltages or electric fields. However, any voltage higher than maximum rated voltages to this high-impedance circuit should be avoided. For proper operation, VIN & VOUT should be constrained to the range VSS ≤ (VIN or VOUT) 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. A ll data sheet.com
www.siliconsupplies.com CMOS High Voltage Logic – CD4001B Rev 1.0 21/11/17 LIMITS PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 5. Not production tested in die form, characterized by chip design and tested in package. SYMBOL VDD CONDITIONS UNITS FULL RANGE4 25°C 85°C VIN = VDD or VSS VOL = 0.4V 5V 0.51 0.42 0.36 VIN = VDD or VSS 10V VOL = 0.5V 1.3 1.1 0.9 Minimum Output Low (Sink) Current IOL VIN = VDD or VSS 15V VOL = 1.5V 3.4 2.8 2.4 mA VIN = VDD or VSS 5V VOH = 2.5V -1.6 -1.3 -1.15 5V VIN = VDD or VSS 10V VIN = VDD or VSS VOH = 9.5V -1.3 -1.1 -0.9 Minimum Output High (Source) Current mA IOH VIN = VDD or VSS 15V VOH = 13.5V -3.4 -2.8 -2.4 TYPICAL LIMITS PARAMETER SYMBOL VDD CONDITIONS UNITS -55°C to 25°C ≤ 85°C ≤ 125°C 5V 125 250 500 10V 60 100 200 Propagation Delay, CL = 50pF, Input A or B to Output Y (Figure 1) tPLH, tPHL 15V RL = 200kΩ ns tr = tf = 20ns 45 80 160 5V 100 200 400 10V 50 100 500 Output Transition CL = 50pF, Time, Any Output (Figure 1) tTLH, tTHL 15V RL = 200kΩ ns tr = tf = 20ns 40 80 160 CL = 50pF, Input Capacitance CIN - RL = 200kΩ tr = tf = 20ns 5 7.5 7.5 pF A ll data sheet.com