CCG2 CYPRESS | Alldatasheet
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Technical content
Datasheet sections
Features
■ 48-MHz ARM Cortex-M0 CPU ■ 32-KB Flash ■ 4-KB SRAM ■ In-system reprogrammable Integrated Digital Blocks ■ Integrated timers and counters to meet response times required by the USB-PD protocol ■ Run-time reconfigurable serial communication block (SCB) with reconfigurable I2C, SPI, or UART functionality Clocks and Oscillators ■ Integrated oscillator eliminating the need for external clock Type-C Support ■ Integrated transceiver (baseband PHY) ■ Integrated UFP (RD), EMCA (RA) termination resistors, and current sources for DFP (RP) ■ Supports one USB Type-C port Low-Power Operation ■ 2.7-V to 5.5-V operation ■ Two independent VCONN rails with integrated isolation between the two ■ Independent supply voltage pin for GPIO that allows 1.71-V to 5.5-V signaling on the I/Os ■ Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA System-Level ESD on CC and VCONN Pins ■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C Packages ■ 1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with 0.4-mm ball pitch ■ 2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN ■ 4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN ■ Supports industrial (40 °C to +85 °C) and extended industrial (40 °C to +105 °C) temperature ranges Logic Block Diagram Flash (32 KB) SRAM (4 KB) Serial Wire Debug Programmable IO Matrix CCG2: USB Type-C Cable Controller CORTEX-M0
48 MHz
I/O SubsystemMCU Subsystem Advanced High-Performance Bus (AHB) CC5 GPIO6 Port
1 Timer, counter, pulse-width modulation block
2 Serial communication block configurable as UART, SPI, or I2C
3 Termination resistor denoting a UFP
4 Termination resistor denoting an EMCA
5 Configuration Channel
6 General-purpose input/output
7 Current Sources to indicate a DFP
(I2C, SPI, UART) Integrated Rd 3, Ra and Rp VCONN1 VCONN2 VDDIO TCPWM1 SCB2 (I2C, SPI, UART)
EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 2 of 33 Available Firmware and Software Tools EZ-PD Configuration Utility The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through the process of configuring and programming the chip. The utility allows users to: 1. Select and configure the parameters they want to modify 2. Program the resulting configuration onto the target CCGx device. The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port controllers, will be provided in later versions of the utility. You can download the EZ-PD Configuration Utility and its associated documentation at the following link: http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility
Figure 1. EZ-PD CCG2 Block Diagram the main processor when the chip is in the Deep Sleep mode. for system functions requested by the user. two watchpoint (data) comparators.
2 X VCONN
range of current capacity on VBUS defined in the Type-C spec. respond to SOP, SOP', or SOP” messaging. Approximation Register) ADC for analog to digital conversions. not available to connect to the mux busses. Figure 2. USB-PD Subsystem transitions between which are managed by the power system. Oscillator (IMO) and the Internal Low-power Oscillator (ILO).
EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 6 of 33 Peripherals Serial Communication Blocks (SCB) EZ-PD CCG2 has two SCBs, which can be configured to implement an I2C, SPI, or UART interface. The hardware I2C blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the SPI mode, the SCB blocks can be configured to act as master or slave. In the I2C mode, the SCB blocks are capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and have flexible buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I 2C that creates a mailbox address range in the memory of EZ-PD CCG2 and effectively reduce I2C communication to reading from and writing to an array in memory. In addition, the blocks support 8-deep FIFOs for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduce the need for clock stretching caused by the CPU not having read data on time. The I 2C peripherals are compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/Os are implemented with GPIO in open-drain modes. The I2C port on SCB 1 block of EZ-PD CCG2 is not completely compliant with the I2C spec in the following respects: ■ The GPIO cells for SCB 1's I2C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the bus load. Timer/Counter/PWM Block (TCPWM) EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadrature signals. GPIO EZ-PD CCG2 has up to 10 GPIOs in addition to the I2C and SWD pins, which can also be used as GPIOs. The I2C pins from SCB 0 are overvoltage-tolerant. The number of available GPIOs vary with the package. The GPIO block implements the following: ■ Seven drive strength modes: ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL) ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode) ■ Selectable slew rates for dV/dt related noise control to improve EMI During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin.
EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 7 of 33 Pinouts Group Name Pin Map 24-QFN Ball Location 20-CSP Pin Map 14-DFN Description USB Type-C Port CC1 2 B4 3 USB PD connector detect/Configuration Channel 1 CC2 1 A4 N/A USB PD connector detect/Configuration Channel 2 RD1 3 B3 N/A Dedicated Rd resistor pin for CC1 Must be left open for cable applications and connected together with CC1 ball for UFP or DFP with dead battery
applications
N/A GPIO / SPI_0_CLK / UART_0_ RX GPIO 18 D3 13 GPIO / SPI_0_MOSI / UART_0_TX GPIO 13 C2 10 GPIO / I2C_1_SDA / SPI_1_MISO / UART_1_RX GPIO 10 D2 N/A GPIO / I2C_1_SCL / SPI_1_CLK / UART_1_TX GPIO 15 B2 11 GPIO / SPI_1_SEL / UART_1_RTS GPIO 14 N/A N/A GPIO GPIO 17 N/A N/A GPIO GPIO 21 N/A N/A GPIO GPIO 23 N/A N/A GPIO GPIO 24 N/A N/A GPIO I2C_0_SCL 20 A3 1 GPIO / I2C_0_SCL / SPI_0_MISO / UART_0_RTS I2C_0_SDA 19 A2 14 GPIO / I2C_0_SDA / SPI_0_SEL / UART_0_CTS SWD _IO 11 E2 8 SWD IO / GPIO / UART_1_CTS / SPI_1_MOSI SWD_CLK 12 D1 9 SWD clock / GPIO RESET XRES 16 B1 12 Reset input POWER VCONN1 5 E4 5 VCONN 1 input (4.0 V to 5.5 V) VCONN2 4 C4 4 VCONN 2 input (4.0 V to 5.5 V) VDDIO 8 E1 N/A 1.71-V to 5.5-V supply for I/Os VCCD 7 A1 6 1.8-V regulator output for filter capacitor VDDD 9 E3 7 VDDD supply input/output (2.7 V to 5.5 V) VDDD 6 VDDD supply input/output (2.7 V to 5.5 V) VSS EPAD N/A EPAD Ground supply VSS D4 Ground supply VSS C1 Ground supply
Table 1. Absolute Maximum Ratings[1]
- Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Table 2. DC Specifications
Table 3. AC Specifications Table 4. I/O DC Specifications
- V IH must not exceed VDDIO + 0.2 V.
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Table 5. I/O AC Specifications Table 6. XRES DC Specifications Table 7. PWM AC Specifications
Table 8. Fixed I2C DC Specifications Table 9. Fixed I2C AC Specifications Table 10. Fixed UART DC Specifications
100 Kbps – – 125 µA Guaranteed by
1000 Kbps – – 312 µA Guaranteed by
Table 11. Fixed UART AC Specifications Table 12. Fixed SPI DC Specifications Table 13. Fixed SPI AC Specifications
Table 14. Fixed SPI Master Mode AC Specifications Table 15. Fixed SPI Slave Mode AC Specifications Table 16. Flash AC Specifications
- It can take as much as 20 milliseconds to write to Flash. Du ring this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
Table 17. Imprecise Power On Reset (PRES) Table 18. Precise Power On Reset (POR) Table 19. SWD Interface Specifications Table 20. IMO DC Specifications Table 21. IMO AC Specifications
Table 22. ILO DC Specifications Table 23. ILO AC Specifications Table 24. PD DC Specifications
2.7 V applied at VCONN1
Table 25. ADC DC Specifications Table 26. ADC AC Specifications
EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 26 of 33
Ordering Information
The EZ-PD CCG2 part numbers and features are listed in Table 27. Ordering Code Definitions Table 27. EZ-PD CCG2 Ordering Information
- Termination resistor denoting an EMCA.
- Termination resistor denoting an accessory or upstream facing port.
- Termination resistor denoting a downstream facing port.
Figure 15. 20-ball WLCSP (1.63 × 2.03 × 0.55 mm) FN20B Package Outline, 001-95010 Table 28. Package Characteristics Table 29. Solder Reflow Peak Temperature Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
- REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
- ALL DIMENSIONS ARE IN MILLIMETERS
Table 31. Acronyms Used in this Document
100 W of power
Table 31. Acronyms Used in this Document (continued)
Table 32. Units of Measure Table 32. Units of Measure (continued)
EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 31 of 33 References and Links To Applications Collaterals Knowledge Base Articles ■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and CCG4 - KBA210740 ■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™ CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477 ■ CCGX Frequently Asked Questions (FAQs) - KBA97244 ■ Handling Precautions for CY4501 CCG1 DVK - KBA210560 ■ Cypress EZ-PD™ CCGx Hardware - KBA204102 ■ Difference between USB Type-C and USB-PD - KBA204033 ■ CCGx Programming Methods - KBA97271 ■ Getting started with Cypress USB Type-C Products - KBA04071 ■ Type-C to DisplayPort Cable Electrical Requirements ■ Dead Battery Charging Implementation in USB Type-C Solutions - KBA97273 ■ Termination Resistors Required for the USB Type-C Connector – KBA97180 ■ VBUS Bypass Capacitor Recommendation for Type-C Cable and Type-C to Legacy Cable/Adapter Assemblies – KBA97270 ■ Need for Regulator and Auxiliary Switch in Type-C to DisplayPort (DP) Cable Solution - KBA97274 ■ Need for a USB Billboard Device in Type-C Solutions – KBA97146 ■ CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies – KBA97145 ■ Cypress USB Type-C Controller Supported Solutions – KBA97179 ■ Termination Resistors for Type-C to Legacy Ports – KBA97272 ■ Handling Instructions for CY4502 CCG2 Development Kit – KBA97916 ■ Thunderbolt™ Cable Application Using CCG3 Devices - KBA210976 ■ Power Adapter Application Using CCG3 Devices - KBA210975 ■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974 ■ Device Flash Memory Size and Advantages - KBA210973 ■ Applications of EZ-PD™ CCG4 - KBA210739 Application Notes ■ AN96527 - Designing USB Type-C Products Using Cypress’s CCG1 Controllers ■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™ CCG2 ■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2 ■ AN210403 - Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C Controllers ■ AN210771 - Getting Started with EZ-PD™ CCG4 Reference Designs ■ EZ-PD™ CCG2 Electronically Marked Cable Assembly (EMCA) Paddle Card Reference Design ■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution ■ CCG1 USB Type-C to DisplayPort Cable Solution ■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution ■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution ■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle Card Reference Design ■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card Reference Schematics ■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle ■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution ■ CCG2 20W Power Adapter Reference Design ■ CCG2 18W Power Adapter Reference Design ■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference Design Kit Kits ■ CY4501 CCG1 Development Kit ■ CY4502 EZ-PD™ CCG2 Development Kit ■ CY4531 EZ-PD CCG3 Evaluation Kit ■ CY4541 EZ-PD™ CCG4 Evaluation Kit Datasheets ■ CCG1 Datasheet: USB Type-C Port Controller with Power Delivery ■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode Controller on Type-C ■ CCG3: USB Type-C Controller Datasheet ■ CCG4: Two-Port USB Type-C Controller Datasheet
EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 32 of 33 Document History Page Description Title: EZ-PD™ CCG2 Dat asheet USB Type-C Port Controller Document Number: 001-93912 Revision ECN Orig. of Change Submission Date Description of Change *E 4680071 GAYA 03/07/2015 Release to web *F 4718374 AKN 04/09/2015 Added 24-pin QFN pin and package information. Added DRP and DFP Application diagrams *G 4774142 AKN 06/15/2015 Changed datasheet status from Preliminary to Final. Updated Logic Block Diagram. Changed number of GPIOs to 10 and added a note about the number of GPIOs varying depending on the package. Updated Power and Digital Peripherals section. Updated Application diagrams. Added SID.PWR#1_A parameter. Added CYPD2122-20FNXIT part in Ordering Information. Removed Errata. *H 4979175 VGT 10/23/2015 Updated Figure 1 and Figure 5. Added VCC_ABS spec and updated the SID.ADC.4 parameter. Added “Guaranteed by characterization” note for the following specs: SID.GIO#16, SID.GIO#17, SID.XRES#3, SID 160 to SID 172A, SID 2226, SID *I 5028128 VGT 12/04/2015 Updated Application Diagrams: Added Figure 12. Added Figure 13. Added Figure 14. Updated Ordering Information. Added part numbers CYPD2119-24LQXIT, CYPD2120-24LQXIT, CYPD2121-24LQXIT, CYPD2125-24LQXIT. *J 5186972 VGT 03/28/2016 Updated temperature ranges in Features. Updated Table 28. Updated Ordering Information. *K 5303957 VGT 06/13/2016 Added Available Firmware and Software Tools. Updated Figure 8: Per the USB PD3.0 spec, SOP” implementation is no longer valid for passive cables. Updated Figure 9, Figure 10, and Figure 11. Added descriptive notes for the application diagrams. Added References and Links To Applications Collaterals. Updated Ordering Information. Updated Cypress logo and copyright information. *L 5387677 VGT 08/02/2016 Added CYPD2122-24LQXI part number in Ordering Information.
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