CCG1

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Features

■ 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB SRAM Integrated analog blocks ■ 12-bit, 1-Msps ADC for VBUS voltage and current monitoring ■ Dynamic overcurrent and overvoltage protection Integrated digital blocks ■ Two configurable 16-bit TCPWM blocks ■ One I2C master or slave Type-C Support ■ Integrated transceiver (BB PHY) ■ Supports up to two USB ports with PD ■ Supports routing of all protocols through an external mux PD Support ■ Supports Provider and Consumer roles ■ Supports all power profiles Low-Power Operation ■ 3.2 V to 5.5 V operation ■ Sleep 1.3 mA, Deep Sleep 1.3 A[1] Packages ■ 40-pin QFN ■ 16-pin SOIC ■ 35-ball wafer-level CSP (WLCSP) Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]

1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I
4. Termination resistor denoting a Downstream Facing Port (DFP).
5. Termination resistor denoting a Upstream Facing Port (UFP).
6. Termination resistor denoting an Electron ically Marked Cable Assembly (EMCA).

Document Number: 001-93639 Rev. *K Page 3 of 31 CCG1 Datasheet Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a 2-wire form of JTAG; the debug configuration used for CCG1 has four break-point (address) comparators and two watchpoint (data) comparators. Flash The CCG1 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. SROM A supervisory ROM that contains boot and configuration routines is provided. System Resources Power System The power system is described in detail in the section Power on page 11. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The CCG1 operates with a single external supply over the range of 3.2 V to 5.5 V operation and has three different power modes: Active, Sleep, and Deep Sleep; transitions between modes are managed by the power system. Serial Communication Blocks (SCB) The CCG1 has one SCB, which can implement an I 2C interface. The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZ-I 2C that creates a mailbox address range in the memory of the CCG1 and effec- tively reduces I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I 2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices, as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The CCG1 is not completely compliant with the I2C spec in the following respects: ■ GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. ■ When the SCB is an I2C Master, it interposes an IDLE state between NACK and Repeated Start; the I2C spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. ■ When the SCB is in the I2C Slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. GPIO The CCG1 has up to 30 GPIOs, which are configured for various functions. Refer to the pinout tables for the definitions. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode). ■ Selectable slew rates for dV/dt related noise control to improve EMI. During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network, known as a high-speed I/O matrix, is used to multiplex between various signals that may connect to an I/O pin.

Table 1. Pin Definitions for 35-ball WLCSP for EMCA Cable Application

applications. Refer to Table 23 on page 23 for part numbers to package mapping. Table 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications

1. Pinout for Notebook DRP application for 40-QFN.
2. Pinout for Monitor DRP application for 40-QFN.
3. Pinout for Notebook DRP application for 35-CSP .

Table 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications (continued)

1. Pinout for Notebook DRP application for 40-QFN.
2. Pinout for Monitor DRP application for 40-QFN.
3. Pinout for Notebook DRP application for 35-CSP .

Table 3. Pin Definitions for 40-Pin QFN for Notebook (DFP)

CC1_LPREF – Analog input 23 I Reference signal for internal use. CC2_LPREF – Analog input 25 I Reference signal for internal use. Table 3. Pin Definitions for 40-Pin QFN for Notebook (DFP) (continued)

Table 4. Pin Definitions for 16-pin SOIC for Power Adapter Application

Figure 2. Pinout for CYPD1122-40LQXI/CYPD1121-40LQXI Figure 3. Pinout for CYPD1134-40LQXI Figure 4. Pinout for CYPD1132-16SXI

16 SWD_IO

13 VSEL1

11 CC_CTRL

Figure 5. Pinout for CYPD1103-35FNXIT/CYPD1131-FNXIT mode. There is a separate low-noise regulator for the bandgap. circuits operating over that range. Refer to Application Diagrams for bypassing schemes.

depending on the type of application.

1. Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Table 5. Absolute Maximum Ratings[11] Table 6. DC Specifications

Table 7. AC Specifications

1. VIH must not exceed VDDD + 0.2 V.

Table 8. I/O DC Specifications Table 9. I/O AC Specifications

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Table 10. XRES DC Specifications Table 11. PWM AC Specifications

Table 12. Fixed I2C DC Specifications Table 13. Fixed I2C AC Specifications Table 14. Flash DC Specifications

1. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.

1. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C

ambient temperature range. Contact customercare@cypress.com. Table 15. Flash AC Specifications

Table 16. Imprecise Power On Reset (PRES) Table 17. Precise Power On Reset (POR) Table 18. SWD Interface Specifications Table 19. IMO DC Specifications Table 20. IMO AC Specifications

Table 21. ILO DC Specifications Table 22. ILO AC Specifications

Figure 6. Single Chip/Cable, Component Count = 19

Figure 9. Notebook (DRP) Application Diagram

5 Volts

Figure 10. Notebook (DFP) Application Diagram

349 VBUS_VMON

Figure 11. Monitor Application Block Diagram

Document Number: 001-93639 Rev. *K Page 23 of 31 CCG1 Datasheet

Ordering Information

The CCG1 part numbers and features are listed in the following table. Ordering Code Definitions Table 23. CCG1 Ordering Information

1. Number of USB Type-C Ports supported .
2. Default VCONN termination.
3. Type-C Cable Termination.

Table 24. Package Characteristics Table 25. Solder Reflow Peak Temperature Table 26. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Figure 14. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068

Table 27. Acronyms Used in this Document capabilities, no analog. See GPIO. Table 27. Acronyms Used in this Document (continued)

Table 28. Units of Measure

Document Number: 001-93639 Rev. *K Page 29 of 31 CCG1 Datasheet

Revision History

Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery Document Number: 001-93639 Revision ECN Orig. of Change Submission Date Description of Change ** 4520316 MSMI 09/30/2014 New datasheet *A 4531795 SJH 10/13/2014 Updated Functional Definition. Updated Figure 8, Figure , Figure 7, Figure , Figure 14, Figure 9. Added Figure 11. Updated Pinouts. Updated Power. Updated Figure , Figure 8. Updated Ordering Information Added Note 24 and referred the same note in 40-pin QFN corresponding to CYPD1122-40LQXI. Added Note 27 and referred the same note in 40-pin QFN corresponding to CYPD1134-40LQXI. *B 4569912 SJH 11/21/2014 Updated Features. Added 16-pin SOIC related information. Updated Functional Definition. Updated Pin Definitions. Added Table 2. Updated Pinouts. Updated Figure 2, Figure 5. Added Figure 4. Updated Power. Updated Figure , Figure 8. Added Figure 6. Updated Electrical Specifications. Updated Device-Level Specifications. Updated Memory. Added Note 14 and referred the same note in F RET parameter. Added details corresponding to spec ID SID182B under FRET parameter. Updated Figure 14, Figure 9, Figure 11. Added Figure 8 and Figure 10. Updated Ordering Information. Updated part numbers. Added a column “Si ID”. Updated Packaging. Updated Table 24. Updated details in maximum value column corresponding to T A and TJ parameters. Added 16-pin SOIC related information. Updated Table 25. *C 4596141 SJH 12/14/2014 Updated Figure 6, Figure 14, Figure 16. Updated Table 8, Table 23. *D 4646123 SJH 02/04/2015 Updated pin definitions for 40-pin QFN and 35-ball WLCSP. Updated Pinout for CYPD1122-40LQXI/CYPD1121-40LQXI and Ordering Information. Updated conditions for Device-Level Specifications. Updated diagrams in Applications in Detail section. *E 4686050 VGT 03/13/2015 Removed information about 28-pin SSOP. Updated Table 3, Table 23, Table 24, Table 25, Table 26, Table 27. Updated Figure 2, Figure . *F 4747272 VGT 05/13//2015 Updated General Description. Added Note 1 and referenced it in Features. Updated Figure 6, Figure 8 through Figure 11. Removed Figure 9. Single Chip/Cable, Component Count = 13. Removed Figure 11. Two Chip/Cable, Component Count = 11/paddle.

Document Number: 001-93639 Rev. *K Page 30 of 31 CCG1 Datasheet *G 4800534 VGT 07/02/2015 Updated Low-Power Operation. Updated the number of GPIOs to “up to 30” in GPIO. Updated “1.8 to 5.5 V” to “3.2 V to 5.5 V” in Low-Power Operation, Power System, Power, Device-Level Specifications and Note 15. Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 14 and Table 18. Added table footnotes 8, 9 and 10. Deleted footnotes 25 through 28. Updated Figure 2 and Figure 8 through Figure 11. Added Figure 3. Updated the following in Power: Removed Figures 5 through 8. Updated the section. *H 4939764 VGT 09/29/2015 Removed specs SID241 and 242. Updated 40-pin QFN package to current revision. *I 5179365 KISB 03/17/2016 Updated max value of I I2C1 from 10.50 µA to 50 µA. Updated copyright information and sales links at the end of the document. *J 5459633 VGT 10/03/2016 Added compliance information regarding the USB Specification. Updated copyright notice to include WICED. Added IoT link in Sales, Solutions, and Legal Information. *K 5725038 VGT 05/03/2017 Updated Cypress logo. Updated Copyright information. Revision History (continued) Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery Document Number: 001-93639 Revision ECN Orig. of Change Submission Date Description of Change

Document Number: 001-93639 Rev. *K Revised May 3, 2017 Page 31 of 31 © Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. 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