CAT93C46RXI-G2

CAT93C46R CATALYST | Alldatasheet

Document overview

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Technical content

© 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1107, Rev. F

FEATURES

I High speed operation: 4MHz @ 5V, 2MHz @ 1.8V I 1.8V to 5.5V supply voltage range I Selectable x8 or x16 memory organization I Sequential read I Software write protection I Power-up inadvertent write protection I Low power CMOS technology I 1,000,000 program/erase cycles I 100 year data retention I Industrial temperature range I RoHS-compliant 8-pin PDIP , SOIC, TSSOP and 8-pad TDFN packages PIN CONFIGURATION

DESCRIPTION

The CAT93C46R is a 1-Kb CMOS Serial EEPROM device which is organized as either 64 registers of 16 bits or 128 registers of 8 bits, as determined by the state of the ORG pin. The CAT93C46R features sequential read and self-timed internal write with auto- clear. On-chip Power-On Reset circuitry protects the internal logic against powering up in the wrong state. In contrast to the CAT93C46, the CAT93C46R features an internal instruction clock counter which provides improved noise immunity for Write/Erase commands. FUNCTIONAL SYMBOL Note: When the ORG pin is connected to V CC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pull-up device will select the x16 organization. CS SK DI ORG DO VCC GND CAT93C46R PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization NC No Connection CAT93C46R 1-Kb Microwire Serial EEPROM PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2) SOIC (W) VCC NC ORG GND DI CS SK DO ORG GND DO DI CS NC VCC SK For Ordering Information details, see page 12. * The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu pre-plated lead frames.

2Doc. No. 1107, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol Parameter Test Conditions Min Max Units ICC1 Power Supply Current f SK = 1MHz 1 mA (Write) V CC = 5.0V ICC2 Power Supply Current f SK = 1MHz 500 µA (Read) V CC = 5.0V ISB1 Power Supply Current CS = 0V 10 µA (Standby) (x8 Mode) ORG = GND ISB2 Power Supply Current CS = 0V 10 µA (Standby) (x16Mode) ORG = Float or V CC ILI Input Leakage Current V IN = 0V to VCC 2 µA ILO Output Leakage Current V OUT = 0V to VCC,2 µA (Including ORG pin) CS = 0V VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 V CC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 V CC x 0.2 V VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V V CC x 0.7 V CC+1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V 0.4 V IOL = 2.1mA VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V 2.4 V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V 0.2 V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V V CC - 0.2 V IOH = -100µA ABSOLUTE MAXIMUM RATINGS (1) Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground (2) -0.5 V to +6.5 V RELIABILITY CHARACTERISTICS (3) lobmySr etemaraPn iMs tinU N DNE )4( ecnarudnE0 00,000,1s elcyCesarE/margorP T RD noitneteRataD0 01s raeY Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than V CC +0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC +1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropria te AEC-Q100 and JEDEC test methods. (4) Block Mode, V CC = 5V, TA = 25°C.

3 Doc No. 1107, Rev. F© 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice PIN CAPACITANCE Symbol Test Conditions Max Units COUT(1) Output Capacitance (DO) V OUT = 0V 5 pF CIN(1) Input Capacitance (CS, SK, DI, ORG) V IN = 0V 5 pF VCC = 1.8V- 5.5V V CC = 4.5V- 5.5V Symbol Parameter Min Max Min Max Units tCSS CS Setup Time 50 50 ns tCSH CS Hold Time 0 0 ns tDIS DI Setup Time 100 50 ns tDIH DI Hold Time 100 50 ns tPD1 Output Delay to 1 0.25 0.1 µs tPD0 Output Delay to 0 0.25 0.1 µs tHZ(1) Output Delay to High-Z 100 100 ns tEW Program/Erase Pulse Width 5 5 ms tCSMIN Minimum CS Low Time 0.25 0.1 µs tSKHI Minimum SK High Time 0.25 0.1 µs tSKLOW Minimum SK Low Time 0.25 0.1 µs tSV Output Delay to Status Valid 0.25 0.1 µs SKMAX Maximum Clock Frequency DC 2 DC 4 MHz A.C. CHARACTERISTICS(2) NOTE: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropria te AEC-Q100 and JEDEC test methods. (2) Test conditions according to “A.C. Test Conditions” table. (3) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V Input Pulse Voltages 0.2V CC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V Timing Reference Voltages 0.5V CC 1.8V ≤ VCC ≤ 4.5V Output Load Current Source I OLmax/IOHmax; CL = 100pF POWER-UP TIMING (1)(3) Symbol Parameter Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms

4Doc. No. 1107, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice DEVICE OPERATION The CAT93C46R is a 1024-bit nonvolatile memory intended for use with industry standard microproces- sors. The CAT93C46R can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The CAT93C46R oper- ates on a single power supply and will generate on chip the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applica- tions where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization). Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C46R will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (t PD0 or tPD1). Sequential Read After the 1st data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the CAT93C46R will automatically increment to the next address and shift out the next data word. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential Read mode, only the initial data word is preceeded by a dummy zero bit; all subsequent data words will follow without a dummy zero bit. Erase/Write Enable and Disable The CAT93C46R powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46R write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. INSTRUCTION SET noitcurtsnIt iBtratSe docpO sserddAa taD stnemmoC8x6 1x8 x6 1x DAER1 0 10 A-6A0 A-5A0 A–NAsserddAdaeR ESARE1 1 10 A-6A0 A-5A0 A–NAsserddAraelC ETIRW1 1 00 A-6A0 A-5A0 D-7D0 D-51D0 A–NAsserddAetirW NEWE1 0 0 XXXXX11X XXX11 elbanEetirW SDWE1 0 0 XXXXX00X XXX00 elbasiDetirW LARE1 0 0 XXXXX01X XXX01 sesserddAllAraelC LARW1 0 0 XXXXX10X XXX10 0D-7D0 D-51Ds esserddAllAetirW

6Doc. No. 1107, Rev. F © 2006 by Catalyst Semiconductor, Inc. Figure 4. Write Instruction Timing after the device has entered the self clocking mode. clocking clear cycle of the selected memory location. memory bits return to a logical “1” state. has entered the self clocking mode. the WRAL command is executed.

8Doc. No. 1107, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD 300 MIL WIDE PLASTIC DIP (L) A e b L E D eB 24C16_8-LEAD_DIP_(300P).eps SYMBOL A b D E e eB L MIN 0.38 0.36 9.02 7.62 6.09 6.35 7.87 0.115 0.130 0.150 NOM 0.46 1.771.14 7.87

2.54 BSC

4.57 A2 3.05 3.81 0.56 10.16 8.25 7.11 9.65 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982

9 Doc No. 1107, Rev. F© 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD 150 MIL WIDE SOIC (V, W) 24C16_8-LEAD_SOIC.eps SYMBOL A b C D E h L MIN 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 NOM 0.250.19 MAX 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 BSC 0.50 1.27 θ10 ° 8° E D A1e L C b h x 45 A Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012. For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

10Doc. No. 1107, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD TSSOP (Y) 8 5 1 4 E E1 E/2 PIN #1 IDENT. D b L e A SEE DETAIL A SEE DETAIL A SEATING PLANE c GAGE PLANE 0.25 SYMBOL A b c D E e L MIN 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 NOM 0.90 0.300.19 3.00 4.40 0.60 0.750.50 MAX 1.20 0.15 1.05 0.20 3.10 6.50 4.50

0.65 BSC

Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-153 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

11 Doc No. 1107, Rev. F© 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice E PIN 1 INDEX AREA L TDFN2X3 (03).eps PIN 1 ID e b 3 x e D A SYMBOL A b D E e L MIN 0.70 0.00 0.45 0.20 1.90 1.30 1.40 2.90 1.20 0.20 0.30 0.40 NOM 0.75 0.02 0.55

0.20 REF

0.25 2.00 3.00

0.50 TYP

0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.401.30 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-229. For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. 8-PAD TDFN 2X3 PACKAGE (VP2)

12Doc. No. 1107, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

ORDERING INFORMATION

Prefix Device # Suffix 93C46R V I Product Number 93C46R CAT Temperature Range I = Industrial (-40°C - 85°C) Optional Company ID Package L = PDIP V = SOIC, JEDEC W = SOIC, JEDEC X = SOIC, EIAJ (4) Y = TSSOP VP2 = TDFN (2X3mm) Tape & Reel T: Tape & Reel 2: 2000/Reel(4) 3: 3000/Reel Lead Finish G: NiPdAu T3– G Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT93C46RVI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C46R XI-T2. (5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.

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REVISION HISTORY

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