CAT93CXXXX CATALYST | Alldatasheet
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CAT93CXXXX (1K-16K) Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
DESCRIPTION
The CAT93CXXXX is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The serial EEPROM memory of the 93CXXXX can be configured either by 16- bits or by 8-bits. Each register can be written (or read) by using the DI (or DO pin). The reset function of the 93CXXXX protects the system during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. Catalyst's advanced CMOS technology substantially reduces device power requirements. The 93CXXXX is available in 8-pin DIP, 8- pin TSSOP or 8-pin SOIC packages. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. PIN CONFIGURATION BLOCK DIAGRAM PIN FUNCTIONS Pin Name Function CS Chip Select RESET/RESET Reset I/O SK Clock Input DI Serial Data Input DO Serial Data Output VCC +2.7 to 6.0V Power Supply GND Ground ORG Memory Organization Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization. 93CX61X 93CX62X 93CX63X
FEATURES
n Programmable Reset Threshold n Built-in Inadvertent Write Protection —V CC Lock Out n High Speed Operation: 3MHz n Low Power CMOS Technology n x 16 or x 8 Selectable Serial Memory n Self-Timed Write Cycle with Auto-Clear n Sequential Read n Fast Nonvolatile Write Cycle: 3ms Max n Active High or Low Reset Outputs —Precision Power Supply Voltage Monitoring —5V, 3.3V and 3V options n Hardware and Software Write Protection n Power-Up Inadvertant Write Protection n 1,000,000 Program/Erase Cycles n 100 Year Data Retention n Commercial, Industrial, and Automotive Temperature Ranges n 2.7-6.0 Volt Operation n 16 Byte Page Mode Advanced Information CS SK DI DO VCC RESET( RESET) ORG GND CS SK DI DO VCC WDI GND RESET( RESET) CS SK DI DO VCC RESET GND RESET VCC ADDRESS DECODERMEMORY ARRAY DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR OUTPUT BUFFER DOSK CS DI ORG GND RESET Controller High Precision Vcc Monitor WDI RESET/ RESET WATCHDOG © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Advanced InformationCAT93CXXXX Stock No. 21084-01 2/98 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. D.C. OPERATING CHARACTERISTICS VCC = +2.7V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current 3 mA f SK = 1MHz (Write) V CC = 5.0V ICC2 Power Supply Current 1 mA f SK = 1MHz (Read) V CC = 5.0V ISB1 Power Supply Current 10 µA CS = 0V (Standby) (x8 Mode) ORG=GND ISB2 Power Supply Current 0 µA CS=0V (Standby) (x16Mode) ORG=Float or V CC ILI Input Leakage Current 1 µAV IN = 0V to VCC ILO Output Leakage Current 1 µAV OUT = 0V to VCC , (Including ORG pin) CS = 0V VIL1 Input Low Voltage -0.1 0.8 V 4.5V ≤VCC <5.5V VIH1 Input High Voltage 2 V CC +1 V VOL1 Output Low Voltage 0.4 V 4.5V ≤VCC <5.5V VOH1 Output High Voltage 2.4 I OL = 2.1mA VI OH = -400µA
Stock No. 21084-01 2/98 Advanced Information A.C. CHARACTERISTICS VCC =2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF Power-Up Timing(1)(2) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Limits VCC =V CC = 2.7V -6V 4.5V-5.5V Test SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions tCSS CS Setup Time 250 50 ns tCSH CS Hold Time 0 0 ns tDIS DI Setup Time 250 50 ns tDIH DI Hold Time 250 50 ns tPD1 Output Delay to 1 0.5 0.1 µs tPD0 Output Delay to 0 0.5 0.1 µs tHZ (1) Output Delay to High-Z 500 100 ns tEW Program/Erase Pulse Width 5 5 ms tCSMIN Minimum CS Low Time 0.5 0.1 µs tSKHI Minimum SK High Time 0.5 0.1 µs tSKLOW Minimum SK Low Time 0.5 0.1 µs tSV Output Delay to Status Valid 0.5 0.1 µs SK MAX Maximum Clock Frequency DC 1000 DC 3000 KHZ C L = 100pF CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(1) Input/Output Capacitance 8 pF V I/O = 0V CIN(1) Input Capacitance 6 pF V IN = 0V RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method NEND (1) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (1) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (1)(3) Latch-up 100 mA JEDEC Standard 17
Advanced InformationCAT93CXXXX Stock No. 21084-01 2/98 INSTRUCTION SET InstructionDevice Start Opcode Address Data Comments Type Bit x8 x16 x8 x16 READ 93C46XX 1 10 A6–A0 A5-A0 Read Address AN–A0 93C56XX(1) 1 10 A8–A0 A7-A0 93C66XX 1 10 A8–A0 A7-A0 93C57XX 1 10 A7-A0 A6-A0 93C86XX 1 10 A10-A0 A9-A0 ERASE 93C46XX 1 11 A6–A0 A5-A0 Clear Address AN–A0 93C56XX(1) 1 11 A8–A0 A7-A0 93C66XX 1 11 A8–A0 A7-A0 93C57XX 1 11 A7-A0 A6-A0 93C86XX 1 11 A10-A0 A9-A0 WRITE 93C46XX 1 01 A6–A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0 93C56XX(1) 1 01 A8–A0 A7-A0 D7-D0 D15-D0 93C66XX 1 01 A8–A0 A7-A0 D7-D0 D15-D0 93C57XX 1 01 A7-A0 A6-A0 D7-D0 D15-D0 93C86XX 1 01 A10-A0 A9-A0 D7-D0 D15-D0 EWEN 93C46XX 1 00 11XXXXX 11XXXX Write Enable 93C56XX 1 00 11XXXXXXX 11XXXXXX 93C66XX 1 00 11XXXXXXX 11XXXXXX 93C57XX 1 00 11XXXXXX 11XXXXX 93C86XX 1 00 11XXXXXXXXX 11XXXXXXXX EWDS 93C46XX 1 00 00XXXXX 00XXXX Write Disable 93C56XX 1 00 00XXXXXXX 00XXXXXX 93C66XX 1 00 00XXXXXXX 00XXXXXX 93C57XX 1 00 00XXXXXX 00XXXXX 93C86XX 1 00 00XXXXXXXXX 00XXXXXXXX ERAL 93C46XX 1 00 10XXXXX 10XXXX Clear All Addresses 93C56XX 1 00 10XXXXXXX 10XXXXXX 93C66XX 1 00 10XXXXXXX 10XXXXXX 93C57XX 1 00 10XXXXXX 10XXXXX 93C86XX 1 00 10XXXXXXXXX 10XXXXXXXX WRAL 93C46XX 1 00 01XXXXX 01XXXX D7-D0 D15-D0 Write All Addresses 93C56XX 1 00 01XXXXXXX 01XXXXXX D7-D0 D15-D0 93C66XX 1 00 01XXXXXXX 01XXXXXX D7-D0 D15-D0 93C57XX 1 00 01XXXXXX 01XXXXX D7-D0 D15-D0 93C86XX 1 00 01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0 Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands.
Figure 1. RESET Output Timing
Advanced InformationCAT93CXXXX Stock No. 21084-01 2/98 DEVICE OPERATION Reset Controller Description The CAT93CXXXX provides a precision RESET con- troller that ensures correct system operation during brown-out and power-up/down conditions. It is config- ured with open drain RESET outputs. During power- up, the RESET outputs remain active until V CC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST ) after reach- ing VTH. After the tPURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when V CC falls below VTH. The RESET outputs will be valid so long as VCC is >1.0V (VRVALID ). The RESET pins are I/Os; therefore, the CAT93CXXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 93CXXXX will initiate a reset timeout after detecting a high and the RESET input in the 93CXXXX will initiate a reset timeout after detecting a low. Watchdog Timer The Watchdog Timer provides an independent protec- tion for microcontrollers. During a system failure, the CAT93CXXXX will respond with a reset signal after a time-out interval of 1.6 seconds for lack of activity. As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. Hardware Data Protection The 93CXXXX is designed with a VCC lock out data protection feature to provide a high degree of data integrity. The V CC sense provides write protection when VCC falls below the reset threshold value. The VCC lock out inhibits writes to the serial EEPROM whenever VCC falls below (power down) or until VCC reaches the reset threshold (power up). Reset Threshold Voltage From the factory the 93CXXXX is offered in five differ- ent variations of reset threshold voltages. They are 2.55-2.70V. To provide added flexibility to design engineers using this product, the 93CXXXX is de- signed with an additional feature of programming the reset threshold voltage. This allows the user to change the existing reset threshold voltage to one of the other four reset threshold voltages. Once the reset threshold voltage is selected it will not change even after cycling the power, unless the user uses the programmer to change the reset threshold voltage. However, the programming function is available only through external program manufacturers. Please call Catalyst for a list of programmer manufacturers which support this function. Memory Functional Description The CAT93CXXXX is a 1024/2048/4096/16,384-bit non- volatile memory intended for use with industry standard microprocessors. The CAT93CXXXX can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions for 93C46XX; seven 10-bit instructions for 93C57XX; seven 11-bit instructions for 93C56XX and 93C66XX; seven 13-bit instructions for 93C86XX; control the reading, writing and erase opera- tions of the device. When organized as X8, seven 10-bit instructions for 93C46XX; seven 11-bit instructions for 93C57; seven 12-bit instructions for 93C56 and 93C66: seven 14-bit instructions for 93C86; control the reading, writing and erase operations of the device. The CAT93CXXXX operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applica- tions where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46XX)//7-bit (93C57XX)/ 8-bit (93C56XX or 93C66XX)/10-bit (93C86XX) (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations).
Figure 6. EWEN/EWDS Instruction Timing contents of all memory bits return to a logical “1” state. The CAT93CXXXX powers up in the write disable state.
Advanced InformationCAT93CXXXX Stock No. 21084-01 2/98
Ordering Information
Figure 8. WRAL Instruction Timing
12 RESET on Pin 7, No WDT
13 RESET on Pin 7, WDT on CS
14 RESET on Pin 7, WDT on CS
2.55V to 2.7 V Reset threshold voltage, Tape & Reel).