CAT93C56

CAT93C56_06 CATALYST | Alldatasheet

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Technical content

© 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice. Doc. No. 1088, Rev. O HALOGEN FREE TM LEAD F REE CS SK DI DO VCC NC ORG GND CS SK DI DO VCC ORG GND VCC CS SK ORG GND DO DI CS SK DI DO VCC ORG GND NC NC NC VCC NC ORG GND CS SK DI DO VCC ORG GND DI CS SK DO NC CAT93C56/57 (Die Rev. E) 2K-Bit Microwire Serial EEPROM

FEATURES

I High speed operation: 1MHz I Low power CMOS technology I 1.8 to 5.5 volt operation I Selectable x8 or x16 memory organization I Self-timed write cycle with auto-clear I Software write protection I Sequential read I Power-up inadvertant write protection I 1,000,000 Program/erase cycles I 100 year data retention I Commercial, industrial and automotive temperature ranges I RoHS-compliant packages PIN CONFIGURATION using Catalyst’s advanced CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and has a data reten- tion of 100 years. The devices are available in 8-pin DIP, SOIC, TSSOP and 8-pad TDFN packages.

DESCRIPTION

The CAT93C56/57 are 2K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at V CC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C56/57 are manufactured Bottom View FUNCTIONAL SYMBOL Note: When the ORG pin is connected to VCC, the x16 organiza- tion is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. CS SK DI ORG DO VCC GND PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization NC No Connection For Ordering Information details, see page 8.

Doc. No. 1088, Rev. O D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units ICC1 Power Supply Current f SK = 1MHz 3 mA (Write) V CC = 5.0V ICC2 Power Supply Current f SK = 1MHz 500 µA (Read) V CC = 5.0V ISB1 Power Supply Current CS = 0V 10 µA (Standby) (x8 Mode) ORG=GND ISB2 Power Supply Current CS=0V 0 10 µA (Standby) (x16Mode) ORG=Float or V CC ILI Input Leakage Current V IN = 0V to VCC 1 µA ILO Output Leakage Current V OUT = 0V to VCC,1 µA (Including ORG pin) CS = 0V VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 V CC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 V CC x 0.2 V VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V V CC x 0.7 V CC+1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V 0.4 V IOL = 2.1mA VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V 2.4 V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V 0.2 V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V V CC - 0.2 V IOH = -100µA ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Typ Max Units NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(3)(4) Latch-Up JEDEC Standard 17 100 mA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.

Doc. No. 1088, Rev. O PIN CAPACITANCE Symbol Test Conditions Min Typ Max Units COUT(2) Output Capacitance (DO) V OUT=0V 5 pF CIN(2) Input Capacitance (CS, SK, DI, ORG) V IN=0V 5 pF INSTRUCTION SET noitcurtsnI eciveD epyT tratS tiBe docpO sserddAa taD stnemmoC8x6 1x8 x6 1x DAER6 5C39 )1( 10 10 A-8A0 A-7A0 A–NAsserddAdaeR 75C391 0 10 A-7A0 A-6A ESARE6 5C39 )1( 11 10 A-8A0 A-7A0 A–NAsserddAraelC 75C391 1 10 A-7A0 A-6A ETIRW6 5C39 )1( 11 00 A-8A0 A-7A0 D-7D0 D-51D0 A–NAsserddAetirW 75C391 1 00 A-7A0 A-6A0 D-7D0 D-51D NEWE6 5C39 )1( 10 0 XXXXX11X XX XXXX11X elbanEetirW 75C391 0 0 XXXXX11X X XXXX11 SDWE6 5C39 )1( 10 0 00X XXXXX X0 0X XXXXX elbasiDetirW 75C391 0 0 00X XXXXX 0 0X XXXX LARE6 5C39 )1( 10 0 10 X XXXXX X1 0 X XXXXX sesserddAllAraelC 75C391 0 0 10 X XXXX X 10 X XXXX LARW6 5C39 )1( 10 0 0X XXXX1X X0 X XXXX1X 0D-7D0 D-51Ds esserddAllAetirW 75C391 0 0 0X XXXX1X 0X XXXX1 0D-7D0 D-51D Limits VCC =V CC =V CC = Test Symbol Parameter Conditions Min Max Min Max Min Max Units tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 400 200 100 ns tDIH DI Hold Time 400 200 100 ns tPD1 Output Delay to 1 1 0.5 0.25 µs tPD0 Output Delay to 0 1 0.5 0.25 µs tHZ(1) Output Delay to High-Z 400 200 100 ns tEW Program/Erase Pulse Width 10 10 10 ms tCSMIN Minimum CS Low Time 1 0.5 0.25 µs tSKHI Minimum SK High Time 1 0.5 0.25 µs tSKLOW Minimum SK Low Time 1 0.5 0.25 µs tSV Output Delay to Status Valid 1 0.5 0.25 µs SKMAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz A.C. CHARACTERISTICS CL = 100pF (3) Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands. (2) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 1088, Rev. O A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V Input Pulse Voltages 0.2V CC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V Timing Reference Voltages 0.5V CC 1.8V ≤ VCC ≤ 4.5V POWER-UP TIMING (1)(2) Symbol Parameter Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in “AC Test Conditions” table. DEVICE OPERATION The CAT93C56/57 is a 2048-bit nonvolatile memory intended for use with industry standard microproces- sors. The CAT93C56/57 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 10-bit instructions for 93C57; seven 11-bit instructions for 93C56 control the reading, writing and erase operations of the device. When organized as X8, seven 11-bit instructions for 93C57; seven 12-bit in- structions for 93C56 control the reading, writing and erase operations of the device. The CAT93C56/57 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indi- cates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address (93C57)/ 8-bit address (93C56) (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C56/ 57 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (t PD0 or tPD1). Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of t CSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Since this device features Auto- Clear before write, it is NOT necessary to erase a memory location before it is written into.

of a cleared location returns to a logical “1” state. The CAT93C56/57 powers up in the write disable state. memory bits return to a logical “1” state. the WRAL command is executed. Figure 4. Erase Instruction Timing

Doc. No. 1088, Rev. O

ORDERING INFORMATION

L = PDIP V = SOIC, JEDEC W = SOIC, JEDEC X = SOIC, EIAJ (5) Y = TSSOP ZD4 = TDFN (3x3mm) Prefix Device # Suffix Product Number 93C56: 2K 93C57: 2K Tape & Reel T: Tape & Reel 2: 2000/Reel (5) 3: 3000/Reel Temperature Range I = Industrial (-40°C - 85°C) A = Automotive (-40°C - 105°C) E = Extended (-40°C to + 125°C) Operating Voltage Blank (Vcc = 2.5V to 5.5V) 1.8 (Vcc = 1.8V to 5.5V) Company ID Die Revision 93C56: E 93C57: E Lead Finish Blank: Matte-Tin G: NiPdAu 93C56 V I T3-1.8CAT Rev E (4) – G Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard finish is NiPdAu. (3) The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage, NiPdAu, Tape & Reel). (4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWW E.) For additional information, please contact your Catalyst sales office. (5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C56X I-T2. (6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.

Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE 2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters

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Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: 1088 Revison: O Issue date: 10/13/06

REVISION HISTORY

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