CAT93C46YIT2

CAT93C46_07 CATALYST | Alldatasheet

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Technical content

© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1106, Rev. F CAT93C46 1-Kb Microwire Serial EEPROM

FEATURES

I High speed operation: 2MHz I 1.8V to 5.5V supply voltage range I Selectable x8 or x16 memory organization I Self-timed write cycle with auto-clear I Software write protection I Power-up inadvertant write protection I Low power CMOS technology I 1,000,000 Program/erase cycles I 100 year data retention I Industrial temperature ranges I RoHS-compliant 8-pin PDIP, SOIC, TSSOP and 8-pad TDFN packages PIN CONFIGURATION PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2) SOIC (W)

DESCRIPTION

The CAT93C46 is a 1K-bit Serial EEPROM memory device which is configured as either 64 registers of 16 bits (ORG pin at V CC ) or 128 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46 features a self-timed internal write with auto-clear. On-chip Power- On Reset circuit protects the internal logic against powering up in the wrong state. FUNCTIONAL SYMBOL Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. CS SK DI ORG DOCAT93C46 VCC GND PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization NC No Connection VCC NC ORG GND DI CS SK DO ORG GND DO DI CS NC VCC SK For Ordering Information details, see page 13.

2 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, TA=-40°C to +85°C, unless otherwise specified. Symbol Parameter Test Conditions Min Max Units ICC1 Power Supply Current f SK = 1MHz 1 mA (Write) V CC = 5.0V ICC2 Power Supply Current f SK = 1MHz 500 µA (Read) V CC = 5.0V ISB1 Power Supply Current V IN=GND or VCC, CS =GND 2 µA (Standby) (x8 Mode) ORG=GND ISB2 Power Supply Current V IN=GND or VCC, CS =GND 1 µA (Standby) (x16Mode) ORG=Float or V CC ILI Input Leakage Current V IN = GND to VCC 1 µA ILO Output Leakage Current V OUT = GND to VCC ,1 µA CS = GND VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 V CC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 V CC x 0.2 V VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V V CC x 0.7 V CC +1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V 0.4 V IOL = 2.1mA VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V 2.4 V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V 0.2 V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V V CC - 0.2 V IOH = -100µA Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC +0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC +1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Block Mode, VCC = 5V, 25°C ABSOLUTE MAXIMUM RATINGS (1) Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground (2) -0.5 V to +6.5 V RELIABILITY CHARACTERISTICS (3) l o b m ySr e t e m a r aPn iMs t i n U N D N E ) 4 ( e c n a r u d nE0 0 0 , 0 0 0 ,1s e l c y C e s a r E / m a r g o r P T R D n o i t n e t e R a t aD0 01s r a e Y

3 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Limits Symbol Parameter Min Max Units tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 µs tPD0 Output Delay to 0 0.25 µs tHZ (1) Output Delay to High-Z 100 ns tEW Program/Erase Pulse Width 5 ms tCSMIN Minimum CS Low Time 0.25 µs tSKHI Minimum SK High Time 0.25 µs tSKLOW Minimum SK Low Time 0.25 µs tSV Output Delay to Status Valid 0.25 µs SK MAX Maximum Clock Frequency DC 2000 kHz A.C. CHARACTERISTICS (2) VCC = +1.8V to +5.5V, TA=-40°C to +85°C, unless otherwise specified. PIN CAPACITANCE TA=25°C, f=1MHz, VCC =5V Symbol Test Conditions Min Typ Max Units C OUT (1) Output Capacitance (DO) V OUT =0V 5 pF C IN(1) Input Capacitance (CS, SK, DI, ORG) V IN=0V 5 pF NOTES: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) Test conditions according to “AC Test Conditions” table. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. POWER-UP TIMING (1)(3) Symbol Parameter Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms

6 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. erase a memory location before it is written into. self clocking clear cycle of the selected memory location. contents of all memory bits return to a logical “1” state. clocking data write to all memory locations in the device. the WRAL command is executed. Figure 4. Write Instruction Timing

8 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD 300 MIL PLASTIC DIP (L) A e b L E D eB 24C16_8-LEAD_DIP_(300P).eps SYMBOL A b D E e eB L MIN 0.38 0.36 9.02 7.62 6.09 6.35 7.87 0.115 0.130 0.150 NOM 0.46 1.77 1.14 7.87

2.54 BSC

4.57 A2 3.05 3.81 0.56 10.16 8.25 7.11 9.65 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

9 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD 150 MIL SOIC (V, W) 24C16_8-LEAD_SOIC.eps SYMBOL A b C D E h L MIN 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 NOM 0.25 0.19 MAX 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 BSC 0.50 1.27 θ10 ° 8° E D A1e L C b h x 45 A Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012. For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

10 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD 208 MIL SOIC (X) Notes: 1. All dimensions are in millimeters. 2. Complies with EIAJ specification EDR-7320. 3. D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.06in per side. 4. E1 does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010in per side. 5. Lead span/stand off height/coplanarity are considered as special characteristic (A1). L A b E e D c SYMBOL A b c D E e L MIN 0.05 0.36 5.13 7.75 5.13 0.51 NOM 0.25 0.19

1.27 BSC

0.25 2.03 0.48 5.33 8.26 5.38 0.76 θ10 ° 8° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

11 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD TSSOP (Y) 8 5 1 4 E E1 E/2 PIN #1 IDENT. D b L e A SEE DETAIL A SEE DETAIL A SEATING PLANE c GAGE PLANE 0.25 SYMBOL A b c D E e L MIN 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 NOM 0.90 0.30 0.19 3.00 4.40 0.60 0.75 0.50 MAX 1.20 0.15 1.05 0.20 3.10 6.50 4.50

0.65 BSC

Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-153 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

12 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-PAD TDFN 2X3 PACKAGE (VP2) E PIN 1 INDEX AREA L TDFN2X3 (03).eps PIN 1 ID e b 3 x e D A SYMBOL A b D E e L MIN 0.70 0.00 0.45 0.20 1.90 1.30 1.40 2.90 1.20 0.20 0.30 0.40 NOM 0.75 0.02 0.55

0.20 REF

0.25 2.00 3.00

0.50 TYP

0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 1.30 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-229. For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

13 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice EXAMPLE OF ORDERING INFORMATION Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish for the SOIC, EIAJ (X) package is Matte-Tin; the standard lead finish for all other packages is NiPdAu. (3) The device used in the above example is a CAT93C46VI-GT3 (SOIC, JEDEC, Industrial Temperature, NiPdAu, Tape & Reel). (4) The SOIC, EIAJ (X) package is available in reels of 2000 pcs/reel (i.e. CAT93C46XI-T2). All other packages are offered in reels of 3000 pcs/reel. (5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Prefix Device # Suffix 93C46 V I Product Number 93C46 CAT Temperature Range I = Industrial (-40°C - 85°C) Optional Company ID Package L = PDIP V = SOIC, JEDEC W = SOIC, JEDEC X = SOIC, EIAJ Y = TSSOP VP2 = TDFN (2X3mm) Tape & Reel(4) T: Tape & Reel 2: 2000/Reel 3: 3000/Reel Lead Finish (2) Blank: Matte-Tin G: NiPdAu T3– G

14 Doc No. 1106, Rev. F© 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

REVISION HISTORY

e t aDn o i s i v eRs t n e m m o C 5 0 / 1 0 / 21A e u s s I l a i t i n I 5 0 / 8 0 / 21B s c i t s i r e t c a r a h C g n i t a r e p O C . D e t a d p U 6 0 / 2 2 / 20C n o i t a r u g i f n o C n i P e t a d p U N v e R e i D , s c i t s i r e t a r a h C . C . A e t a d p U s n o i s n e m i D e g a k c a P e t a d p U n o i t a m r o f n I g n i r e d r O e t a d p U g n i k r a M e g a k c a P e t a d p U 6 0 / 4 2 / 50D n o i t a r u g i f n o C n i P e t a d p U s n o i t c n u F n i P e t a d p U s c i t s i r e t a r a h C g n i t a r e p O . C . D e t a d p U s c i t s i r e t a r a h C . C . A e t a d p U n o i t a r e p O e c i v e D e t a d p U g n i k r a M e g a k c a P e t a d p U l e e R d n a e p a T e v o m e R n o i t a m r o f n I e g a k c a P f o e l p m a x E e t a d p U 6 0 / 1 0 / 80E s c i t s i r e t a r a h C g n i t a r e p O . C . D e t a d p U e c n a t i c a p a C n i P r o f n o i t i d n o C t s e T e t a d p U s c i t s i r e t a r a h C . C . A e t a d p U n o i t a r e p O e c i v e D e t a d p U e g a k c a P ) X ( C I O S l i m 8 0 2 d a e L 8 d d A g n i k r a M e g a k c a P e t a d p U n o i t a m r o f n I e g a k c a P f o e l p m a x E e t a d p U 7 0 / 8 0 / 20F s c i t s i r e t c a r a h C g n i t a r e p O . C . D e t a d p U s c i t s i r e t c a r a h C . C . A e t a d p U 6 d n a 5 s e r u g i F e t a d p U g n i k r a M e g a k c a P e v o m e R

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