CAT5111_07 CATALYST | Alldatasheet

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© 2007 Catalyst Semiconductor, Inc. 1 Doc. No. MD-2008 Rev. P Characteristics subject to change without notice 100-Tap Digitally Programmable Potentiometer (DPP™) with Buffered Wiper

FEATURES

„ 100-position linear taper potentiometer „ Non-volatile EEPROM wiper storage; buffered wiper „ Low power CMOS technology „ Single supply operation: 2.5V-6.0V „ Increment up/down serial interface „ Resistance values: 10kΩ, 50kΩ and 100kΩ „ Available in PDIP, SOIC, TSSOP and MSOP packages

APPLICATIONS

„ Automated product calibration „ Remote control adjustments „ Offset, gain and zero control „ Tamper-proof calibrations „ Contrast, brightness and volume controls „ Motor controls and feedback systems „ Programmable analog functions For Ordering Information details, see page 10.

DESCRIPTION

The CAT5111 is a single digitally programmable potentiometer (DPP™) designed as a electronic replacement for mechanical potentiometers. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The CAT5111 contains a 100-tap series resistor array connected between two terminals R H and R L. An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, R WB. The CAT5111 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new system values without effecting the stored setting. Wiper-control of the CAT5111 is accomplished with three input control pins, CS¯¯, U/D¯, and INC¯¯¯. The INC¯¯¯ input increments the wiper in the direction which is determined by the logic state of the U/D¯ input. The CS¯¯ input is used to select the device and also store the wiper position prior to power down. The digitally programmable potentiometer can be used as a buffered voltage divider. For applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the CAT5113. The buffered wiper of the CAT5111 is not compatible with that application. FUNCTIONAL DIAGRAM Control and Memory Power On Recall VCC GND U/D INC CS RH RH RWB RWB RL RL Electronic Potentiometer Implementation

Doc. No. MD-2008 Rev. P 2 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice PIN CONFIGURATION PDIP 8-Lead (L) SOIC 8 Lead (V) MSOP 8 Lead (Z) INC¯¯¯ 1 8 VCC U/D¯ 2 7 CS¯¯ RH 3 6 RL GND 4 5 RWB CAT TSSOP 8 Lead (Y) CS¯¯ 1 8 RL VCC 2 7 RWB INC¯¯¯ 3 6 GND U/D¯ 4 5 RH CAT PIN DESCRIPTIONS Name Function INC¯¯¯ Increment Control U/D¯ Up/Down Control RH Potentiometer High Terminal GND Ground RWB Buffered Wiper Terminal RL Potentiometer Low Terminal CS¯¯ Chip Select VCC Supply Voltage PIN DESCRIPTION INC¯¯¯: Increment Control Input The INC¯¯¯ input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D¯ input. U/D¯: Up/Down Control Input The U/D¯ input controls the direction of the wiper movement. When in a high state and CS¯¯ is low, any high-to-low transition on INC¯¯¯ will cause the wiper to move one increment toward the R H terminal. When in a low state and CS¯¯ is low, any high-to-low transition on INC¯¯¯ will cause the wiper to move one increment towards the RL terminal. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the R L terminal. Voltage applied to the R H terminal cannot exceed the supply voltage, VCC or go below ground, GND. RWB: Wiper Potentiometer Terminal (Buffered) RWB is the buffered wiper terminal of the poten– tiometer. Its position on the resistor array is controlled by the control inputs, INC¯¯¯, U/D¯ and CS¯¯. R L: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the R H terminal. Voltage applied to the R L terminal cannot exceed the supply voltage, VCC or go below ground, GND. R L and R H are electri- cally interchangeable. CS¯¯: Chip Select The chip select input is used to activate the control input of the CAT5111 and is active low. When in a high state, activity on the INC¯¯¯ and U/D¯ inputs will not affect or change the position of the wiper. DEVICE OPERATION The CAT5111 operates like a digitally controlled potentiometer with R H and R L equivalent to the high and low terminals and R WB equivalent to the mecha– nical potentiometer's wiper. There are 100 available tap positions including the resistor end points, R H and RL. There are 99 resistor elements connected in series between the R H and R L terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC¯¯¯, U/D¯ and CS¯¯. These inputs control a seven-bi t up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS¯¯ inputs. With CS¯¯ set LOW the CAT5111 is selected and will respond to the U/D¯ and INC¯¯¯ inputs. HIGH to LOW transitions on INC¯¯¯ wil increment or decrement the wiper (depending on the state of the U/D ¯ input and seven-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS¯¯ transitions HIGH while the INC¯¯¯ input is also HIGH. When the CAT5111 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restor ed, the contents of the memory are recalled and the counter is set to the value stored. With INC¯¯¯ set low, the CAT5111 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in non- volatile memory.

© 2007 Catalyst Semiconductor, Inc. 3 Doc. No. MD-2008 Rev. P Characteristics subject to change without notice OPERATION MODES High to Low Low High Wiper toward R H High to Low Low Low Wiper toward R L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby ABSOLUTE MAXIMUM RATINGS(1) Parameters Ratings Units Supply Voltage V CC to GND -0.5 to +7V V Inputs CS¯¯ to GND -0.5 to VCC +0.5 V INC¯¯¯ to GND -0.5 to VCC +0.5 V U/D¯ to GND -0.5 to VCC +0.5 V R H to GND -0.5 to V CC +0.5 V R L to GND -0.5 to V CC +0.5 V R WB to GND -0.5 to V CC +0.5 V Parameters Ratings Units Operating Ambient Temperature Commercial (‘C’ or Blank suffix) 0 to 70 ºC Industrial (‘I’ suffix) -40 to +85 ºC Junction Temperature +150 ºC Storage Temperature -65 to 150 ºC Lead Soldering (10s max) +300 ºC RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min Typ Max Units VZAP (2) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V ILTH (2) (3) Latch-Up JEDEC Standard 17 100 mA TDR Data Retention MIL-STD-883, Test Method 1008 100 Years NEND Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores DC ELECTRICAL CHARACTERISTICS VCC = +2.5V to +6V unless otherwise specified Power Supply Symbol Parameter Conditions Min Typ Max Units VCC Operating Voltage Range 2.5 – 6 V VCC = 6V, f = 1MHz, IW = 0 – – 200 µA ICC1 Supply Current (Increment) VCC = 6V, f = 250kHz, IW = 0 – – 100 µA Programming, VCC = 6V – – 1000 µA ICC2 Supply Current (Write) VCC = 3V – – 500 µA ISB1 (3) Supply Current (Standby) CS¯¯ = VCC - 0.3V U/D¯, INC¯¯¯ = VCC - 0.3V or GND – 75 150 µA Notes: (1) Stresses above those listed under “Absolut e Maximum Ratings” may cause permanent damage to the device. These are stress rat ings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. Exposure to any absolute maxi mum rating for extended periods may affect device performance and re liability. (2) This parameter is tested initially and after a des ign or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V (4) I W = source or sink (5) These parameters are periodically sampled and are not 100% tested. CH RH RWI RWB Potentiometer Equivalent Circuit CW CL RL

Doc. No. MD-2008 Rev. P 4 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice Logic Inputs Symbol Parameter Conditions Min Typ Max Units IIH Input Leakage Current V IN = VCC – – 10 µA IIL Input Leakage Current V IN = 0V – – -10 µA VIH1 TTL High Level Input Voltage 2 – V CC V VIL1 TTL Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V 0 – 0.8 V VIH2 CMOS High Level Input Voltage V CC x 0.7 – V CC + 0.3 V VIL2 CMOS Low Level Input Voltage 2.5V ≤ VCC ≤ 6V -0.3 – V CC x 0.2 V Potentiometer Characteristics Symbol Parameter Conditions Min Typ Max Units -10 Device 10 -50 Device 50 RPOT Potentiometer Resistance -00 Device 100 kΩ Pot. Resistance Tolerance ±20 % VRH Voltage on R H pin 0 V CC V VRL Voltage on R L pin 0 V CC V Resolution 1 % INL Integral Linearity Error I W ≤ 2µA 0.5 1 LSB DNL Differential Linearity Error I W ≤ 2µA 0.25 0.5 LSB ROUT Buffer Output Resistance 0.05VCC ≤ VWB ≤ 0.95VCC, VCC = 5V 1 Ω IOUT Buffer Output Current 0.05VCC ≤ VWB ≤ 0.95VCC, VCC = 5V 3 mA TCRPOT TC of Pot Resistance 300 ppm/ºC TCRATIO Ratiometric TC TBD ppm/ºC RISO Isolation Resistance TBD Ω CRH/CRL/CRW Potentiometer Capacitances 8/8/25 pF fc Frequency Response Passive Attenuator, 10k Ω 1.7 MHz VWB(SWING) Output Voltage Range I OUT ≤ 100µA, VCC = 5V 0.01V CC 0.99V CC

© 2007 Catalyst Semiconductor, Inc. 5 Doc. No. MD-2008 Rev. P Characteristics subject to change without notice AC CONDITIONS OF TEST VCC Range 2.5V ≤ VCC ≤ 6V Input Pulse Levels 0.2V CC to 0.7VCC Input Rise and Fall Times 10ns Input Reference Levels 0.5V CC AC OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified Symbol Parameter Min Typ (1) Max Units tCI CS¯¯ to INC¯¯¯ Setup 100 – – ns tDI U/D¯ to INC¯¯¯ Setup 50 – – ns tID U/D¯ to INC¯¯¯ Hold 100 – – ns tIL INC¯¯¯ LOW Period 250 – – ns tIH INC¯¯¯ HIGH Period 250 – – ns tIC INC¯¯¯ Inactive to CS¯¯ Inactive 1 – – µs tCPH CS¯¯ Deselect Time (NO STORE) 100 – – ns tCPH CS¯¯ Deselect Time (STORE) 10 – – ms tIW INC¯¯¯ to VOUT Change – 1 5 µs tCYC INC¯¯¯ Cycle Time 1 – – µs tR, tF (2) INC¯¯¯ Input Rise and Fall Time – – 500 µs tPU (2) Power-up to Wiper Stable – – 1 ms tWR Store Cycle – 5 10 ms A.C. TIMING Notes: (1) Typical values are for T A = 25ºC and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) MI in the A.C. Timing diagram refers to the minimum incr emental change in the W output due to a change in the wiper position. CS INC U/D RWB tCI tIL MI(3) 90% 90% 10% (store)tCYC tIH tIC tCPH tF tR tDI tID tIW

Doc. No. MD-2008 Rev. P 6 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice PACKAGE OUTLINES PDIP 8-LEAD (300MIL) (L) Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC Standard MS001. (3) Dimensioning and tolerancing per ANSI Y14.5M-1982 A e b c L E D eB SYMBOL A b D E e eB L MIN 0.38 0.36 9.02 7.62 6.09 6.35 7.87 2.92 3.81 NOM 0.46 1.771.14 7.87

2.54 BSC

4.57 A2 3.05 3.81 0.56 c 0.21 0.26 0.35 10.16 8.25 7.11 9.65 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

© 2007 Catalyst Semiconductor, Inc. 7 Doc. No. MD-2008 Rev. P Characteristics subject to change without notice SOIC 8-LEAD NARROW BODY (150MIL) (V) Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC Specification MS-012. SYMBOL A b C D E h L MIN 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 NOM 0.250.19 MAX 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 BSC 0.50 1.27 Ө1 0° 8° E D A1e L C b h x 45 A For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

Doc. No. MD-2008 Rev. P 8 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 8-LEAD TSSOP (Y) Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC Standard MO-153 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. 8 5 1 4 E E1 E/2 PIN #1 IDENT. D b L e A SEE DETAIL A SEE DETAIL A SEATING PLANE c GAGE PLANE 0.25 SYMBOL A b c D E e L MIN 0.05 0.80 0.09 2.90 6.30 6.4 4.30 0.00 8.00 NOM 0.90 0.300.19 3.00 4.40 0.60 0.750.50 MAX 1.20 0.15 1.05 0.20 3.10 6.50 4.50

0.65 BSC

© 2007 Catalyst Semiconductor, Inc. 9 Doc. No. MD-2008 Rev. P Characteristics subject to change without notice 8-LEAD MSOP (Z) Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC Specification MS-187. (3) Stand off height/coplanarity are considered as special characteristics. c EE1 e ee b D A2 A GAUGE PLANE L θ SYMBOL MIN NOM MAX A1 . 1 A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.28 0.33 0.38 c D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 e0 . 6 5 B S C L 0.35 0.45 0.55 Ө 0º 6º For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

Doc. No. MD-2008 Rev. P 10 © 2007 Catalyst Semiconductor, Inc. Characteristics subject to change without notice EXAMPLE OF ORDERING INFORMATION Notes: (1) All packages are RoHS compliant. (2) Standard lead finish is NiPdAu. (3) This device used in the above example is a CAT5111VI-10-GT3 (SOIC, Industrial Temperature, 10kΩ, NiPdAu, Tape & Reel). (4) For Matte-Tin finish, contact factory. ORDERING PART NUMBER CAT5111LI-10-G CAT5111LI-50-G CAT5111LI-00-G CAT5111VI-10-G CAT5111VI-50-G CAT5111VI-00-G CAT5111YI-10-G CAT5111YI-50-G CAT5111YI-00-G CAT5111ZI-10-G CAT5111ZI-50-G CAT5111ZI-00-G Prefix Device # Suffix CAT 5111 V I -10 – G (4) T3 Optional Company ID Temperature Range I = Industrial (-40ºC to 85ºC) Resistance -10: 10k ohms -50: 50k ohms -00: 100k ohms Lead Finish Blank: Matte-Tin G:NiPdAu Package L: PDIP V: SOIC Y: TSSOP Z: MSOP Tape & Reel T: Tape & Reel 3: 3000/Reel Product Number 5111

REVISION HISTORY

Date Rev. Reason 3/10/2004 M Updated Potentiometer Parameters 3/29/2004 N Changed Green Package marking for SOIC from W to V 4/12/2004 O Updated Reel Ordering Information 06/01/2007 P Updated Example of Ordering Information Added Package Outline Added MD- in front of Document No. Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory™, DPP™, EZDim™, LDD™ , LDD™, MiniPot™ and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUAR ANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRO DUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARIS ING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconduct or product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any produ ct or service descr ibed herein without not ice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters

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Santa Clara, CA 95054 Phone: 408.542.1000 Document No: MD-2008 Fax: 408.542.1200 Revision: P www.catsemi.com Issue date: 06/01 /07