CAT5111 CATALYST | Alldatasheet
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Technical content
100-Tap Digitally Programmable Potentiometer (DPP™) with Buffered Wiper
FEATURES
I 100-position linear taper potentiometer I Non-volatile NVRAM wiper storage; buffered wiper I Low power CMOS technology I Single supply operation: 2.5V-6.0V I Increment up/down serial interface I Resistance values: 10kΩ,Ω,Ω,Ω,Ω, 50kΩ Ω Ω Ω Ω and 100kΩΩΩΩΩ I Available in PDIP, SOIC, TSSOP and MSOP p ackages
APPLICATIONS
I Automated product calibration I Remote control adjustments I Offset, gain and zero control I Tamper-proof calibrations I Contrast, brightness and volume controls I Motor controls and feedback systems I Programmable analog functions system values without effecting the stored setting. Wiper-control of the CAT5111 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The digitally programmable potentiometer can be used as a buffered voltage divider. For applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the CAT5113. The buffered wiper of the CAT5111 is not compatible with that application. DPPs bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit. FUNCTIONAL DIAGRAM
DESCRIPTION
The CAT5111 is a single digitally programmable potentiometer (DPP™) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The CAT5111 contains a 100-tap series resistor array connected between two terminals R H and RL. An up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, R WB . The CAT5111 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new Electronic Potentiometer Implementation R H – R WB R L CS INC U /D Control and Memory VCC R R R WB H L Power On Recall GND © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 2008, Rev. O1 HALOGEN FREE TM LEAD F REE
2Doc. No. 2008, Rev. O of the CAT5111 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. DEVICE OPERATION The CAT5111 operates like a digitally controlled potentiometer with R H and RL equivalent to the high and low terminals and RWB equivalent to the mechanical potentiometer's wiper. There are 100 available tap positions including the resistor end points, R H and RL. There are 99 resistor elements connected in series between the R H and RL terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC, U/D and CS. These inputs control a seven- bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. With CS set LOW the CAT5111 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and seven-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5111 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. With INC set low, the CAT5111 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. PIN DESCRIPTIONS INCINCINCINCINC: Increment Control Input The INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input. U/DDDDD: Up/Down Control Input The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any high- to-low transition on INC will cause the wiper to move one increment toward the R H terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the R L terminal. R H: High End Potentiometer Terminal R H is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the R L terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. R WB : Wiper Potentiometer Terminal (Buffered) R WB is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. R L: Low End Potentiometer Terminal R L is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the R H terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. R L and R H are electrically interchangeable. CSCSCSCSCS: Chip Select The chip select input is used to activate the control input PIN FUNCTIONS Pin Name Function INC Increment Control U/D Up/Down Control R H Potentiometer High Terminal GND Ground R WB Buffered Wiper Terminal R L Potentiometer Low Terminal CS Chip Select VCC Supply Voltage PIN CONFIGURATION INC VCC CS R L R WB U /D R H GND CS INC VCC R L R WB U /D R H GND VCC R L R WBGND R H INC U/D CS CS INC VCC R L R WB U /D R H GND
Doc. No. 2008, Rev. O OPERATING MODES ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC to GND –0.5V to +7V Inputs CS to GND –0.5V to VCC +0.5V INC to GND –0.5V to VCC +0.5V U/D to GND –0.5V to VCC +0.5V R H to GND –0.5V to VCC +0.5V R L to GND –0.5V to VCC +0.5V R WB to GND –0.5V to VCC +0.5V Operating Ambient Temperature Commercial (‘C ’ or Blank suffix) 0°C to +70°C Industrial (‘I’ suffix) – 40°C to +85°C Junction Temperature +150 °C Storage Temperature –65°C to +150°C Lead Soldering (10 sec max) +300 °C * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. NOTES: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V (3) IW =source or sink (4) These parameters are periodically sampled and are not 100% tested. RL CL CH RH C W RWB Rwi Potentiometer Equivalent Circuit Power Supply Symbol Parameter Conditions Min Typ Max Units VCC Operating Voltage Range 2.5 — 6.0 V ICC1 Supply Current (Increment) VCC = 6V, f = 1MHz, IW =0 —— 200 µA VCC = 6V, f = 250kHz, IW =0 —— 100 ICC2 Supply Current (Write) Programming, VCC = 6V —— 1m A VCC = 3V —— 500 µA ISB1 (2) Supply Current (Standby) CS=VCC -0.3V — 75 150 µA U/D, INC=VCC -0.3V or GND Symbol Parameter Conditions Min Typ Max Units IIH Input Leakage Current V IN = VCC —— 10 µA IIL Input Leakage Current V IN = 0V —— – 10 µA VIH1 TTL High Level Input Voltage 4.5V ≤ VCC ≤ 5.5V 2 — VCC V VIL1 TTL Low Level Input Voltage 0 — 0.8 V VIH2 CMOS High Level Input Voltage 2.5V ≤ VCC ≤ 6V V CC x 0.7 — VCC + 0.3 V VIL2 CMOS Low Level Input Voltage -0.3 — VCC x 0.2 V Logic Inputs INCcnonmarkingreturncnonmarkingreturn CScnonmarkingreturncnonmarkingreturn U/Dcnonmarkingreturn Operation High to Low Low High Wiper toward RH High to Low Low Low Wiper toward R L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby RELIABILITY CHARACTERISTICS Symbol Parameter Test MethodMin Typ Max Units VZAP (1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH (1)(2) Latch-Up JEDEC Standard 17 100 mA TDR Data Retention MIL-STD-883, Test Method 1008 100 Years N END Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores
4Doc. No. 2008, Rev. O Symbol Parameter Conditions Min Typ Max Units RPOT Potentiometer Resistance -10 Device 10 -50 Device 50 k Ω -00 Device 100 Pot Resistance Tolerance ±20 % VRH Voltage on RH pin 0 V CC V VRL Voltage on RL pin 0 V CC V Resolution 1 % INL Integral Linearity Error I W ≤ 2µA 0.5 1 LSB DNL Differential Linearity Error IW ≤ 2µA 0.25 0.5 LSB ROUT Buffer Output Resistance .05VCC ≤ VWB ≤ .95VCC , VCC =5V 1 Ω IOUT Buffer Output Current .05VCC ≤ VWB ≤ .95VCC , VCC =5V 3 mA TCRPOT TC of Pot Resistance 300 ppm/ oC TCRATIO Ratiometric TC TBD ppm/ oC RISO Isolation Resistance TBD Ω CRH /CRL /CRW Potentiometer Capacitances 8/8/25 pF fc Frequency Response Passive Attenuator, 10k Ω 1.7 MHz VWB(SWING) Output Voltage Range I OUT ≤100µA, VCC =5V 0.01VCC .99VCC Potentiometer Parameters
Doc. No. 2008, Rev. O VCC Range 2.5V ≤ VCC ≤ 6V Input Pulse Levels 0.2V CC to 0.7VCC Input Rise and Fall Times 10ns Input Reference Levels 0.5V CC AC CONDITIONS OF TEST A. C. TIMING (1) Typical values are for TA=25˚C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. CS INC U /D R WB tCI tCYC tIL MI(3) 90% 90% 10% (store) tF tR tIW tIDtDI tIH tCPHtIC Symbol Parameter Min Typ (1) Max Units tCI CS to INC Setup 100 —— ns tDI U/D to INC Setup 50 —— ns tID U/D to INC Hold 100 —— ns tIL INC LOW Period 250 —— ns tIH INC HIGH Period 250 —— ns tIC INC Inactive to CS Inactive 1 —— µs tCPH CS Deselect Time (NO STORE) 100 —— ns tCPH CS Deselect Time (STORE) 10 —— ms tIW INC to VOUT Change — 15 µs tCYC INC Cycle Time 1 —— µs tR, tF(2) INC Input Rise and Fall Time —— 500 µs tPU (2) Power-up to Wiper Stable —— 1 msec tWR Store Cycle — 51 0 m s AC OPERATING CHARACTERISTICS: VCC = +2.5V to +6.0V, VH = VCC , VL = 0V, unless otherwise specified
6Doc. No. 2008, Rev. O
ORDERING INFORMATION
Notes: (1) The device used in the above example is a CAT5111 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel) Prefix Device # Suffix 5111 S Product Number Package P: PDIP S: SOIC U: TSSOP CAT Optional Company ID I TE13 Tape & Reel SOIC: 2000/Reel TSSOP: 2000/Reel MSOP: 2500/Reel -10 Resistance -10: 10kohms -50: 50kohms -00: 100kohms 5111: Buffered 5113: Unbuffered R: MSOP L: PDIP (Lead free, Halogen free) V: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free)
Doc. No. 2008, Rev. O Catalyst Semiconductor, Inc. Corporate Headquarters
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Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE 2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Publication #: 2002 Revison: O Issue date: 4/12/04
REVISION HISTORY
Date Rev. Reason 3/10/2004 M Updated Potentiometer Parameters 3/29/2004 N Changed Green Package marking for SOIC from W to V 4/12/2004 O Updated Reel Ordering Information