CAT504

CAT504 CATALYST | Alldatasheet

Document overview

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Technical content

1© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice PROG PROGRAM CONTROL DI CS DATA REGISTER & EEPROM CLK SERIAL CONTROL DAC 2 DAC 3 DAC 4 V 1 OUT V 2 OUT V 3 OUT V 4 OUT DO SERIAL DATA OUTPUT REGISTER GND V L REF V H REFVPP VDD 31 1 4 DAC 1

FEATURES

n Output settings retained without power n Output range includes both supply rails n 4 independently addressable outputs n 1 LSB Accuracy n Serial µP interface n Single supply operation: 2.7V-5.5V n Setting read-back without effecting outputs

APPLICATIONS

n Automated product calibration. n Remote control adjustment of equipment n Offset, gain and zero adjustments in Self- Calibrating and Adaptive Control systems. n Tamper-proof calibrations.

DESCRIPTION

The CAT504 is a quad 8-Bit Memory DAC designed as an electronic replacement for mechanical potentiom- eters and trim pots. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibra- tion, and applications where equipment which is either difficult to access or in a hazardous environment, re- quires periodic adjustment. The 4 independently programmable DAC's have an output range which includes both supply rails. Output settings, stored in non-volatile EEPROM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each output can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DAC’s output. Control of the CAT504 is accomplished with a simple 3 wire serial interface. A Chip Select pin allows several CAT504s to share a common serial interface and com- munication back to the host controller is via a single serial data line thanks to the CAT504’s Tri-Stated Data Output pin. The CAT504 operates from a single 3–5 volt power supply drawing just a few milliwatts of power. When storing data in EEPROM memory an additional 20 volt low current supply is required. The CAT504 is available in the 0 to 70° C Commercial and –40° C to + 85° C Industrial operating temperature ranges and offered in 14-pin plastic DIP and Surface mount packages. FUNCTIONAL DIAGRAM PIN CONFIGURATION CAT504 8-Bit Quad DACpot CAT504 VPP CLK CS PROG DI DO VDD 11 4 GND VREF H VOUT 1 VOUT 2 VOUT 3 VOUT 4 VREF L VPP CLK CS PROG DI DO VDD 11 4 GND VREF H VOUT 1 VOUT 2 VOUT 3 VOUT 4 VREF L CAT 504 CAT 504 Doc. No. 25048-0A 2/98 M-1

2Doc. No. 25048-0A 2/98 M-1 ABSOLUTE MAXIMUM RATINGS* Supply Voltage Inputs Outputs Operating Ambient Temperature * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min Max Units Test Method VZAP (1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (1)(2) Latch-Up 100 mA JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. Logic Inputs IIH Input Leakage Current V IN = VDD ——1 0 µA IIL Input Leakage Current V IN = 0V — — –10 µA VIH High Level Input Voltage 2 — V DD V VIL Low Level Input Voltage 0 — 0.8 V References VRH VREF H Input Voltage Range 2.7 — V DD V VRL VREF L Input Voltage Range GND — V DD -2.7 V ZIN VREF H–V REF L Resistance — 7k — Ω Logic Outputs VOH High Level Output Voltage I OH = – 40 µAV DD –0.3 — — V VOL Low Level Output Voltage I OL = 1 mA, VDD = +5V — — 0.4 V IOL = 0.4 mA, VDD = +3V — — 0.4 V Symbol Parameter Conditions Min Typ Max Units Resolution 8 — — Bits Accuracy INL Integral Linearity Error I LOAD = 250 nA, TR = C — — ± 1 LSB TR = I — — ± 1 LSB ILOAD = 1 µA, TR = C — — ± 2 LSB TR = I — — ± 2 LSB DNL Differential Linearity Error I LOAD = 250 nA, TR = C — — ± 0.5 LSB TR = I — — ± 0.5 LSB ILOAD = 1 µA, TR = C — — ± 1.5 LSB TR = I — — ± 1.5 LSB DC ELECTRICAL CHARACTERISTICS: VDD = 2.7V to 5.5V, VREF H = VDD , VREF L = 0V, unless otherwise specified

3 Doc. No. 25048-0A 2/98 M-1 DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = 2.7V to 5.5V, VREF H = +VDD , VREF L = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Symbol Parameter Conditions Min Typ Max Units Digital tCSMIN Minimum CS Low Time 150 — — ns tCSS CS Setup Time 100 — — ns tCSH CS Hold Time 0 — — ns tDIS DI Setup Time 50 — — ns tDIH DI Hold Time 50 — — ns tDO1 Output Delay to 1 — — 150 ns tDO0 Output Delay to 0 — — 150 ns tHZ Output Delay to High-Z — 400 — ns tLZ Output Delay to Low-Z — 400 — ns tPROG Erase/Write Pulse Width 3 5 — ms tPS PROG Setup Time 150 — — ns tCLK H Minimum CLK High Time 500 — — ns tCLK L Minimum CLK Low Time 300 — — ns fC Clock Frequency DC — 1 MHz Analog tDS DAC Settling Time to 1/2 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs C LOAD = 10 pF, VDD = +3V — 6 10 µs Pin Capacitance C IN Input Capacitance V IN = 0V, f = 1 MHz(2) —8— p F C OUT Output Capacitance V OUT = 0V, f = 1 MHz(2) —6— p F NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. C L = 100 pF see note 1 AC ELECTRICAL CHARACTERISTICS: VDD = 2.7V to 5.5V, VREF H = +VDD , VREF L = 0V, unless otherwise specified Analog Output FSO Full-Scale Output Voltage V R = VREF H–V REF L 0.99 V R 0.995 VR —V ZSO Zero-Scale Output Voltage V R = VREF H–V REF L — 0.005 V R 0.10 VR V IL DAC Output Load Current — — 1 µA R OUT DAC Output Impedance V DD = +5V — — 20k Ω VDD = +3V — — 40k Ω PSSR Power Supply Rejection I LOAD = 250 nA — — 1 LSB / V Temperature TC O VOUT Temperature Coefficient VREF H = +5V, VREF L = 0V — — 200 µV/ °C VDD = +5V, ILOAD = 250nA TC REF Temperature Coefficient of V REF H to VREF L — 700 — ppm / °C VREF Resistance Power Supply IDD Supply Current Excludes V REF ——5 0 µA IPP Programming Current V PP = +19V — 200 500 µA VDD Operating Voltage Range 2.7 — 5.5 V VPP Programing Voltage Range 18 19 20 V

4Doc. No. 25048-0A 2/98 M-1 to 1 2 3 4 5 to 1 2 3 4 5 CLK CS DI DO PROG t HCLK Rising CLK edge to falling CLK edge t L CLK Falling CLK edge to CLK rising edge tCSH Falling CLK edge for last data bit (DI) to falling CS edge tCSS Rising CS edge to next rising CLK edge tCSMIN Falling CS edge to rising CS edge tDIS Data valid to first rising CLK edge after CS = high tDIH Rising CLK edge to end of data valid tDO0 Rising CLK edge to D0 = low tLZ Rising CS edge to D0 becoming high low impedance (active output) tDO1 Rising CLK edge to D0 = high tHZ Falling CS edge to D0 becoming high impedance (Tri-State) tPS Rising PROG edge to next rising CLK edge tPROG Rising PROG edge to falling PROG edge t HCLK t LCLK tCSHtCSS tCSMIN tDIS tDIH tDO0tLZ tDO1 tPS tHZ tPROG TIMING FROM TO MIN/MAX Min Min Min Min Min Min Min Max (Max) Max (Max) Min Min PARAM NAME A. C. TIMING DIAGRAM

5 Doc. No. 25048-0A 2/98 M-1 PIN DESCRIPTION Pin Name Function 1V DD Power supply positive.

2 CLK Clock input pin

3V PP EEPROM Programming Voltage

4 CS Chip Select

5 DI Serial data input pin. 6 DO Serial data output pin.

7 PROG EEPROM Programming Enable

8 GND Power supply ground. 9V REF L Minimum DAC output voltage. 10 V OUT 4 DAC output channel 4. 11 V OUT 3 DAC output channel 3. 12 V OUT 2 DAC output channel 2. 13 V OUT 1 DAC output channel 1. 14 V REF H Maximum DAC output voltage. DEVICE OPERATION The CAT504 is a quad 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without chang- ing the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT504 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DAC address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT504’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high imped- ance Tri-State mode. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT504’s clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. No clock is necessary upon system power-up. The CAT504’s internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock. As data transfers are edge triggered clean clock transi- tions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic fami- lies work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. DAC addressing is as follows: DAC OUTPUT A0 A1 VOUT 1 0 0 VOUT 2 1 0 VOUT 3 0 1 VOUT 4 1 1

output values stored in EEPROM memory.

255 OUT

255 REF REF REF OUT

255 FS ZERO ZERO

Figure 3. Temporary Change in Output

8Doc. No. 25048-0A 2/98 M-1 APPLICATION CIRCUITS (Cont.) Coarse-Fine Offset Control by Averaging DAC Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DAC Outputs for Dual Power Supply Systems FINE ADJUST DAC COARSE ADJUST DAC GND V LREF V HREFVDD RC 127R C +5V V REF VREF Fine adjust gives ± 1 LSB change in V when V = ——— OFFSET VREF 2OFFSET V OFFSET FINE ADJUST DAC COARSE ADJUST DAC GND V LREF V HREFVDD RC 127R C +5V +V REF -V REF R o OFFSET VOFFSET REF(+V ) - (V ) OFFSETREF(-V ) + (V ) Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference OPT 504 LT 1029 I > 2 mA GND VDD V = 5.000VREF V HREF V LREF CONTROL & DATA OPT 504 GND VDD V HREF V LREF CONTROL & DATA + 15K 10 µF 5.1V 10K 4.02 K 1.00K 10 µF 35V LM 324 1N5231B MPT3055EL 28 - 32V OUTPUT 0 - 25V @ 1A CAT504 CAT504

9 Doc. No. 25048-0A 2/98 M-1 APPLICATION CIRCUITS (Cont.) 10K +5V WINDOW 2 10K +5V WINDOW 3 10K +5V WINDOW 4 10K +5V WINDOW 5 10K +5V WINDOW 1 GND V LREF CS DI DO PROG CLK VPP VDD V HREF V REF+5V 1.0 µF LM 339 DAC 1 DAC 2 DAC 3 DAC 4 WINDOW 1 WINDOW 2 WINDOW 3 WINDOW 4 WINDOW 5 VREF V 1OUT V 2OUT V 3OUT V 4OUT GND WINDOW STRUCTURE OPT 504 V IN Staircase Window Comparator Overlapping Window Comparator 10K +5V WINDOW 2 10K +5V WINDOW 3 10K +5V WINDOW 1 GND V LREF CS DI DO PROG CLK VPP VDD V HREF V REF+5V 1.0 µF LM 339 DAC 1 DAC 2 DAC 3 DAC 4 WINDOW 1 WINDOW 2 V 1OUT V 2OUT V 3OUT V 4OUT GND WINDOW STRUCTURE OPT 504 V IN WINDOW 3 V HREF CAT504 CAT504

10Doc. No. 25048-0A 2/98 M-1 APPLICATION CIRCUITS (Cont.) Current Sink with 4 Decades of Resolution Current Source with 4 Decades of Resolution GND V LREF VDD V REF +5V DAC OPT 504CONTROL & DATA DAC 10K 10K 39Ω 1W LM385-2.5 5 µA steps I = 2 - 255 mASINK 2N7000 10K 10K TIP 30 39Ω 1W 5 meg 5 meg 3.9K -15V 2N7000 +5V +15V 4.7 µA 1 mA steps 2.2K GND V LREF VDD V HREF +5V DAC OPT 504 CONTROL & DATA DAC 5 meg 5 meg 39Ω 1W 39Ω 1W 5 meg 5 meg 3.9K LM385-2.5 -15V 5 µA steps I = 2 - 255 mASOURCE 1 mA steps 10K 10K +15V TIP 29 BS170P BS170P 51K CAT504 CAT504

11 Doc. No. 25048-0A 2/98 M-1 APPLICATION CIRCUITS (Cont.) Vpp CS PROG DI DO CLK VDD V HREF V LREF V 3OUT V 2OUT V 1OUT V 4OUT GND 47K 47K 47K 47K 1.0 µF 0.22 µF 0.22 µF 0.22 µF 0.22 µF OUT 215 OUT 110 +12V VCC TREB CAP BASS CAP OUTPUT 1 BYPASS OUTPUT 2 TREB CAP BASS CAP GND GND STEREO ENHANCE IN 2 VOLUME BALANCE TREBLE BASS LOUDNESS V IN 1 Z LM1040OPT 504 CHIP SELECT. PROGRAM DATA IN DATA OUT CLOCK INPUT 2 20V IN5250B 2.5 µF INPUT 1 1.0 µF 1N914 1N914 +12V .005 µF 10K 74C14 0.47 µF 0.47 µF 0.1 µF 4.7K 0.1 µF 0.01 µF 0.39 µF 47 µF 10 µF 10 µF 0.39 µF 0.01 µFDigital Stereo Control CAT504

12Doc. No. 25048-0A 2/98 M-1

ORDERING INFORMATION

Notes: (1) The device used in the above example is a CAT504JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Prefix Device # Suffix 504 J Product Number Package P: PDIP J: SOIC CAT Optional Company ID I Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) -TE13 Tape & Reel TE13: 2000/Reel