CAT24C00_05 CATALYST | Alldatasheet

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© 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 CAT24C00 128-Bit Serial EEPROM Doc. No. 1027, Rev. O * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. PIN CONFIGURATION BLOCK DIAGRAM PIN FUNCTIONS Pin Name Function SDA Serial Data/Address SCL Serial Clock NC No Connect VCC 1.8 V to 5.5 V Power Supply VSS Ground

FEATURES

I 400 kHz I2C bus compatible* I 1.8 to 5.5 volt operation I Low power CMOS technology I Self-timed write cycle with auto-clear I 1,000,000 Program/erase cycles I 100 year data retention I 8-pin DIP, 8-pin SOIC, 8 pin TSSOP and SOT-23 I Industrial and Extended Temperature Ranges

DESCRIPTION

The CAT24C00 is a 128-bit Serial CMOS EEPROM internally organized as 16 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The device operates via the I 2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 5-pin SOT-23. NC NC NC VSS VCC NC SCL SDA NC NC NC VSS VCC NC SCL SDA NC NC NC VSS VCC NC SCL SDA DOUT ACK SENSE AMPS SHIFT REGISTERS CONTROL LOGIC WORD ADDRESS BUFFERS START/STOP LOGIC STATE COUNTERS E2PROM VCC EXTERNAL LOAD COLUMN DECODERS XDEC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL VSS SCL SDA SCL VSS SDA VCC NC

2Doc. No. 1027, Rev. O © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5 V Symbol Parameter Test Conditions Min Typ Max Units CI/O(3) Input/Output Capacitance (SDA) V I/O = 0 V 8 pF CIN(3) Input Capacitance (SCL) V IN = 0 V 6 pF D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units ICC Power Supply Current f SCL = 400 kHz 2 mA ISB(5) Standby Current (VCC = 5.0 V) V IN = GND or VCC 1 µA ILI Input Leakage Current V IN = GND to VCC 10 µA ILO Output Leakage Current V OUT = GND to VCC 10 µA VIL Input Low Voltage –1V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage (VCC = 3.0 V) I OL = 3 mA 0.4 V VOL2 Output Low Voltage (VCC = 1.8 V) I OL = 1.5 mA 0.5 V ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Note: (1) The minimum DC input voltage is – 0.5 V. During transitions, inputs may undershoot to – 2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriat e AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from – 1 V to V CC + 1 V. (5) Maximum standby current (I SB) = 10µA for the Extended Automotive temperature range. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Typ. Max. Units NEND(3) Endurance 1,000,000 Cycles/Byte TDR(3) Data Retention 100 Years VZAP(3) ESD Susceptibility 2000 Volts ILTH(3)(4) Latch-up 100 mA

3 Doc. No. 1027, Rev. O© 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Write Cycle Limits Symbol Parameter Min Typ Max Units tWR Write Cycle Time 5 ms A.C. CHARACTERISTICS VCC = 1.8 V to 5.5 V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 1.8 V - 6.0 V 2.5 V - 6.0 V Min Max Min Max Units FSCL Clock Frequency 100 400 kHz TI(1) Noise Suppression Time 100 100 ns Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out 3.5 1 µs and ACK Out tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 50 50 ns tR(1) SDA and SCL Rise Time 1 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4 0.6 µs tDH Data Out Hold Time 100 100 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Power-Up Timing(1)(2) Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms

4Doc. No. 1027, Rev. O © 2005 by Catalyst Semiconductor, Inc. device controls which mode is activated. other open drain or open collector outputs. interpreted as a START or STOP condition. Figure 2. Write Cycle Timing Figure 1. Bus Timing Figure 3. Start/Stop Timing

5020 FHD F05

5020 FHD F04

5020 FHD F03

5 Doc. No. 1027, Rev. O© 2005 by Catalyst Semiconductor, Inc. depending on the state of the R/W bit. data transmission and waits for a STOP condition. byte to be written into the addressed memory location. Figure 4. Acknowledge Timing

5020 FHD F06

6Doc. No. 1027, Rev. O © 2005 by Catalyst Semiconductor, Inc. next read or write operation. READ, Selective READ and Sequential READ. to address 0 and continue to clock out data. Figure 5. Slave Address Bits acknowledge but will generate a STOP condition. acknowledge, thus sending the STOP condition. will “wrap around” and continue to clock out data bytes.

8Doc. No. 1027, Rev. O © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Notes: (1) The device used in the above example is a CAT24C00JI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Volt age, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWB). For additi onal information, please contact your Catalyst sales office.

ORDERING INFORMATION

Prefix Device # Suffix 24C00 J I TE13 Product Number 24C00: 128 Bit Tape & Reel Package P: PDIP J : SOIC (JEDEC) U: TSSOP Operating Voltage Blank: 1.8 V - 5.5 V XCAT Temperature Range I = Industrial (-40°C to 85°C) Optional Company ID TP: SOT23 L : PDIP (Lead free, Halogen free) TB: SOT23 (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GTB: SOT23 (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC (Lead-free, Halogen-free, NiPdAu lead plating) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) E = Extended (-40°C to 125°C) Rev B (2) Die Revision

9 Doc. No. 1027, Rev. O© 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

REVISION HISTORY

Date Rev. Reason 9/24/2003 H Eliminated commercial temperature range class Updated marking 10/30/2003 I Eliminated automotive temperature reange 12/9/2003 J Changed Industrial temp range designation from "Blank" to "I" 12/23/2003 K Eliminatd Commercial and Automotive temp ranges from Features on front page of data sheet 12/29/2003 L Moved DC Operating Characteristics typ numbers for VOL1 and VOL2 to max column Changed 1.8V to 1.8V - 6.0V for AC Characteristics Changed 4.5V - 5.5V to 2.5V - 6.0V for AC Characteristics 7/7/2004 M Added Die Revision to Ordering Information 7/27/2004 N Updated DC Operating Characteristics chart and notes 07/12/2005 O Upate Rekiability Characteristics table Update Ordering Information

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