CAT34AC02RA-1.8TE13

CAT34AC02 CATALYST | Alldatasheet

Document overview

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Technical content

2K-Bit SMBus EEPROM for ACR Card Configuration PIN CONFIGURATION BLOCK DIAGRAM PIN FUNCTIONS Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground

FEATURES

I 400 kHz (5V) and 100 kHz (1.8V) SMBus compatible I 1.8 to 6.0 volt operation I Low power CMOS technology – zero standby current I 16-byte page write buffer I Industrial, automotive and extended temperature ranges I Self-timed write cycle with auto-clear I 1,000,000 program/erase cycles I 100 year data retention I 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages I 256 x 8 memory organization I Hardware write protect

DESCRIPTION

The CAT34AC02 is a 2K-bit Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces de- vice power requirements. The CAT34AC02 features a 16-byte page write buffer. The device operates via the SMBus serial interface for ACR card configuration and is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages. © 2003 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc No. 1025, Rev. E Preliminary Information VSS A0 VCC WP SCL SDA VSS VCC WP SCL SDA VCC WP SCL SDA VSS HALOGEN FREE TM LEAD F REE

2Doc. No. 1025, Rev. E D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units ICC Power Supply Current (Read) f SCL = 100 kHz 1 mA ICC Power Supply Current (Write) f SCL = 100 kHz 3 mA ISB (5) Standby Current (VCC = 5.0V) V IN = GND or VCC 0 µA ILI Input Leakage Current V IN = GND to VCC 10 µA ILO Output Leakage Current V OUT = GND to VCC 10 µA VIL Input Low Voltage –1V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage (VCC = 3.0V) I OL = 3 mA 0.4 V VOL2 Output Low Voltage (VCC = 1.8V) I OL = 1.5 mA 0.5 V CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Parameter Test Conditions Min Typ Max Units C I/O(3) Input/Output Capacitance (SDA) V I/O = 0V 8 pF C IN(3) Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Typ Max Units N END (3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR (3) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP (3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH (3)(4) Latch-up JEDEC Standard 17 100 mA ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias –55°C to +125°C Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. (5) Standby Current (ISB ) = 0µA (<900nA).

3 Doc No. 1025, Rev. E Write Cycle Limits Symbol Parameter Min Typ Max Units tWR Write Cycle Time 4 5 ms A.C. CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Read & Write Cycle Limits Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Power-Up Timing(1)(2) Symbol Parameter Min Typ Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. lobmySr etemaraP stinU niMx aMn iMx aM F LCS ycneuqerFkcolC0 010 04z Hk TI )1( tatnatsnoCemiTnoisserppuSesioN stupnIADS,LCS 0010 01s n tAA tuOataDADSotwoLLCS tuOKCAdna 5.31 s µ t FUB )1( aerofeBeerFebtsuMsuBehtemiT tratSnaCnoissimsnarTweN 7.42 .1s µ t ATS:DH emiTdloHnoitidnoCtratS4 6 .0s µ t WOL doirePwoLkcolC7 .42 .1s µ t HGIH doirePhgiHkcolC4 6 .0s µ t ATS:US arof(emiTputeSnoitidnoCtratS )noitidnoCtratSdetaepeR 7.46 .0s µ t TAD:DH emiTdloHnIataD0 0 s n t TAD:US emiTputeSnIataD0 50 5s n tR )1( emiTesiRLCSdnaADS1 3 .0s µ tF )1( emiTllaFLCSdnaADS0 030 03s n t OTS:US emiTputeSnoitidnoCpotS4 6 .0s µ t HD emiTdloHtuOataD0 010 01s n

READ, Selective READ and Sequential READ. acknowledge but will generate a STOP condition. with an acknowledge, thus sending the STOP condition. Figure 8. Immediate Address Read Timing

Figure 10. Selective Read Timing Figure 11. Sequential Read Timing

5020 FHD F12

5020 FHD F11

Figure 9. Memory Array

9 Doc No. 1025, Rev. E

ORDERING INFORMATION

Notes: (1) The device used in the above example is a 34AC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) Prefix Device # Suffix 34AC02 J I TE13 Product Number Tape & Reel TE13: 2000/Reel Package P: PDIP J: SOIC (JEDEC) U: TSSOP Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V -1.8CAT Temperature Range I = Industrial (-40ßC to 85ßC) A = Automotive (-40ßC to 105ßC) Optional Company ID E = Extended (-40ßC to 125ßC) R: MSOP L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free)

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