CAT33C804A CATALYST | Alldatasheet

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Technical content

4K-Bit Secure Access Serial E2PROM

FEATURES

n Password READ/WRITE Protection: 1 to 8 Bytes n Memory Pointer WRITE Protection n Sequential READ Operation n 256 x 16 or 512 x 8 Selectable Serial Memory n UART Compatible Asynchronous Protocol n Commercial, Industrial and Automotive Temperature Ranges n 100,000 Program/Erase Cycles n I/O Speed: 9600 Baud –Clock Frequency: 4.9152 MHz Xtal n Low Power Consumption: –Active: 3 mA –Standby: 250 µA n 100 Year Data Retention 33C804 F02 BLOCK DIAGRAM

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DO (1) Serial Data Output CLK Clock Input DI(1) Serial Data Input PE Parity Enable ERR Error Indication Pin VCC +3V Power Supply GND Ground Note: (1) DI, DO may be tied together to form a common I/O.

DESCRIPTION

The CAT33C804A is a 4K-bit Serial E2PROM that safe- guards stored data from unauthorized access by use of a user selectable (1 to 8 byte) access code and a movable memory pointer. Two operating modes provide unprotected and password-protected operation allow- ing the user to configure the device as anything from a ROM to a fully protected no-access memory. The CAT33C804A uses a UART compatible asynchronous protocol and has a Sequential Read feature where data can be sequentially clocked out of the memory array. The device is available in 8-pin DIP or 16-pin SOIC packages. © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 25044-00 2/98

2Doc. No. 25044-00 2/98 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method N END (3) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (3)(4) Latch-up 100 mA JEDEC Standard 17 Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. (5) PE pin test conditions: VIH < VIN < VIL D.C. CHARACTERISTICS VCC = +3V ±10%,unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC Power Supply Current 3 mA V CC = 3.3V, CS = VCC (Operating) DO is Unloaded. ISB Power Supply Current 250 µAV CC = 3.3V, CS = 0V (Standby) DI = 0V, CLK = 0V VIL Input Low Voltage –0.1 0.8 V VIH Input High Voltage 2 V VOL Output Low Voltage 0.4 V I OL = 2.1mA VOH Output High Voltage 2.4 V I OH = –400µA ILI(5) Input Leakage Current 2 µAV IN = 3.3V ILO Output Leakage Current 10 µAV OUT = 3.3V, CS = 0V

3 Doc. No. 25044-00 2/98 A.C. CHARACTERISTICS VCC = +3V ±10%,unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions tCSH CS Hold Time 0 ns C L = 100pF tD CLK to DO Delay 104 µsV IN = VIH or VIL tPD CLK to DO Delay 150 ns V OUT = VOH or VOL tHZ (1) (2) CLK to DO High-Z Delay 50 ns tEW Program/Erase Pulse Width 12 ms tCSL CS Low Pulse Width 100 ns tSV ERR Output Delay 150 ns C L = 100pF tVCCS (1) VCC to CS Setup Time 5 µsC L = 100pF fCLK Clock Frequency DC 4.9152 MHz Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t HZ is measured from the falling edge of the clock to the time when the output is no longer driven.

until the end of memory, or until Chip Select goes LOW. via an asynchronous serial communication protocol. disabling instructions are sent or until power is removed. (1) x = DON’T CARE; a = ADDRESS BIT. Figure 2. Secure Mode

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1 TO 8

Figure 3. Unprotected Mode(1)

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Figure 8. EWEN/EWDS Timing (x8 Format)

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Figure 9. EWEN/EWDS Timing (x16 Format)

rect access code has been previously executed. at or above the address in the memory pointer. Figure 10. ERR Pin Timing

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0 A15…A8 P1

0 A7…A0 P1

the output will then go to high impedance. by transmission error), the device will stop its operation. last two bits are reserved for future use.

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Figure 13. Asynchronous Communication Protocol (1) Parity bit if enabled; skipped if parity disabled.

14Doc. No. 25044-00 2/98 WRAL Write All 1000 1100 0011 1001 [D15–D8] [D7–D0] (x16 organization) 1000 1100 0011 1001 [D7–D0] (x8 organization) Write one or two bytes of data to all memory locations. An ERAL will be automatically performed before the WRAL is executed. For protection against inadvertent clearing or writing of data, the ERAL instruction is required to be entered preceding the WRAL instruction. RSEQ Read Sequentially 1100 1100 1011 1011 [A7–A0] (x16 organization) [A15–A8] [A7–A0] (x8 organization) Read memory starting from specified address, sequen- tially to the highest address or until CS goes LOW. The instruction is terminated when CS goes LOW. ENBSY Enable Busy 1000 0100 Enable the status indicator on DO during program/erase cycle. DO goes LOW then HIGH once the write cycle is complete. DO will go to HIGH-Z at the end of the next op code transmission. DISBSY Disable Busy 1000 0101 Disable the status indicator on DO during program/ erase cycle. EWEN Program/Erase Enable 1000 0001 Enable program/erase to be performed on non-pro- tected portion of memory. This instruction must be entered before any program/erase instruction will be carried out. Once entered, it will remain valid until power- down or an EWDS (Program/Erase Disable) is ex- ecuted. EWDS Program/Erase Disable 1000 0010 Disable all write and clear functions. ORG Select Memory Organization 1000 011R (where R = 0 or 1) Set memory organization to 512 x 8 if R = 0. Set memory organization to 256 x 16 if R = 1. RSR Read Status Register 1100 1000 Output the contents of the 8-bit status register. The contents of the first three bits of the register are 101, which allows the user to quickly determine whether the device is listening or is in an error condition. The next three bits indicate parity error, instruction error and RDY/ BUSY status. The last two bits are reserved for future use. NOP No Operation 1000 0000 No Operation. 33C804 F19

ORDERING INFORMATION

Notes: (1) The device used in the above example is a 33C804AJI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Prefix Device # Suffix 33C804A J I -TE13 Product Number Tape & Reel TE13: 2000/Reel Package P: PDIP J: SOIC (JEDEC) Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* CAT * -40˚C to +125˚C is available upon request Optional Company ID