CAT310_07 CATALYST | Alldatasheet

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Technical content

© Catalyst Semiconductor, Inc. 1 Doc No. 25087, Rev. 1 Characteristics subject to change without notice

10 Channel Automotive LED Display Driver

FEATURES

  • Automotive “load dump” protection (40V)
  • 10 independent LED channels
  • Up to 50mA output per channel
  • Overvoltage detection at 19V
  • Serial interface for channel programming
  • Daisy chain output for multi-driver cascading
  • LED blanking control
  • Operating temperature from -40ºC to +125ºC
  • 20-pin SOIC package

APPLICATIONS

  • Automotive lighting
  • White and other color high brightness LEDs
  • Multi-color high-brightness LED cluster displays
  • General LED lighting

ORDERING INFORMATION

1000 CAT310W

The CAT310 is a 10-channel LED driver for automotive and other lighting applications. All LED output channels are driven from a low on- resistance open-drain High Voltage CMOS Nch-FETs and are fully compliant with “Load Dump” transients of up to 40 volts. The LED bias current of each channel can be set independently using an external series ballast resistor, making the device ideal for multi-color instrumentation displays. A high-speed serial interface (suitable with both 3.3 volt and 5 volt systems) feeding a 10 bit shift register is used to program the desired state (on/off) of each channel. The device offers a blanking control pin (BLANK) which can be used to disable all channels on demand. A serial output data pin (SOUT) is provided to daisy-chain devices in large cluster LED During initial power up all channels are reset and cleared via an under-voltage lock out (UVLO) detector and for added protection all channels are disabled in the event of a battery over-voltage condition (19 volts or more). For Ordering Information details, see page 10. TYPICAL APPLICATION CIRCUIT PIN DIAGRAM SOIC 20-pin package

© Catalyst Semiconductor, Inc. 2 Doc No. 25087, Rev. 1 Characteristics subject to change without notice ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit VCC voltage 7 V Input voltage range (SIN, SCLK, BLANK, XLAT) -0.3V to VCC+0.3V V SOUT voltage range -0.3V to VCC+0.3V V Peak OUT0 to OUT9 voltage 40 V VBATT input voltage 40 V DC output current on OUT0 to OUT9 70 mA Storage Temperature Range -55 to +160 °C Operating Junction Temperature Range -40 to +150 °C Lead Soldering Temperature (10sec.) 300 °C ESD Rating: Low Voltage Pins Human Body Model Machine Model 3000 300 V ESD Rating: VBATT, OUT[0:9] pins Human Body Model Machine Model 1000 100 V RECOMMENDED OPERATING CONDITIONS Parameter Range Unit VCC 3.0 to 5.5 V Voltage applied to OUT0 to OUT9 9 to 17 V Output current on OUT0 to OUT9 0 to 50 mA Ambient Temperature Range -40 to +125 °C ELECTRICAL OPERATING CHARACTERISTICS DC Characteristics VCC = 5.0V, -40ºC ≤ TA ≤ 125 ºC, over recommended operating conditions unless specified otherwise. Symbol Name Conditions Min Typ Max Units ISTBY Standby Quiescent Current Static input signal. All outputs turned off. 1 10 µA VOVP VBATT Over Voltage Protection Trigger threshold 17 19 21 V VUVLO VCC Under Voltage Lockout Trigger threshold 1.7 2.5 V RSW Switch on resistance for OUT0 to OUT9 IO(n) = 30mA 2 5 12 Ω IO(n)LKG OUT0 to OUT9 Output Switch Leakage V(OUT(n)) = 15V 0.1 10 µA IXLAT XLAT Internal Pull-down current XLAT = VCC XLAT = 0.3V µA IBLANK BLANK Internal Pull-up current BLANK = 0V BLANK = VCC - 0.3V µA VIH VIL Logic high input voltage Logic low input voltage

0.3 VCC

0.7V CC V IIL Logic Input leakage current (SCLK, SIN) VI = VCC or GND -5 0 5 µA VOH VOL SOUT logic high output voltage SOUT logic low output voltage IOH = -1mA IOL = 1mA VCC -0.3V 0.3 V

© Catalyst Semiconductor, Inc. 3 Doc No. 25087, Rev. 1 Characteristics subject to change without notice ELECTRICAL OPERATING CHARACTERISTICS Switching Characteristics VCC = 5.0V, -40ºC ≤ TA ≤ 125 ºC, over recommended operating conditions unless specified otherwise. Symbol Name Conditions Min Typ Max Units SCLK fSCLK SCLK Clock Frequency 10 MHz twh/wl SCLK Pulse width High or Low 30 ns SIN tsu Setup time SIN to SCLK 10 ns th Hold time SIN to SCLK 10 ns XLAT tw XLAT Pulse width SIN to SCLK 20 ns th Hold time SCLK to XLAT 20 ns tr SOUT rise time (10% to 90%) C L = 15pF 20 ns tf SOUT fall time (90% to 10%) C L = 15pF 15 ns tpd Propagation delay time Blank ↑ to OUT(n) 25 ns tpd Propagation delay time Blank ↓ to OUT(n) 25 ns tpd Propagation delay time SCLK to SOUT 25 ns All logic inputs contain Schmitt trigger inputs. BLOCK DIAGRAM

© Catalyst Semiconductor, Inc. 4 Doc No. 25087, Rev. 1 Characteristics subject to change without notice PIN DESCRIPTIONS VCC is the supply input for the internal logic and is compatible with both 3.3V and 5V systems. The logic is held in a reset state until VCC exceeds 2.5V. It is recommended that a small bypass ceramic capacitor (1uF) be placed between VCC and GND pins on the device. SIN is the CMOS logic pin for delivering the serial input data stream into the internal 10-bit shift register. The most recent or last data value in the serial stream is used to configure the state of output channel “zero” (OUT0). During the initial power up sequence all contents of the shift register are reset and cleared to zero. SCLK is the CMOS logic pin used to clock the internal shift register. On each rising edge of clock, the serial data will advance through one stage of the shift register. XLAT is the CMOS logic input used to transfer data from the 10-bit shift register into the output channel latches. An internal pull- down current of 10 microampere is present on this pin. When XLAT is low, the state of each output channel remains unchanged. When XLAT is driven high, the contents of the shift register appear at their respective output channels. An external pull-up resistance of 10kΩ or less is adequate for logic high. PGND, GND pins should be connected to the ground on the PCB. BLANK is the CMOS logic input (active high) used to temporarily disable all outputs. An internal pull-up current of 10 microampere is present on this pin. The BLANK pin must be driven to a logic low in order for channel outputs to resume normal operation. An external pull- down resistance of 10kΩ or less is adequate for logic low. SOUT is the CMOS logic output used for daisy chain applications. The serial output data stream is fed from the last stage of the internal 10-bit shift register. On each rising edge of the clock, the SOUT value will be updated. The data value present on this pin is identical to the data value being used for configuring the state of output channel nine (OUT9). At initial power up, the SOUT data stream will contain all zeroes until the shift register has been fully loaded. VBATT input monitors the battery voltage. If an over-voltage, above 19V typical, is detected, all outputs are disabled. Upon conclusion of the over-voltage condition, all outputs resume normal operation. The current drawn by the VBATT pin is less than 1 microampere during normal operation. OUT0-OUT9 are the ten LED outputs connected internally to the switch N-channel FETs. They sink currents up to 50mA per channel and can withstand transients up to 40V compatible with automotive “load dump”. The output on-resistance is 5 Ω, and the off- resistance is 5MΩ. PIN TABLE Pin Number Pin Name Description/Function 1 SCLK Clock input for the data shift register. 2 XLAT Control input for the data latch. 3 SIN Serial data input. 4 SOUT Serial data output. 5 GND Ground. 6-10 OUT4 - OUT0 Open drain outputs. 11-15 OUT9 - OUT5 Open drain outputs. 16 PGND Ground for LED driver outputs. 17 VBATT Battery sense input.

18 VCC Power supply voltage for the logic

19 BLANK Blank input. When BLANK is high, all the output drivers are turned off. 20 N.C. No connect.

© Catalyst Semiconductor, Inc. 5 Doc No. 25087, Rev. 1 Characteristics subject to change without notice TYPICAL CHARACTERISTICS VCC = 5V, VBATT = 14V, TAMB = 25ºC, unless otherwise specified. VBATT Overvoltage Detection Amplitude between 16V and 26V 18V XLAT pull-down Current vs. Input Voltage 012345 X LAT VOLTAGE [V] XLAT CURRENT [uA] -40ºC 85ºC125ºC 25ºC VBATT Load Dump 40V BLANK and Output waveform BLANK pull-up Current vs. Input Voltage 012345 BLANK VOLTAGE [V] BLANK CURRENT [uA]VCC = 5V -40ºC 85ºC 25ºC 125ºC Switch On-resistance vs. VCC 23456 VCC VOLTAGE [V] SWITCH ON RESISTANCE [ Ω] 25ºC 125ºC 85ºC -40ºC

© Catalyst Semiconductor, Inc. 6 Doc No. 25087, Rev. 1 Characteristics subject to change without notice TYPICAL CHARACTERISTICS VCC = 5V, VBATT = 14V, TAMB = 25ºC, unless otherwise specified. Output Channel Leakage vs. Bias Voltage 10 11 12 13 14 15 16 OUTPUT PIN BIAS VOLTAGE [V] OUTPUT PIN LEAKAGE [uA] 125ºC 25ºC85ºC -40ºC Quiescent Current vs. Temperature -50 -25 0 25 50 75 100 125 TEMPERATURE [ºC] QUIESCENT CURRENT[uA] VBATT Overvoltage Detection vs. Temperature -50 -25 0 25 50 75 100 125 TEMPERATURE [ºC] OVERVOLTAGE DETECTION [V] VCC Undervoltage Lockout vs. Temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - 5 0 - 2 502 5 5 0 7 5 1 0 0 1 2 5 TEMPERATURE [ºC] UNDERVOLTAGE LOCKOUT [V]

© Catalyst Semiconductor, Inc. 7 Doc No. 25087, Rev. 1 Characteristics subject to change without notice FUNCTIONAL DESCRIPTION The CAT310 implements a 10-bit serial-in shift register for storing the setting of the ten outputs. Serial input data SIN are clocked into the shift register on the rising edge of the clock. At the th clock pulse, the first data bit entered is outputted from the shift register to SOUT. The following clock pulses will output the following data bits onto SOUT. The output data pattern replicates the input data stream with a delay of ten clock pulses. The 10-bit data pattern present in the shift register is stored in the 10-bit data latch when the latch signal XLAT is logic high. When XLAT transitions to logic low, data are latched and stay unchanged for as long as XLAT remains low. The last serial input data corresponds to OUT0. The serial input data that was received 10 clock pulse ago is stored in OUT9. When the BLANK input is logic high, all the output switches are in the off state. If the BLANK input is low, the 10-bit data latches control the 10 output switches. A data bit value of zero keeps the switch off. A data bit value of one keeps the switch on. Serial to Parallel Shift Register CLK → SIN → Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 9 → SOUT XLAT → LED OUT0 LED OUT1 LED OUT2 LED OUT3 LED OUT4 LED OUT5 LED OUT6 LED OUT7 LED OUT8 LED OUT9 TIMING DIAGRAM

© Catalyst Semiconductor, Inc. 8 Doc No. 25087, Rev. 1 Characteristics subject to change without notice

APPLICATION INFORMATION

For applications with a large number of LEDs, several CAT310 drivers can be daisy chained. The serial data output pin (SOUT) of the first driver is connected to the second driver data input pin (SIN). This sequence is repeated until the last driver is linked. All drivers are controlled by the same clock signal. Figure 1 shows an example with three CAT310 devices driving a total of 30 LEDs in parallel. The controller transmits the serial data sequentially through the CAT310 devices. For N drivers connected in cascade, after 10 x N clock pulses, the data are latched with one single XLAT transition. Figure 1. Daisy Chain Application Diagram

© Catalyst Semiconductor, Inc. 9 Doc No. 25087, Rev. 1 Characteristics subject to change without notice PACKAGE OUTLINE DRAWING SOIC 20-Lead 300mils (W) Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. A2 θ E1 E e PIN#1 IDENTIFICATION b D c A TOP VIEW SIDE VIEW END VIEW θ1hh L SYMBOL MIN NOM MAX A 2.36 2.49 2.64 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.41 0.51 c 0.20 0.27 0.33 D 12.60 12.80 13.00 E 10.01 10.30 10.64 E1 7.40 7.50 7.60 e1 . 2 7 B S C h 0.25 0.75 L 0.40 0.81 1.27 θ 0° 8° θ15 ° 1 5 ° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

© Catalyst Semiconductor, Inc. 10 Doc No. 25087, Rev. 1 Characteristics subject to change without notice EXAMPLE OF ORDERING INFORMATION Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin. (3) The device used in the above example is a CAT310W–T1 (SOIC, Tape & Reel). Optional Company ID Package W: SOIC Prefix Device # Suffix CAT 310 W – T1 Product Number Tape & Reel T: Tape & Reel 1: 1000/Reel

© Catalyst Semiconductor, Inc. 11 Doc No. 25087, Rev. 1 Characteristics subject to change without notice

REVISION HISTORY

05/05/2005 00 Initial issue 08/22/2007 1 Update Ordering Information Update Package Outline Drawing Add Example of Ordering Information Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™ and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUAR ANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRO DUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARIS ING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconduct or product could creat e a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters

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Santa Clara, CA 95054 Phone: 408.542.1000 Document No: 25087 Fax: 408.542.1200 Revision: Rev. 1 www.catsemi.com Issue date: 08/22/07