CAT24AC128 CATALYST | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

DESCRIPTION

The CAT24AC128 is a 128kbit Serial CMOS EEPROM internally organized as 16,384 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24AC128 features a 64-byte page write buffer. The device operates * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. I Commercial, industrial and extended automotive temperature ranges I Write protect feature – Entire array protected when WP at V IH I 1,000,000 program/erase cycles I 100 year data retention I 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or 14-pin TSSOP via the I2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP packages. Three device address inputs allows up to 8 devices to share a common 2-wire I 2C bus. PIN CONFIGURATION BLOCK DIAGRAM I 400kHz (2.5V) and 100kHz (1.8V) I2C bus compatibility I 1.8 to 5.5 volt operation I Low power CMOS technology I Schmitt trigger filtered inputs for noise suppression I 64-Byte page write buffer I Self-timed write cycle with auto-clear

FEATURES

© 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice DOUT ACK SENSE AMPS SHIFT REGISTERS CONTROL LOGIC WORD ADDRESS BUFFERS START/STOP LOGIC STATE COUNTERS E2PROM 256X512 VCC EXTERNAL LOAD COLUMN DECODERS XDEC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL VSS WP SCL SDA 256 512 SLAVE ADDRESS COMPARATORS Doc. No. 1028, Rev. I NC NC SDA WP NC NC NC SCL NC VSS VCC14 CAT24AC128 128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins HALOGEN FREE TM LEAD F REE PIN FUNCTIONS Pin Name Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +5.5V Power Supply VSS Ground A0 - A2 Device Address Inputs

2Doc. No. 1028, Rev. I Symbol Parameter Test Conditions Min Typ Max Units ICC1 Power Supply Current - Read f SCL = 100 KHz 1 mA VCC = 5V ICC2 Power Supply Current - Write f SCL = 100 KHz 3 mA VCC = 5V ISB(5) Standby Current V IN = GND or VCC 1 µA VCC = 5V ILI Input Leakage Current V IN = GND to VCC 3 µA ILO Output Leakage Current V OUT = GND to VCC 3 µA VIL Input Low Voltage –1V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage (VCC = +3.0V) I OL = 3.0 mA 0.4 V VOL2 Output Low Voltage (VCC = +1.8V) I OL = 1.5 mA 0.5 V ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. CAPACITANCE T A = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Conditions Min Typ Max Units CI/O(3) Input/Output Capacitance (SDA) V I/O = 0V 8 pF CIN(3) Input Capacitance (SCL, WP, A0, A1, A2) V IN = 0V 6 pF Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriat e AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. (5) Maximum standby current (I SB) = 10µA for the Extended Automotive temperature range. D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Typ. Max. Units NEND(3) Endurance 1,000,000 Cycles/Byte TDR(3) Data Retention 100 Years VZAP(3) ESD Susceptibility 2000 Volts ILTH(3)(4) Latch-up 100 mA

3 Doc. No. 1028, Rev. I Power-Up Timing (1)(2) Symbol Parameter Min Typ Max Units tPUR Power-Up to Read Operation 1 ms tPUW Power-Up to Write Operation 1 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. FUNCTIONAL DESCRIPTION The CAT24AC128 supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24AC128 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter V CC = 1.8 V - 5.5 V V CC = 2.5 V - 5.5 V Min Max Min Max Units FSCL Clock Frequency 100 400 kHz tAA SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 µs and ACK Out tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time 4.0 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 100 100 ns tR(1) SDA and SCL Rise Time 1.0 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time 5 5 ms tSP Input Suppression (SDA, SCL) 100 100 ns

9 Doc. No. 1028, Rev. I Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 0.180 (4.57) MAX 0.015 (0.38) 0.100 (2.54) BSC 0.014 (0.36) 0.022 (0.56) 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65) 0.355 (9.02) 0.400 (10.16) 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 8-LEAD 150 MIL WIDE SOIC (J, W) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0 —8 0.0075 (0.19) 0.0098 (0.25) 0.0099 (0.25) 0.0196 (0.50) X 45 0.016 (0.40) 0.050 (1.27) 0.1890 (4.80) 0.1968 (5.00)

10Doc. No. 1028, Rev. I Note: 1. All linear dimensions are in inches and parenthetically in millimeters. 0.205 (5.20) 0.213 (5.40) 0.303 (7.70) 0.318 (8.10)

4 REF

0.008 (0.20) 0.025 (0.65) 0.0137 (0.35) 0.0177 (0.45) 0.080 (2.03) MAX 0.205 (5.15) 0.210 (5.35) 0.0267 (0.68) 0.054 (1.37) 8-LEAD 210 MIL WIDE SOIC (K, X) 14-LEAD TSSOP (U14, Y14)

7.72 TYP

4.16 TYP

(1.78 TYP)

0.42 TYP

0.65 TYP

LAND PATTERN RECOMMENDATION -B- 3.2 6.4 ABC0.2 14 8 4.4 + 0.1 ALL LEAD TIPS PIN #1 IDENT. 1 7 ALL LEAD TIPS 1.1 MAX TYP 0.1 C (0.9) 0.10 + 0.05 TYP 0.19 - 0.30 TYP

0.3 M A B S C S

0.09 - 0.20 TYP 0.6+0.1 SEATING PLANE GAGE PLANE 0.25 o - 8 o DETAIL A -C- -D- Dimension D Pkg Min Max 14 4.9 5.1

Catalyst Semiconductor, Inc. Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: 1028 Revison: I Issue date: 06/23/05 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE 2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.

REVISION HISTORY

Date Rev. Reason 07/7/2004 G Added Die Revision to Ordering Information Started revision history 07/27/2004 H Updated DC Operating Characteristics table and notes 06/23/2005 I Update Features Update Pin Functions Update Reliability Characteristics Update D.C. Operating Characteristics Update A.C. Characteristics Update Read Operations Update Figures 8, 9, 10 Add Figure 11 Update Ordering Information