CAT24AA02TDI-T

CAT24AA01 CATALYST | Alldatasheet

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Technical content

CAT24AA01, CAT24AA02 © Catalyst Semiconductor, Inc. 1 Doc. No. MD-1120 Rev. B Characteristics subject to change without notice 1-Kb and 2-Kb I2C CMOS Serial EEPROM

FEATURES

„ Supports Standard and Fast I2C Protocol „ 1.7 V to 5.5 V Supply Voltage Range „ 16-Byte Page Write Buffer „ Hardware Write Protection for entire memory „ Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) „ Low power CMOS technology „ 1,000,000 program/erase cycles „ 100 year data retention „ Industrial temperature range „ RoHS-compliant TSOT-23 5-lead and SOIC 8-lead packages

DESCRIPTION

The CAT24AA01/24AA02 are 1-Kb and 2-Kb CMOS Serial EEPROM devices internally or ganized as 128x8/256x8 bits. They feature a 16-byte page write buffer and support both the Standard (100kHz) and the Fast (400kHz) I2C protocols. In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02 have no external address pins, and are therefore suitable in applications that require a single CAT24AA01/02 on the I 2C bus. For Ordering Information details, see page 12. PIN CONFIGURATION SOIC (W) NC 1 8 V CC NC 2 7 WP NC 3 6 SCL VSS 4

5 SDA

TSOT-23 (TD) SCL 1 5 WP VSS 2 SDA 3 4 V CC * For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTIONS FUNCTIONAL SYMBOL Pin Name Function SDA Serial Data/Address SCL Clock Input WP Write Protect VCC Power Supply VSS Ground VCC VSS SDA SCL WP CAT24AA02 CAT24AA01

CAT24AA01, CAT24AA02 Doc. No. MD-1120 Rev. B 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice ABSOLUTE MAXIMUM RATINGS(1) Parameters Ratings Units Storage Temperature –65 to +150 ºC Voltage on any Pin with Respect to Ground(2) –0.5 to +6.5 V REABILITY CHARACTERISTICS(3) Symbol Parameter Min Units NEND (4) Endurance 1,000,000 Program/Erase Cycles TDR Data Retention 100 Years D.C. OPERATING CHARACTERISTICS V CC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions Min Max Units ICCR Read Current Read, f SCL = 400 kHz 0.5 mA ICCW Write Current Write 1 mA ISB Standby Current All I/O Pins at GND or V CC 1 μA IL I/O Pin Leakage Pin at GND or V CC 1 μA VIL Input Low Voltage -0.5 V CC x 0.3 V VIH Input High Voltage VCC x 0.7 V CC + 0.5 V VOL1 Output Low Voltage V CC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage V CC < 2.5 V, IOL = 1.0 mA 0.2 V PIN IMPEDANCE CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Conditions Max Units CIN (3) SDA I/O Pin Capacitance V IN = 0V 8 pF CIN (3) Input Capacitance (other pins) V IN = 0V 6 pF VIN < VIH 100 IWP (5) WP Input Current VIN > VIH 1 μA Notes: (1) Stresses above those listed under “Absol ute Maximum Ratings” may cause permanent damage to the device. These are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than V CC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropr iate AEC-Q100 and JEDEC test methods. (4) Page Mode @ 25°C (5) When not driven, the WP pin is pulled down to GND internal ly. For improved noise immunity, the internal pull-down is relat ively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC), the strong pull-down reverts to a weak current source.

CAT24AA01, CAT24AA02 © Catalyst Semiconductor, Inc. 3 Doc. No. MD-1120 Rev. B Characteristics subject to change without notice A.C. CHARACTERISTICS (1) VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C. Standard Fast Symbol Parameter Min Max Min Max Units FSCL Clock Frequency 100 400 kHz tHD:STA START Condition Hold Time 4 0.6 μs tLOW Low Period of SCL Clock 4.7 1.3 μs tHIGH High Period of SCL Clock 4 0.6 μs tSU:STA START Condition Setup Time 4.7 0.6 μs tHD:DAT Data In Hold Time 0 0 μs tSU:DAT Data In Setup Time 250 100 ns tR SDA and SCL Rise Time 1000 300 ns tF (2) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time 4 0.6 μs tBUF Bus Free Time Between STOP and START 4.7 1.3 μs tAA SCL Low to Data Out Valid 3.5 0.9 μs tDH Data Out Hold Time 100 100 ns Ti (2) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns tSU:WP WP Setup Time 0 0 μs tHD:WP WP Hold Time 2.5 2.5 μs tWR Write Cycle Time 5 5 ms tPU (2, 3) Power-up to Ready Mode 1 1 ms A.C. TEST CONDITIONS Notes: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. Input Levels 0.2 x V CC to 0.8 x VCC Input Rise and Fall Times ≤ 50ns Input Reference Levels 0.3 x V CC, 0.7 x VCC Output Reference Levels 0.5 x V CC Output Load Current Source: I OL = 3mA (VCC ≥ 2.5V); IOL = 1mA (VCC < 2.5V); CL = 100pF

CAT24AA01, CAT24AA02 Doc. No. MD-1120 Rev. B 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice POWER-ON RESET (POR) Each CAT24AA01/02 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after V CC exceeds the POR trigger level and w ill power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against brown-out failure, following a temporary loss of power. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and delivered on the negative edge of SCL. WP: When the Write Protect input pin is forced HIGH by an external source, all write operations are inhibited. When the pin is not driven by an external source, it is pulled LOW internally. FUNCTIONAL DESCRIPTION The CAT24AA01/02 supports the Inter-Integrated Circuit (I 2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Sl ave devices which execute requests. The CAT24AA01/02 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. I2C BUS PROTOCOL The 2-wire I 2C bus consists of two lines, SCL and SDA, connected to the V CC supply via pull-up resistors. The Master provides the clock to the SCL line, and the Master and Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by releasing it HIGH. Data tran sfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 1). A START is generated by a HIGH to LOW transition, while a STOP is generated by a LOW to HIGH transition. The START acts like a wake-up call. Absent a START, no Slave will respond to the Master. The STOP completes all commands. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address (Figure 2). The first four bits of the Slave address are 1010 (Ah). For the CAT24AA01/02 the next three bits must be 000. The last bit, R/W¯¯, instructs the Slave to either provide (1) or accept (0) data, i.e. it signals a Read (1) or a Write (0) request. Acknowledge During the 9 th clock cycle following every byte sent onto the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK ) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 3). Bus timing is illustrated in Figure 4.

CAT24AA01, CAT24AA02 Doc. No. MD-1120 Rev. B 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice WRITE OPERATIONS Byte Write To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W¯¯ bit set to ‘0’. The Master then sends an address byte and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress WR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 6). Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 16 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (t WR). Acknowledge Polling As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum speci fied Write time (t WR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the st data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh.

CAT24AA01, CAT24AA02 Doc. No. MD-1120 Rev. B 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W¯¯ bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a speci fic address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W¯¯ bit set to ‘0’ and then sends an address byte to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W¯¯ bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. For the CAT24AA01, the internal address counter will not wrap around at the end of the 128 byte memory space.

CAT24AA01, CAT24AA02 Doc. No. MD-1120 Rev. B 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice PACKAGE OUTLINE DRAWINGS SOIC 8-Lead 150mils (W) (1)(2) Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012. E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º SYMBOL MIN NOM MAX For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.

CAT24AA01, CAT24AA02 © Catalyst Semiconductor, Inc. 11 Doc. No. MD-1120 Rev. B Characteristics subject to change without notice TSOT 5-Lead (TD)(1)(2) Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-193. For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. θ E1 E e b D c A TOP VIEW SIDE VIEW END VIEW L SYMBOL MIN NOM MAX A1 . 0 0 A1 0.01 0.05 0.10 A2 0.80 0.87 0.90 b 0.30 0.45 c 0.12 0.15 0.20 D 2.90 BSC E 2.80 BSC E1 1.60 BSC e0 . 9 5 T Y P L 0.30 0.40 0.50 L1 0.60 REF L2 0.25 BSC θ 0º 8º

CAT24AA01, CAT24AA02 Doc. No. MD-1120 Rev. B 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice EXAMPLE OF ORDERING INFORMATION(1) Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard plated finish is NiPdAu. (3) The device used in the above example is a CAT24AA02TDI-GT3 (TSOT-23 5-lead, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Prefix Device # Suffix CAT 24AA02 TD I – G T3 Company ID Package TD: TSOT-23 5-lead W: SOIC 8-lead Temperature Range I: Industrial (-40ºC to 85ºC) Tape & Reel T: Tape & Reel 3: 3,000/Reel 10: 10,000/Reel Lead Finish G: NiPdAu Blank: Matte-Tin Product Number 24AA01 24AA02 For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp

REVISION HISTORY

Date Rev. Reason 12/07/2007 A Initial Issue 03/12/2008 B Add CAT24AA01 Add link to Product Top Mark Code Catalyst Semiconductor, Inc. Corporate Headquarters

2975 Stender Way

Santa Clara, CA 95054 Phone: 408.542.1000 Document No: MD-1120 Fax: 408.542.1200 Revision: B www.catsemi.com Issue date: 03/12/08 Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quant um Charge Programmable™ I2C™ is a trademark of Philips Corporati on. Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUAR ANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRO DUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARIS ING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconduct or product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any produ ct or service descr ibed herein without not ice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. Circuit diagrams illustrate typical semiconductor applications and may not be complete.