CAT22C10 CATALYST | Alldatasheet
Document overview
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Technical content
256-Bit Nonvolatile CMOS Static RAM
FEATURES
n Fast RAM Access Times: –200ns –300ns n Infinite E2PROM to RAM Recall n CMOS and TTL Compatible I/O n Power Up/Down Protection n 100,000 Program/Erase Cycles (E2PROM) n Low CMOS Power Consumption: –Active: 40mA Max. –Standby: 30 µA Max. n JEDEC Standard Pinouts: –18-pin DIP –16-pin SOIC n 10 Year Data Retention n Commercial, Industrial and Automotive Temperature Ranges
DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory organized as 64 words x 4 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile E 2PROM array which allows for easy transfer of data from RAM array to E2PROM (STORE) and from E2PROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typi- cally within 1.5µs. The CAT22C10 features unlimited RAM write operations either through external RAM PIN CONFIGURATION PIN FUNCTIONS Pin Name Function A0–A5 Address I/O0–I/O3 Data In/Out WE Write Enable CS Chip Select RECALL Recall STORE Store VCC +5V VSS Ground NC No Connect writes or internal recalls from E2PROM. Internal false store protection circuitry prohibits STORE operations when V CC is less than 3.0V. The CAT22C10 is manufactured using Catalyst’s ad- vanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (E 2PROM) and has a data retention of 10 years. The device is available in JEDEC approved 18-pin plastic DIP and 16- pin SOIC packages. © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice NC Vss CS STORE NC Vcc I/O3 I/O2 I/O1 I/O0 WE RECALL Vcc I/O4 I/O3 I/O2 I/O1 Vss WE CS STORE RECALL 22C10 F01 22C10 F02 Doc. No. 25018-0A 2/98 N-1
2Doc. No. 25018-0A 2/98 N-1 MODE SELECTION (1)(2)(3) Input Mode CSCSCSCSCS WEWEWEWEWE RECALLRECALLRECALLRECALLRECALL STORESTORESTORESTORESTORE I/O Standby H X H H Output High-Z RAM Read L H H H Output Data RAM Write L L H H Input Data (E2PROM → RAM) X H L H Output High-Z RECALL (E2PROM → RAM) H X L H Output High-Z RECALL (RAM → E2PROM) X H H L Output High-Z STORE (RAM → E2PROM) H X H L Output High-Z STORE BLOCK DIAGRAM POWER-UP TIMING (4) Symbol Parameter Min. Max. Units VCCSR V CC Slew Rate 0.5 0.005 V/ms Note: (1) RECALL signal has priority over STORE signal when both are applied at the same time. (2) STORE is inhibited when RECALL is active. (3) The store operation is inhibited when VCC is below ≈ 3.0V. (4) This parameter is tested initially and after a design or process change that affects the parameter. ROW SELECT COLUMN SELECT CONTROL LOGIC READ/WRITE CIRCUITS RECALL E2PROM ARRAY STOREA0 STORE RECALL CS WE I/O0 I/O1 I/O2 I/O3 STATIC RAM ARRAY
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3 Doc. No. 25018-0A 2/98 N-1 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method N END (1) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (1) Data Retention 10 Years MIL-STD-883, Test Method 1008 VZAP (1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (1)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Unit Conditions ICC Current Consumption 40 mA All Inputs = 5.5V (Operating) T A = 0°C All I/O’s Open ISB Current Consumption 30 µA CS = V CC (Standby) All I/O’s Open ILI Input Current 10 µA0 ≤ VIN ≤ 5.5V ILO Output Leakage Current 10 µA0 ≤ VOUT ≤ 5.5V VIH High Level Input Voltage 2 V CC V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage 2.4 V I OH = –2mA VOL Low Level Output Voltage 0.4 V I OL = 4.2mA VDH RAM Data Holding Voltage 1.5 5.5 V V CC CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Parameter Max. Unit Conditions C I/O(1) Input/Output Capacitance 10 pF V I/O = 0V C IN(1) Input Capacitance 6 pF V IN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to V CC +1V.
4Doc. No. 25018-0A 2/98 N-1 A.C. CHARACTERISTICS, Read Cycle VCC = +5V ±10%, unless otherwise specified. 22C10-20 22C10-30 Symbol Parameter Min. Max. Min. Max. Unit Conditions tRC Read Cycle Time 200 300 ns C L = 100pF tAA Address Access Time 200 300 ns +1TTL gate tCO CS Access Time 200 300 ns V OH = 2.2V tOH Output Data Hold Time 0 0 ns V OL = 0.65V tLZ(1) CS Enable Time 0 0 ns V IH = 2.2V tHZ (1) CS Disable Time 100 100 ns V IL = 0.65V A.C. CHARACTERISTICS, Write Cycle VCC = +5V ±10%, unless otherwise specified. 22C10-20 22C10-30 Symbol Parameter Min. Max. Min. Max. Unit Conditions tWC Write Cycle Time 200 300 ns tCW CS Write Pulse Width 150 150 ns tAS Address Setup Time 50 50 ns C L = 100pF tWP Write Pulse Width 150 150 ns +1TTL gate tWR Write Recovery Time 25 25 ns V OH = 2.2V tDW Data Valid Time 100 100 ns V OL = 0.65V tDH Data Hold Time 0 0 ns V IH = 2.2V tWZ (1) Output Disable Time 100 100 ns V IL = 0.65V tOW Output Enable Time 0 0 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
5 Doc. No. 25018-0A 2/98 N-1 A.C. CHARACTERISTICS, Store Cycle VCC = +5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Max. Units Conditions tSTC Store Time 10 ms tSTP Store Pulse Width 200 ns C L = 100pF + 1TTL gate tSTZ (1) Store Disable Time 100 ns V OH = 2.2V, VOL = 0.65V tOST (1) Store Enable Time 0 ns V IH = 2.2V, VIL = 0.65V A.C. CHARACTERISTICS, Recall Cycle VCC = +5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Max. Units Conditions tRCC Recall Cycle Time 1.4 µs tRCP Recall Pulse Width 300 ns C L = 100pF + 1TTL gate tRCZ Recall Disable Time 100 ns V OH = 2.2V, VOL = 0.65V tORC Recall Enable Time 0 ns V IH = 2.2V, VIL = 0.65V tARC Recall Data Access Time 1.1 µs Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
I/O path should be buffered. through the Input/Output pins (I/O0–I/O3). flexibility to use this part in battery operated systems. Figure 1. Read Cycle Timing
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address must be supplied for the byte being written. Figure 2. Write Cycle Timing
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Figure 3. Early Write Cycle Timing
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will be written to the specified location in the Static RAM.
accessed by using the normal read mode. immediately accessed by using the normal read mode. ber of times without affecting the integrity of the data. state as long as the RECALL signal is held low. system power is below 3.0V typ. Figure 4. Recall Cycle Timing
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Figure 5. Store Cycle Timing
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ORDERING INFORMATION
Notes: (1) The device used in the above example is a 22C10JI-20TE13 (SOIC, Industrial Temperature, 200ns Access Time, Tape & Reel) Prefix Device # Suffix 22C10 J I -TE13 Product Number Tape & Reel TE13: 2000/Reel Package P: PDIP J: SOIC (JEDEC) -20 Speed 20: 200ns 30: 300ns CAT Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C)* * -40˚ to +125˚C is available upon request Optional Company ID
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