CAT1021 CATALYST | Alldatasheet
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Technical content
DESCRIPTION
The CAT1021, CAT1022 and CAT1023 are complete memory and supervisory solutions for microcontroller- based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I 2C bus. The CAT1021 and CAT1023 provide a precision V CC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET) drives low whenever VCC falls below the reset threshold voltage. The CAT1022 has only a RESET output and does not have a Write Protect input. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high. All supervisors have a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or “hangs” the system. For the CAT1021 and CAT1022, the watchdog timer monitors the SDA signal. The CAT1023 has a separate watchdog timer interrupt input pin, WDI. CAT1021, CAT1022, CAT1023 Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
FEATURES
■ Precision power supply voltage monitor — 5V, 3.3V and 3V systems — Five threshold voltage options ■ Watchdog timer ■ Active high or low reset — Valid reset guaranteed at V CC = 1 V ■ 400kHz I2C bus ■ 3.0V to 5.5V operation ■ Low power CMOS technology ■ 16-Byte page write buffer ■ Built-in inadvertent write protection — WP pin (CAT1021) ■ 1,000,000 Program/Erase cycles ■ Manual reset input ■ 100 year data retention ■ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm foot-print) packages — TDFN max height is 0.8mm ■ Industrial and extended temperature ranges © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc No. 3009, Rev. K The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition, the RESET pin or a separate input, MR, can be used as an input for push-button manual reset capability. The on-chip, 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a V CC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up. Available packages include an 8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN package thickness is 0.8mm maximum. TDFN footprint options are 3x3mm. HALOGENFREE TM LEAD FREE
CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K BLOCK DIAGRAM Part Dash Minimum Maximum Number Threshold Threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 Threshold Voltage Options PIN CONFIGURATION (Bottom View) 0.8mm maximum height - (RD4, ZD4) MR VCC RESET SCL SDA RESET WP VSS CAT1021 MR VCC NC SCL SDA RESET NC VSS CAT1022 MR VCC SCL SDA RESET VSS CAT1023 VCC WDI RESET VCC NC SCL SDA MR RESET NC VSS CAT1022 VCC WDI SCL SDA MR RESET RESET VSS CAT1023 VCC RESET SCL SDA MR RESET WP VSS CAT1021 2kbit DOUT ACK SENSE AMPS SHIFT REGISTERS CONTROL LOGIC WORD ADDRESS BUFFERS START/STOP LOGIC EEPROM VCC EXTERNAL LOAD COLUMN DECODERS XDEC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL VSS SDA RESET Controller Precision Vcc Monitor STATE COUNTERS SLAVE ADDRESS COMPARATORS SC L RESET RESET MR WP (CAT1021) (CAT1021/23) WDI (CAT1023)
CAT1021, CAT1022, CAT1023 Doc No. 3009, Rev. K PIN DESCRIPTION RESET/RESETRESETRESETRESETRESET: RESET OUTPUTS (RESET CAT1021/23 Only) These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET pin must be connected through a pull-up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input. PIN FUNCTIONS Pin Name Function NC No Connect RESET Active Low Reset Input/Output VSS Ground SDA Serial Data/Address SCL Clock Input RESET Active High Reset Output (CAT1021/23) VCC Power Supply WP Write Protect (CAT1021 only) MR Manual Reset Input WDI Watchdog Timer Interrupt (CAT1023) CAT102X FAMILY OVERVIEW For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets. eciveD launaM teseR niPtupnI godhctaW godhctaW rotinoM niP etirW noitcetorP niP tnednepednI yrailixuA esneSegatloV evitcA:TESER WOLdnahgiH MORPEE 1201TAC ADS k2 2201TAC ADS k2 3201TAC IDW k2 4201TAC k2 5201TAC k2 6201TAC k2 7201TAC IDW k2 OPERATING TEMPERATURE RANGE Industrial -40 ˚C to 85˚C Extended -40 ˚C to 125˚C MR:MR:MR:MR:MR: MANUAL RESET INPUT Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor. WP (CAT1021 Only): WRITE PROTECT INPUT When WP input is tied to V SS or left unconnected write operations to the entire array are allowed. When tied to V CC, the entire array is protected. This input has an internal pull down resistor. WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active.
CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K ABSOLUTE MAXIMUM RATINGS Voltage on any Pin with Package Power Dissipation Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. Notes: 1. V IL min and VIH max are reference values only and are not tested. 2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. DC OPERATING CHARACTERISTICS VCC = 3.0V to 5.5V and over the recommended temperature conditions unless otherwise specified. lobmySr etemaraPs noitidnoCtseTn iMp yTx aMs tinU I IL tnerruCegakaeLtupnIV NI ccVotDNG=2 -0 1A µ I OL tnerruCegakaeLtuptuOV NI ccVotDNG=0 1-0 1A µ I 1CC )etirW(tnerruCylppuSrewoP f LCS zHk004= V CC V5.5= 3A m I 2CC )daeR(tnerruCylppuSrewoP f LCS zHk004= V CC V5.5= 1A m I BS tnerruCybdnatS ,V5.5=ccV V NI ccVroDNG= 06A µ V LI )1( egatloVwoLtupnI5 .0-c cVx3.0V V HI )1( egatloVhgiHtupnIc cVx7.05 .0+ccVV V LO egatloVwoLtuptuO ,ADS( TESER ) I LO Am3= V CC V7.2= 4.0V V HO egatloVhgiHtuptuO )TESER( I HO Am4.0-= V CC V7.2= -ccV 57.0 V V HT dlohserhTteseR 54-x201TAC V 24-x201TAC 03-x201TAC 82-x201TAC 52-x201TAC V DILAVR VdilaVtuptuOteseR CC egatloV0 0.1V V TR )2( siseretsyHdlohserhTteseR5 1V m
CAT1021, CAT1022, CAT1023 Doc No. 3009, Rev. K CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Test Conditions Max Units COUT(1) Output Capacitance V OUT = 0V 8 pF CIN(1) Input Capacitance V IN = 0V 6 pF AC CHARACTERISTICS VCC = 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified. Notes: 1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 2. Test Conditions according to “AC Test Conditions” table. 3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cyc le. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. elcyCetirW&daeRyromeM )2( lobmySr etemaraPn iMx aMs tinU f LCS ycneuqerFkcolC0 04z Hk t PS ekipSretliFtupnI )LCS,ADS(noisserppuS 001s n t WOL doirePwoLkcolC3 .1s µ t HGIH doirePhgiHkcolC6 .0s µ tR )1( emiTesiRLCSdnaADS0 03s n tF )1( emiTllaFLCSdnaADS0 03s n t ATS;DH emiTdloHnoitidnoCtratS6 .0s µ t ATS;US emiTputeSnoitidnoCtratS )tratSdetaepeRarof( 6.0s µ t TAD;DH emiTdloHtupnIataD0 s n t TAD;US emiTputeStupnIataD0 01s n t OTS;US emiTputeSnoitidnoCpotS6 .0s µ t AA dilaVtuOataDotwoLLCS0 09s n t HD emiTdloHtuOataD0 5s n t FUB )1( aerofeBeerFebtsumsuBehtemiT tratSnaCnoissimsnarTweN 3.1s µ t CW )3( )egaProetyB(emiTelcyCetirW5 s m
CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K RESET CIRCUIT AC CHARACTERISTICS Notes: 1. Test Conditions according to “AC Test Conditions” table. 2. Power-up, Input Reference Voltage V CC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 3. Power-Down, Input Reference Voltage V CC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 4. V CC Glitch Reference Voltage = VTHmin; Based on characterization data 5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. t PUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. 7. Latch-up protection is provided for stresses up to 100 mA on input and output pins from -1 V to V CC + 1 V. AC TEST CONDITIONS lobmySr etemaraP tseT snoitidnoC niMp yTx aMs tinU t TSRUP tuoemiTteseR2 etoN0 310 020 72s m t DPR V HT yaleDtuptuOTESERot3 etoN5 s µ t HCTILG V CC htdiWesluPtcejeRhctilG5 ,4etoN0 3s n hctilGRMy tinummIhctilGteseRlaunaM1 etoN0 01s n t WRM htdiWesluPRM1 etoN5 s µ t DRM yaleDtuptuOTESERottupnIRM1 etoN1 s µ t DW tuoemiTgodhctaW1 etoN0 .16 .13 .2c es GNIMITPU-REWOP 6,5 lobmySr etemaraP tseT snoitidnoC niMp yTx aMs tinU t RUP noitarepOdaeRotpU-rewoP 072s m t WUP noitarepOetirWotpU-rewoP 072s m retemaraPs noitidnoCtseT segatloVesluPtupnIV 2.0 CC V8.0ot CC semitllaFdnaesiRtupnIs n01 segatloVecnerefeRtupnIV 3.0 CC V7.0, CC segatloVecnerefeRtuptuOV 5.0 CC daoLtuptuO I:ecruoStnerruC LO ;Am3= CL Fp001= RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Max Units NEND(5) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(5) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(5) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(5)(7) Latch-Up JEDEC Standard 17 100 mA
CAT1021, CAT1022, CAT1023 Doc No. 3009, Rev. K embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2V. In addition, the CAT1021 includes a Write Protection Input which when tied to V CC will disable any write operations to the device. Watchdog Timer The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, CAT1021/ 22/23 devices will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. The CAT1023 is designed with the Watchdog timer feature on the WDI pin. The CAT1021 and CAT1022 monitor the SDA line. If WDI or SDA does not toggle within a 1.6 second interval, the reset condition will be generated on the reset outputs. The watchdog timer is cleared by any transition on a monitored line. As long as reset signal is asserted, the watchdog timer will not count and will stay cleared. DEVICE OPERATION Reset Controller Description The CAT1021/22/23 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs. During power-up, the RESET outputs remain active until V CC reaches the V TH threshold and will continue driving the outputs for approximately 200ms (t PURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors. During power-down, the RESET outputs will be active when V CC falls below V TH. The RESET output will be valid so long as V CC is >1.0V (VRVALID). The device is designed to ignore the fast negative going VCC transient pulses (glitches). Reset output timing is shown in Figure 1. Manual Reset Operation The RESET pin can operate as reset output and manual reset input. The input is edge triggered; that is, the RESET input will initiate a reset timeout after detecting a high to low transition. When RESET I/O is driven to the active state, the 200 msec timer will begin to time the reset interval. If external reset is shorter than 200 ms, Reset outputs will remain active at least 200 ms. The CAT1021/22/23 also have a separate manual reset input. Driving the MR input low by connecting a pushbutton (normally open) from MR pin to GND will generate a reset condition. The input has an internal pull up resistor. Reset remains asserted while MR is low and for the Reset Timeout period after MR input has gone high. Glitches shorter than 100 ns on MR input will not generate a reset pulse. No external debouncing circuits are required. Manual reset operation using MR input is shown in Figure 2. Hardware Data Protection The CAT1021/22/23 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. Whenever the device is in a Reset condition, the
then proceed with the next read or write operation. acknowledge after the first byte of data is received. Figure 10. Immediate Address Read Timing
CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. Dimension D Pkg Min Max 0.180 (4.57) MAX 0.015 (0.38) 0.100 (2.54) BSC 0.014 (0.36) 0.022 (0.56) D 0.245 (6.17) 0.295 (7.49) 0.045 (1.14) 0.060 (1.52) 0.110 (2.79) 0.150 (3.81) 0.120 (3.05) 0.150 (3.81) 0.300 (7.62) 0.325 (8.26) 0.310 (7.87) 0.380 (9.65)
CAT1021, CAT1022, CAT1023 Doc No. 3009, Rev. K 8-LEAD 150 MIL WIDE SOIC (J, W) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 3. Lead coplanarity is 0.004" (0.102mm) maximum. 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) D 0°–8° 0.0075 (0.19) 0.0098 (0.25) 0.0099 (0.25) 0.0196 (0.50) X 45° 0.016 (0.40) 0.050 (1.27) Dimension D Pkg Min Max
CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K 8-LEAD TSSOP (U, Y)
CAT1021, CAT1022, CAT1023 Doc No. 3009, Rev. K
8 LEAD MSOP (R, Z)
0.0150 0.0110 0.38 0.28 0.1970 0.1890 5.00 4.80 S 0.0256 [0.65] BSC 0.1220 0.1142 3.10 2.90 0.0433 [1.10] MAX. 0.039 [0.10] MAX. S 0.0059 0.0020 0.15 0.05 S 0.0374 0.0295 0.95 0.75 0.0276 0.0157 0.70 0.40 0.1220 0.1142 3.10 2.90 0˚ - 6˚ 0.0091 0.0051 0.23 0.13 0.0118 [0.30] REF. BASE METAL 0.0050 [0.127] 0.0150 0.0110 0.38 0.28 WITH PLATING SECTION A - A WITH PLATING Notes: (1) All dimensions are in mm Angles in degrees. 2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per si de. 3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side. 4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm. (5) This part is compliant with JEDEC Specification MO-187 Variations AA. (6) Lead span/stand off height/coplanarity are considered as special characteristics. (S) (7) Controlling dimensions in inches. [mm]
CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K 3.00 + 0.10 (S) 1 4 3.00 + 0.10 (S) PIN 1 INDEX AREA C 0.75 + 0.05 0.0 - 0.05 0.30 + 0.07 (8x) 0.25 min. 0.75 + 0.05A B 2.30 + 0.10 C0.35 PIN 1 ID 1.50 + 0.10 1.95 REF. (2x) 0.65 TYP. (6x) 0.30 + 0.10 (8x)1 0.15 0.15 C C NOTE: 1. ALL DIMENSION ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY SHALL NOT EXCEED 0.08 mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S) 5. REFER JEDEC MO-229 / WEEC TDFN 3X3 PACKAGE (RD4, ZD4)
CAT1021, CAT1022, CAT1023 Doc No. 3009, Rev. K
Ordering Information
Note: (1) The device used in the above example is a CAT1021JI-30TE13 (Supervisory circuit with I2C serial 2k CMOS EEPROM, SOIC, Industrial Temperature, 3.0-3.15V Reset Threshold Voltage, Tape and Reel). 1021 Temperature Range I = Industrial (-40˚C to 85˚C) Prefix Device # Suffix J I Product Number 1021: 2K Package P: PDIP J: SOIC R: MSOP U: TSSOP RD4: 8-pad TDFN (3x3mm) L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free) ZD4: TDFN 3x3mm (Lead free, Halogen free) -30CAT Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V Optional Company ID 1022: 2K 1023: 2K E = Extended (-40˚C to +125˚C) TE13 Tape & Reel SOIC: 2000/Reel TSSOP: 2000/Reel MSOP: 2500/Reel TDFN: 2000/Reel
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REVISION HISTORY
Date Rev. Reason 9/25/2003 F Added Green Package logo Updated DC Operating Characteristic notes Updated Reliability Characteristics notes 11/7/2003 G Eliminated Automotive temperature range Updated Ordering Information with “Green” package codes Updated Reset Circuit AC Characteristics 4/12/2004 H Eliminated data sheet designation Updated Reel Ordering Information 11/1/2004 I Eliminated 8-pad TDFN package (3x4.9mm) Changed SOIC package designators Added package outlines 11/04/04 J Update Pin Configuration 11/11/04 K Update Features Update Description Updae DC Operating Characteristic Update AC Characteristics