C9531 CYPRESS | Alldatasheet
Document overview
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Technical content
Features
- Dedicated clock buffer power pins for reduced noise, crosstalk and jitter Input clock frequency of 25 MHz to 33 MHz Output frequencies of XINx1, XINx2, XINx3 and XINx4 One output bank of 5 clocks. One REF XIN clock output. SMBus clock control interface for individual clock disabling and SSCG control Output clock duty cycle is 50% (± 5%) < 250 ps skew between output clocks within a bank Output jitter <175 ps Spread Spectrum feature for reduced electromagnetic interference (EMI) OE pin for entire output bank enable control and testability 28-pin SSOP and TSSOP packages Note: 1. XIN is the frequency of the clock on the device’s XIN pin.
Table 1. Test Mode Logic Table[1]
Document #: 38-07034 Rev. *D Page 2 of 10 Notes: 2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. 3. A bypass capacitor (0.1µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the trace. 4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s). Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts block write a opera- tions from the controller. The bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The C9531 does not support the Block Read function. The block write protocol is outlined in Table 2. The addresses are listed in Table 3. Pin Description[3] Pin[2] Name PWR [4] I/O Description 3X I N V D D A I Crystal Buffer Input Pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. 4X O U T V D D A O Crystal Buffer Output Pin. Connects to a crystal only. When a Can Oscillator is used or in test mode, this pin is kept unconnected.
1 REF VDD O Buffered inverted outputs of the signal applied at Xin, typically
33.33 or 25.0 MHz. 14* OE VDD I Output Enable for Clock Bank. Causes the CLK (0:4) output clocks to be in a three-state condition when driven to a logic low level. 24, 23, 22, 19, 18 CLK(0:4) VDDP O A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
8 GOOD# VDD O When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock. This output is latched. 6*, 7* S(0,1) VDD I Clock Bank Selection Bits. These control the clock frequency that will be present on the outputs of the bank of buffers. See table on page one for frequency codes and selection values. 20, 25 VDDP PWR 3.3V common power supply pin for all PCI clocks CLK (0:4). 10*, 11*, 12* IA(0:2) VDD I SMBus Address Selection Input Pins. See Table 3 on page 3. 15* SSCG# VDD I Spread Spectrum Clock Generator. Enables Spread Spectrum clock modulation when at a logic low level, see Spread Spectrum Clocking on page 6. 28 SDATA VDD I/O Data for the Internal SMBus Circuitry. See Table 3 on page 3. 27 SCLK VDD I Clock for the Internal SMBus Circuitry. See Table 3 on page 3. 13, 17 VDDA I Power for Internal Analog Circuitry. This supply should have a separately decoupled current source from VDD. 2V D D P W R Power supply for internal core logic. 5, 9, 16, 21, 26 VSS PWR Ground pins for the device.
Table 2. Block Read and Block Write Protocol
9 Write = 0
10 Acknowledge from slave
19 Acknowledge from slave
28 Acknowledge from slave
37 Acknowledge from slave
46 Acknowledge from slave
Table 3. SMBus Address Selection Table 7 1 TESTEN Test Mode Enable.
Table 4. Clarification Table for Byte0, bit 5 Table 5. Test Table
71 R e s e r v e d
61 R e s e r v e d
41 R e s e r v e d
31 R e s e r v e d
21 R e s e r v e d
11 R e s e r v e d
01 R e s e r v e d
51 R e s e r v e d
Document #: 38-07034 Rev. *D Page 5 of 10 Output Clock Three-state Control All of the clocks in the Bank may be placed in a three-state condition by bringing their relevant OE pins to a logic low state. This transition to and from a three-state and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a board level testing feature. When output clocks are being enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner. The output enable pin contains an internal pull-up resistor that will insure that a logic 1 is maintained and sensed by the device if no external circuitry is connected to this pin. Output Clock Frequency Control All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of these control signals is determined by the SMBus register Byte 0 bit 0. At initial power up this bit is set of a logic 1 state and thus the frequency selections are controlled by the logic levels present on the device’s S(0,1) pins. If the application does not use an SMBus interface then hardware frequency selection S(0,1) must be used. If it is desired to control the output clocks using an SMBus interface, then this bit (B0b0) must first be set to a low state. After this is done the device will use the contents of the internal SMBus register Bytes 0 bits 3 and 4 to control the output clock’s frequency. The following formula and schematic may be used to under- stand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. where: C XTAL = The load rating of the crystal. C XINFTG = The clock generators XIN pin effective device internal capacitance to ground. C XOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground. C XINPCB = The effective capacitance to ground of the crystal to device PCB trace. C XOUTPCB = The effective capacitance to ground of the crystal to device PCB trace. C XINDISC = Any discrete capacitance that is placed between the XIn pin and ground. C XOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground. As an example and using this formula for this data sheet’s device, a design that has no discrete loading capacitors DISC ) and each of the crystal device PCB traces has a capacitance (CPCB ) to ground of 4 pF (typical value) would calculate as: Therefore, to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20 pF. XINPCB + CXINFTG + CXINDISC ) x (CXOUTPCB ) + CXOUTFTG ) + CXOUTDISC ) (CXINPCB + CXINFTG + CXINDISC ) + (CXOUTPCB ) + CXOUTFTG ) + CXOUTDISC )C L = CXINPCB CXOUTPCB CXOUTDISC CXINDISC CXINFTG CXOUTFTG XIN XOUT Clock Generator (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) C L = 40 x 40 40 x 40= = 1600 80 = 20 pF.
greater extent, at all of its harmonics. pin 15 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. SMBus byte 0 bit 6 low to set the feature active.
- When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100-MHz output clock
frequency will sweep through a spectral range from 99 to 100 MHz. Table 6. Spectrum Spreading Selection Table[5] Figure 1. Spread Spectrum
Document #: 38-07034 Rev. *D Page 7 of 10 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD,VDDP Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 V DD + 0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESD HBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V Ø JC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 °C/W Ø JA Dissipation, Junction to Ambient JEDEC (JESD 51) °C/W UL–94 Flammability Rating At 1/8 in. V–0 MSL Moisture Sensitivity Level 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Parameter Description Condition Min. Max. Unit VDD , VDDP, VDDA 3.3V Operating Voltage 3.3V ± 5% 3.135 3.465 V VILI2C Input Low Voltage SDATA, SCLK – 1 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – – VIL Input Low Voltage V SS –0.5 0.8 V VIH Input High Voltage 2.0 V DD +0. 5 V IIL Input Leakage Current except Pull-ups or Pull-downs 0 < VIN < VDD –5 5 µA VOL Output Low Voltage I OL = 1 mA – 0.4 V VOH Output High Voltage I OH = –1 mA 2.4 – V IOZ High-Impedance Output Current –10 10 µA C IN Input Pin Capacitance 2 5 pF C OUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH C XTAL Crystal Pin Capacitance From XIN and XOUT pins to ground 32 38 pF VXIH Xin High Voltage 0.7V DD VDD V VXIL Xin Low Voltage 0 0.3V DD V IDD Dynamic Supply Current At 133 MHz and all outputs loaded per Table 7 – 300 mA IPD Power-down Supply Current PD# Asserted – 1 mA Parameter Description Condition Min. Max. Unit Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70% 45 55 % XINFREQ XIN Frequency When Xin is driven from an external clock source 25 33.3 MHz TR / TF XIN Rise and Fall Times Measured between 0.3V DD and 0.7VDD –1 0 . 0 n s
Document #: 38-07034 Rev. *D Page 8 of 10 Test and Measurement Set-up TCCJ XIN Cycle to Cycle Jitter As an average over 1µs duration – 500 ps LACC Long Term Accuracy Over 150 ms 300 ppm CLK TDC CLK Duty Cycle Measurement at 1.5V 45 55 % TPERIOD33 33-MHz CLK Period Measurement at 1.5V 29.5 30.5 ns TPERIOD66 66-MHz CLK Period Measurement at 1.5V 14.5 15.5 ns TPERIOD100 100-MHz CLK Period Measurement at 1.5V 9.5 10.5 ns TPERIOD133 133-MHz CLK Period Measurement at 1.5V 7.0 8.0 ns TR / TF CLK Rise and Fall Times Measured between 0.4V and 2.4V 0.5 2.0 ns TSKEW Any CLK to Any CLK Clock Skew Measurement at 1.5V – 250 ps TCCJ CLK Cycle to Cycle Jitter Measurement at 1.5V – 175 ps REF TDC REF Duty Cycle Measurement at 1.5V 45 55 % TR / TF REF Rise and Fall Times Measured between 0.4V and 2.4V 1.0 4.0 ns TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 750 ps ENABLE/DISABLE and SET-UP tpZL,tpZH Output Enable Delay (all outputs) – 10.0 ns tpLZ,tpZH Output Disable Delay (all outputs) – 10.0 ns T STABLE Clock Stabilization from Power-up – 3.0 ms Parameter Description Condition Min. Max. Unit 2.4V 0.4V 3.3V Tr Tf 1.5V 3.3V Si gnal s tD C - - Probe O utput under Test Load Cap Lumped Load LVTTL Signaling Figure 2. Test and Measurement Set-up Table 7. Loading
Ordering Information
Part Number Package Type Product Flow IMIC9531CY 28-Pin SSOP Commercial, 0° to 70°C IMIC9531CYT 28-Pin SSOP – Tape and Reel Commercial, 0° to 70°C IMIC9531CT 28-Pin TSSOP Commercial, 0° to 70°C IMIC9531CTT 28-Pin TSSOP – Tape and Reel Commercial, 0° to 70°C
Document #: 38-07034 Rev. *D Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.. Package Drawing and Dimension All product and company names mentioned in this document may be the trademarks of their respective holders. 28-lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C 28-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z29 51-85120-**
Document #: 38-07034 Rev. *D Page 10 of 10 Document History Page Document Title: C9531 PCIX I/O System Clock Generator with EMI Control Features Document #: 38-07034 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106962 06/12/02 IKA Convert from IMI to Cypress *A 114504 08/15/02 DMG Converted from Word to Frame Corrected Ordering Information by adding tape and reel option IMIC9531CYT and IMIC9531CTT to match the Devmaster *B 120839 11/25/02 RGL/ DMG Corrected the Package Drawing and Dimension from 28 TSOP to 28 TSSOP Removed the read function in the SMBus Area *C 122727 12/14/02 RBI Added power up requirements to maximum ratings information *D 126597 05/14/03 RGL Fixed DC and AC table to match characteristic data Added 25-MHz Operation