Microcontroller

BS83B08A-4

Holtek Semiconductor In...

Touch Flash MCU

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Revision: V1.61 Date: April 11, 2017

Rev. 1.61 2 April 11, 2017 Rev. 1.61 3 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Table of Contents

Rev. 1.61 2 April 11, 2017 Rev. 1.61 3 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

Rev. 1.61 4 April 11, 2017 Rev. 1.61 5 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

Features

Operating V oltage ♦ For BS83B04A-4 – fSYS=8MHz: 2.2V~5.5V ♦ For BS83B08A-3/BS83B12A-3/BS83B16A-3 – fSYS=8MHz: 2.7V~5.5V – fSYS=12MHz: 2.7V~5.5V – fSYS=16MHz: 4.5V~5.5V ♦ For BS83B08A-4/BS83B12A-4/BS83B16A-4 – fSYS=8MHz: 2.2V~5.5V – fSYS=12MHz: 2.7V~5.5V – fSYS=16MHz: 4.5V~5.5V
Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
Fully integrated 4/8/12/16 touch key functions -- require no external components
Power down and wake-up functions to reduce power consumption
Fully integrated low and high speed internal oscillators
Low Speed -- 32kHz
High speed -- 8MHz, 12MHz, 16MHz
Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
All instructions executed in one or two instruction cycles
Table read instructions
63 powerful instructions
Up to 4-level subroutine nesting
Bit manipulation instruction Peripheral Features
Flash Program Memory: 2K×16
RAM Data Memory: 128×8~288×8
True EEPROM Memory: 32×8~64×8
Watchdog T imer function
Up to 22 bidirectional I/O lines
External interrupt line shared with I/O pin
Single 8-bit T imer/Event Counter
Single T ime-Base function for generation of fixed time interrupt signals
I2C for all devices and SPI interface for the devices except BS83B04A-4
Low voltage reset function
4/8/12/16 touch key functions
High current LED driver

Rev. 1.61 6 April 11, 2017 Rev. 1.61 7 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU General Description These devices are a series of Flash Memory type 8-bit high performance RISC architecture microcontrollers with fully integrated touch key functions. W ith all touch key functions provided internally and with the convenience of Flash Memory multi-programming features, this device range has all the features to of fer designers a reliable and easy means of impl ementing T ouch Keys within their products applications. The t ouch ke y func tions a re ful ly i ntegrated c ompletely e liminating t he ne ed for e xternal components. In addition to the flash program memory , other memory includes an area of RAM Data M emory as w ell as an area of true EEPRO M memory for s torage of non-volatile data s uch as serial numbers, calibration data etc. Protective features such as an internal W atchdog T imer and Low V oltage Reset functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. All d evices i nclude f ully i ntegrated l ow a nd h igh sp eed o scillators wh ich r equire n o e xternal components for their implementation. T he ability to operate and switch dynamically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the internal I2C and SPI inter faces, while the inclusion of flexible I/O programming features, Timer/Event Counters and many other features further enhance device functionality and flexibility. These touch key devices will find excellent use in a huge range of modern T ouch Key product applications such as instrumentatio n, household appliances, electronic ally controlled tools to name but a few. Selection Table Most features are common to all devices, the main distinguishing feature is the number of I/Os and Touch Keys. The following table summarises the main features of each device. Part No. Internal Clock VDD System Clock Program Memory Data Memory Data EEPROM I/O High Current LED Output 8-bit Timer Time Base Touch Key SPI/ I2C LVR Stack Package Marking BS83B04A-4 8MHz 2.2V~ 5.5V 8MHz 2K×16 128×8 32×8 8 ― 1 1 4 1 2.10V 4 8SOP 10MSOP BS83B04A-4 BS83B04A-4 (for 8SOP) 83B04A4 (for 10MSOP) BS83B08A-3 8MHz 12MHz 16MHz 2.7V~ 5.5V 8MHz~ 16MHz 2K×16 160×8 64×8 14 ― 1 1 8 1 2.55V 4 16NSOP 16SSOP ― BS83B08A-4 8MHz 12MHz 16MHz 2.2V~ 5.5V 8MHz~ 16MHz 2K×16 160×8 64×8 14 ― 1 1 8 1 2.10V 4 16NSOP 16SSOP ― BS83B12A-3 8MHz 12MHz 16MHz 2.7V~ 5.5V 8MHz~ 16MHz 2K×16 288×8 64×8 18 18 1 1 12 1 2.55V 4 20SOP 20SSOP ― BS83B12A-4 8MHz 12MHz 16MHz 2.2V~ 5.5V 8MHz~ 16MHz 2K×16 288×8 64×8 18 18 1 1 12 1 2.10V 4 20SOP 20SSOP ― BS83B16A-3 8MHz 12MHz 16MHz 2.7V~ 5.5V 8MHz~ 16MHz 2K×16 288×8 64×8 22 22 1 1 16 1 2.55V 4 24SOP 24SSOP ― BS83B16A-4 8MHz 12MHz 16MHz 2.2V~ 5.5V 8MHz~ 16MHz 2K×16 288×8 64×8 22 22 1 1 16 1 2.10V 4 24SOP 24SSOP ―

Rev. 1.61 6 April 11, 2017 Rev. 1.61 7 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Block Diagram 8-bit RISC MCU Core Flash Program Memory Flash Programming Circuitry Time Base Low Voltage Reset LIRC Oscillator 8-bit Timer Watchdog Timer HIRC Oscillator RAM Data Memory SIMTouch Keys Flash Program Memory I/O Stack Interrupt Controller Note: SPI for all devices except BS83B04A-4. Pin Assignment PA5/Key1 PA1/Key2 PA3/Key3 PA4/Key4 VDD VSS PA2/SDA/ICPCK PA0/INT/SCL/ICPDA BS83B04A-4

8 SOP-A

PA6/[INT] PA7 BS83B04A-4

10 MSOP-A

PA6/[INT] PA7 BS83BV04A

16 NSOP-A

BS83B08A-3/BS83B08A-4/83V08AV15

16 NSOP-A/SSOP-A

BS83B12A-3/BS83B12A-4/BS83V12A

20 SOP-A/SSOP-A

BS83B16A-3/BS83B16A-4/BS83V16A

24 SOP-A/SSOP-A

Note: The OCDSD A and OCDSCK pins are used for OCDS function while the ICPDA and ICPCK pins are used for ICP function.

Rev. 1.61 8 April 11, 2017 Rev. 1.61 9 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Pin Descriptions The function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in other sections of the datasheet. BS83B04A-4 Pin Name Function OPT I/T O/T Description PA0/INT/SCL/ ICPDA/OCDSDA PA0 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT SFS ST — External interrupt SCL IICC0 ST NMOS I2C clock ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1/KEY2 PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up KEY2 TKM0C1 NSI — Touch key inputs PA2/SDA/ ICPCK/OCDSCK PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDA — ST NMOS I2C data ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. PA3/KEY3 PA3 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up KEY3 TKM0C1 NSI — Touch key inputs PA4/KEY4 PA4 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up KEY4 TKM0C1 NSI — Touch key inputs PA5/KEY1 PA5 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up KEY1 TKM0C1 NSI — Touch key inputs PA6/[INT] PA6 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT SFS ST — External interrupt PA7 PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up VDD VDD — PWR — Power supply * VSS VSS — PWR — Ground ** Note: I/T: Input type; O/T : Output type OP: Optional by register selection; PWR: Power ST: Schmitt Trigger input; CMOS: CMOS output NMOS: NMOS output; NSI: Non-standard input *: VDD is the device power supply while AVDD is the touch key circuit power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the touch key circuit ground pin. The AVSS pin is bonded together internally with VSS.

Rev. 1.61 8 April 11, 2017 Rev. 1.61 9 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU BS83B08A-3/BS83B08A-4 Pin Name Function OPT I/T O/T Description PA0/SDI/ SDA/ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDI — ST — SPI data input SDA — ST NMOS I2C data ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1/SDO PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDO SIMC0 — CMOS SPI data output PA2/SCK/ SCL/ICPCK/ OCDSCK PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCK SIMC0 ST CMOS SPI serial clock SCL SIMC0 ST NMOS I 2C clock ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. PA3/SCS PA3 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCS SIMC0 ST CMOS SPI slave select PA4/INT PA4 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT INTEG ST — External interrupt PA7 PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PB0/KEY1~ PB3/KEY4 PB0~PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up KEY1~KEY4 TKM0C1 NSI — Touch key inputs PB4/KEY5~ PB7/KEY8 PB4~PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up KEY5~ KEY8 TKM1C1 NSI — Touch key inputs VDD VDD — PWR — Power supply * AVDD AVDD — PWR — Touch Key Circuit PWR and it should be double bonded to VDD* VSS VSS — PWR — Ground AVSS AVSS — PWR — Touch Key Circuit PWR and it should be double bonded to VSS Note: I/T: Input type; O/T : Output type OP: Optional by register selection; PWR: Power ST: Schmitt Trigger input; CMOS: CMOS output NMOS: NMOS output; NSI: Non-standard input *: VDD is the device power supply while AVDD is the touch key circuit power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the touch key circuit ground pin. The AVSS pin is bonded together internally with VSS.

Rev. 1.61 10 April 11, 2017 Rev. 1.61 11 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU BS83B12A-3/BS83B12A-4 Pin Name Function OPT I/T O/T Description PA0/SDI/ SDA/ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDI — ST — SPI data input SDA — ST NMOS I2C data ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1/SDO PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDO SIMC0 — CMOS SPI data output PA2/SCK/ SCL/ICPCK/ OCDSCK PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCK SIMC0 ST CMOS SPI serial clock SCL SIMC0 ST NMOS I 2C clock ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. PA3/SCS PA3 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCS SIMC0 ST CMOS SPI slave select PA4/INT PA4 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT INTEG ST — External interrupt PA7 PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PB0/KEY1~ PB3/KEY4 PB0~PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up KEY1~KEY4 TKM0C1 NSI — Touch key inputs PB4/KEY5~ PB7/KEY8 PB4~PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up KEY5~KEY8 TKM1C1 NSI — Touch key inputs PC0/KEY9~ PC3/KEY12 PC0~PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up KEY9~ KEY12 TKM2C1 NSI — Touch key inputs VDD VDD — PWR — Power supply * AVDD AVDD — PWR — Touch Key Circuit PWR and it should be double bonded to VDD* VSS VSS — PWR — Ground AVSS AVSS — PWR — Touch Key Circuit PWR and it should be double bonded to VSS Note: I/T: Input type; O/T : Output type OP: Optional by register selection; PWR: Power ST: Schmitt Trigger input; CMOS: CMOS output NMOS: NMOS output; NSI: Non-standard input *: VDD is the device power supply while AVDD is the touch key circuit power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the touch key circuit ground pin. The AVSS pin is bonded together internally with VSS.

Rev. 1.61 10 April 11, 2017 Rev. 1.61 11 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU BS83B16A-3/BS83B16A-4 Pin Name Function OPT I/T O/T Description PA0/SDI/ SDA/ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDI — ST — SPI data input SDA — ST NMOS I 2C data ICPDA — ST CMOS In-circuit programming address/data pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only. PA1/SDO PA1 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SDO SIMC0 — CMOS SPI data output PA2/SCK/ SCL/ICPCK/ OCDSCK PA2 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCK SIMC0 ST CMOS SPI serial clock SCL SIMC0 ST NMOS I 2C clock ICPCK — ST — In-circuit programming clock pin OCDSCK — ST — On-chip debug support clock pin, for EV chip only. PA3/SCS PA3 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up SCS SIMC0 ST CMOS SPI slave select PA4/INT PA4 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up INT INTEG ST — External interrupt PA7 PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up PB0/KEY1~ PB3/KEY4 PB0~PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up KEY1~KEY4 TKM0C1 NSI — Touch key inputs PB4/KEY5~ PB7/KEY8 PB4~PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up KEY5~KEY8 TKM1C1 NSI — Touch key inputs PC0/KEY9~ PC3/KEY12 PC0~PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up KEY9~ KEY12 TKM2C1 NSI — Touch key inputs PC4/KEY13~ PC7/KEY16 PC4~PC7 PCPU ST CMOS General purpose I/O. Register enabled pull-up KEY13~ KEY16 TKM3C1 NSI — Touch key inputs VDD VDD — PWR — Power supply * AVDD AVDD — PWR — Touch Key Circuit PWR and it should be double bonded to VDD* VSS VSS — PWR — Ground AVSS AVSS — PWR — Touch Key Circuit PWR and it should be double bonded to VSS Note: I/T: Input type; O/T : Output type OP: Optional by register selection; PWR: Power ST: Schmitt Trigger input; CMOS: CMOS output NMOS: NMOS output; NSI: Non-standard input *: VDD is the device power supply while AVDD is the touch key circuit power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the touch key circuit ground pin. The AVSS pin is bonded together internally with VSS.

Rev. 1.61 12 April 11, 2017 Rev. 1.61 13 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Absolute Maximum Ratings Note: T hese a re st ress ra tings onl y. St resses e xceeding t he ra nge spe cified und er "Absol ute Ma ximum Ratings" m ay c ause subst antial da mage t o t he de vice. Funct ional ope ration of t his de vice a t ot her conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VDD Operating Voltage (HIRC) (BS83B08A-3/BS83B12A-3/ BS83B16A-3) fSYS=8MHz 2.7 — 5.5 V fSYS=12MHz 2.7 — 5.5 V fSYS=16MHz 4.5 — 5.5 V Operating Voltage (HIRC) (BS83B08A-4/BS83B12A-4/ BS83B16A-4) f SYS=8MHz 2.2 — 5.5 V fSYS=12MHz 2.7 — 5.5 V fSYS=16MHz 4.5 — 5.5 V Operating Voltage (HIRC) (BS83B04A-4) — fSYS=8MHz 2.2 — 5.5 V IDD1 Operating Current (HIRC, fSYS=fH, fS=fSUB=fLIRC) (BS83B08A-3/BS83B12A-3/ BS83B16A-3/BS83B08A-4/ BS83B12A-4/BS83B16A-4) 3V No load, f H=8MHz, WDT enable — 1.2 1.8 mA 5V — 2.2 3.3 mA 3V No load, fH=12MHz, WDT enable — 1.6 2.4 mA 5V — 3.3 5.0 mA 5V No load, fH=16MHz, WDT enable — 4.0 6.0 mA Operating Current (HIRC, fSYS=fH, fS=fSUB=fLIRC) (BS83B04A-4) No load, fH=8MHz, WDT enable — 0.8 1.2 mA 5V — 1.6 2.4 mA IDD2 Operating Current (HIRC, fSYS=fL, fS=fSUB=fLIRC) 3V No load, fH=12MHz, fL=fH/2, WDT enable — 1.2 2.0 mA 5V — 2.2 3.3 mA 3V No load, fH=12MHz, fL=fH/4, WDT enable — 1.0 1.5 mA 5V — 1.8 2.7 mA 5V No load, fH=12MHz, fL=fH/8, WDT enable — 0.9 1.4 mA 3V — 1.6 2.4 mA 3V No load, fH =12MHz, fL=fH/16, WDT enable — 0.8 1.2 mA 5V — 1.5 2.3 mA 3V No load, fH=12MHz, fL=fH/32, WDT enable — 0.8 1.2 mA 5V — 1.5 2.3 mA 5V No load, fH=12MHz, fL=fH/64, WDT enable — 0.8 1.2 mA 3V — 1.5 2.3 mA

Rev. 1.61 12 April 11, 2017 Rev. 1.61 13 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions IDD3 Operating Current (LIRC, fSYS=fL=fLIRC, fS=fSUB=fLIRC) (BS83B08A-3/BS83B12A-3/ BS83B16A-3/BS83B08A-4/ BS83B12A-4/BS83B16A-4) No load, WDT enable, LVR enable — 50 100 μA 5V — 70 150 μA Operating Current (LIRC, f SYS=fL=fLIRC, fS=fSUB=fLIRC) (BS83B04A-4) No load, WDT enable, LVR enable — 10 20 μA 5V — 30 50 μA ISTB1 IDLE Mode Standby Current (HIRC, fSYS=fH, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=12MHz — 0.9 1.4 mA 5V — 1.4 2.1 mA ISTB2 IDLE Mode Standby Current (HIRC, fSYS=off, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=12MHz, LVR enable — 40 80 μA 5V — 50 100 μA ISTB3 IDLE Mode Standby Current (HIRC, f SYS=fL, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=12MHz/64 — 0.7 1.1 mA 5V — 1.4 2.1 mA ISTB4 IDLE Mode Standby Current (HIRC, fSYS=off, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=12MHz/64, LVR enable — 40 80 μA 5V — 50 100 μA ISTB5 IDLE Mode Standby Current (LIRC, fSYS=fL=fLIRC, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=32kHz — 1.9 4.0 μA 5V — 3.3 7.0 μA ISTB6 IDLE Mode Standby Current (LIRC, f SYS=off, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=32kHz, LVR enable — 40 80 μA 5V — 50 100 μA ISTB7 SLEEP Mode Standby Current (LIRC, fSYS=off, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=32kHz — 1.3 3.0 μA 5V — 2.4 5.0 μA ISTB8 SLEEP Mode Standby Current (BS83B04A-4 only) 3V No load, WDT enable — 1.5 3.0 μA 5V — 3.0 5.0 μA ISTB9 IDLE0 Mode Standby Current (BS83B04A-4 only) 3V No load, f SUB on — 3.0 5.0 μA 5V — 5.0 10.0 μA ISTB10 IDLE1 Mode Standby Current (BS83B04A-4 only) 3V No load, f SUB on, fSYS=fHIRC=8MHz — 360 500 μA 5V — 600 800 μA VIL Input Low Voltage for I/O Ports or Input Pins 5V — 0 — 1.5 V — 0 — 0.2VDD V VIH Input High Voltage for I/O Ports or Input Pins 5V — 3.5 — 5.0 V — 0.8V DD — VDD V VLVR Low Voltage Reset Voltage (BS83B08A-3/BS83B12A-3/ BS83B16A-3) — LVR enable, 2.55V -5% 2.55 +5% V Low Voltage Reset Voltage (BS83B04A-4/BS83B08A-4/ BS83B12A-4/BS83B16A-4) — LVR enable, 2.10V -5% 2.10 +5% V

Rev. 1.61 14 April 11, 2017 Rev. 1.61 15 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions ILVR Low Voltage Reset Current — LVR enable — 62 90 μA IOL Sink Current for I/O Port (BS83B08A-3/BS83B08A-4) 3V VOL=0.1VDD 4 8 — mA 5V 10 20 — mA Sink Current for I/O Port (BS83B04A-4/BS83B12A-3/ BS83B12A-4/BS83B16A-3/ BS83B16A-4) VOL=0.1VDD 8 16 — mA 5V 16 32 — mA IOH Source Current for I/O Port (BS83B08A-3/BS83B08A-4) 3V VOH=0.9VDD -2 -4 — mA 5V -5 -10 — mA Source Current for I/O Port (BS83B12A-3/BS83B12A-4/ BS83B16A-3/BS83B16A-4) VOH=0.9VDD -3.75 -7.5 — mA 5V -7.5 -15 — mA RPH Pull-high Resistance for I/O Ports 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ A.C. Characteristics Ta=25°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock (HIRC) 3V/5V Ta=25°C -2% 8 +2% MHz -2% 12 +2% MHz 5V Ta=25°C -2% 16 +2% MHz fTIMER Timer Input Pin Frequency 2.7V~5.5V — — 8 MHz 2.7V~5.5V — — 12 MHz 4.5V~5.5V — — 16 MHz fLIRC System Clock (32kHz) 5V Ta=25°C -10% 32 +10% kHz tINT Interrupt Pulse Width — — 1 — — μs tLVR Low Voltage Width to Reset — — 60 120 240 μs tEERD EEPROM Read Time — — 1 2 4 tSYS tEEWR EEPROM Write Time — — 1 2 4 ms tRSTD System reset delay time (POR reset, LVR hardware reset, LVR software reset, WDT software reset, reset control register software reset) — — 25 50 100 ms System reset delay time (WDT time-out hardware cold reset) — — 8.3 16.7 33.3 ms

Rev. 1.61 14 April 11, 2017 Rev. 1.61 15 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions tSST System start-up timer period (wake-up from halt, fSYS off at halt) — fSYS=fHIRC~fHIRC/64 16 — — tHIRC — fSYS=fLIRC 2 — — tLIRC System start-up timer period (slow mode ↔ normal mode) — fHIRC off→on (HTO=1) 16 — — tHIRC System start-up timer period (wake-up from halt, fSYS on at halt state) — fSYS=fHIRC~fHIRC/64 2 — — tHIRC — fSYS=fLIRC 2 — — tLIRC System start-up timer period (WDT time-out hardware cold reset) — — 0 — — tH fI2C I2C standard mode (100kHz) fSYS frequency — No clock debounce 2 — — MHz — 2 system clock debounce 4 — — MHz — 4 system clock debounce 8 — — MHz I 2C fast mode (400kHz) fSYS frequency — No clock debounce 5 — — MHz — 2 system clock debounce 10 — — MHz — 4 system clock debounce 20 — — MHz Note: 1. tSYS=1/fSYS 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. 3. 16MHz can not be used when the supply voltage is below 3.3V. Power-on Reset Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tPOR RRPOR VPOR Time

Rev. 1.61 16 April 11, 2017 Rev. 1.61 17 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU System Architecture A key factor in the high-performan ce features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantag e of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. An 8-bi t wi de AL U i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal regis ters are implemented in the D ata M emory and can be directly or indirectly addressed. The simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum relia bility and flexibility . This makes these devices suitable for low- cost, high-volume production for controller applications. Clocking and Pipelining The mai n system clock, deri ved from eit her a high or low speed oscilla tor is subdivide d into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way , one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. Fetch Inst. (PC) (System Clock) fSYS Phase Clock T1 Phase Clock T2 Phase Clock T3 Phase Clock T4 Program Counter PC PC+1 PC+2 Pipelining Execute Inst. (PC-1) Fetch Inst. (PC+1) Execute Inst. (PC) Fetch Inst. (PC+2) Execute Inst. (PC+1) System Clock and Pipelining

Rev. 1.61 16 April 11, 2017 Rev. 1.61 17 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle t o first obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Fetch Inst. 11 MOV A,[12H]

2 CALL DELAY

3 CPL [12H]

4 : 5 :

6 DELAY: NOP

Execute Inst. 1 Fetch Inst. 2 Execute Inst. 2 Fetch Inst. 3 Flush Pipeline Fetch Inst. 6 Execute Inst. 6 Fetch Inst. 7 Instruction Fetching Program Counter During pro gram e xecution, t he Progr am Co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. It is automatically incremented by one each time an instruction is e xecuted e xcept f or i nstructions, su ch a s “ JMP” o r “ CALL” t hat d emand a j ump t o a non-consecutive Pr ogram Me mory a ddress. On ly t he l ower 8 b its, k nown a s t he Pr ogram C ounter Low Register, are directly addressable by the application program. When executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the Program Counter . For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program CounterHigh Byte PCL Register BS83B04A-4 PC10~PC8 PCL7~PCL0BS83B08A-3/BS83B08A-4 PC10~PC8 BS83B12A-3/BS83B12A-4 PC10~PC8 BS83B16A-3/BS83B16A-4 PC10~PC8 The lower byte of the Program Counter , known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register . By transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch.

Rev. 1.61 18 April 11, 2017 Rev. 1.61 19 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer , and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily . However , when the stack is full, a CALL subroutine instruction can still be exec uted whic h wi ll result in a st ack overflow . Prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. If the stack is overflow , the first Program Counter save in the stack will be lost. Stack Pointer Stack Level 2 Stack Level 1 Stack Level 3 Stack Level 4 Program Memory Program Counter Bottom of Stack Top of Stack Arithmetic and Logic Unit – ALU The arith metic-logic unit or ALU is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. Connected to the main micro controller data bus, the ALU receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register . As these ALU calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:

Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
Increment and Decrement INCA, INC, DECA, DEC
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Rev. 1.61 18 April 11, 2017 Rev. 1.61 19 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. By using the appropriate programming tools, these Flash device s of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. Structure The Progra m Me mory ha s a c apacity of 2K×16 bi ts. T he Progra m Me mory i s a ddressed by t he Program Counter and also contains data, table information and interrupt entries. T able data, which can be setup in any location within the Program Memory , is addressed by a separate table pointer register. Special Vectors Within the Program Memory , certai n locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. /G30/G30/G30/G34/G48 /G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G56/G65 /G63/G74 /G6F/G72 /G73 /G31/G36/G62/G69 /G74/G73 /G30/G37 /G46/G46 /G48 /G30/G30/G30/G30/G48 /G52/G65 /G73/G65 /G74 /G30/G30/G31/G38/G48 Program Memory Structure Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. T o use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register , TBLP and TBHP . These registers define the total address of the look-up table. After setting up the table pointer , the table data can be retrieved from the Program Memory using the “T ABRDC [m]” or “T ABRDL [m]” instructions, respectively . When the instruction is executed, the low er order table byte from the Program Memory will be transferred to the user defined Data Memory regis ter [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register . Any unused bits in this transferred higher order byte will be read as “0”.

Rev. 1.61 20 April 11, 2017 Rev. 1.61 21 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU The accompanying diagram illustrates the addressing data flow of the look-up table. Last Page or TBHP Register Address TBLP Register Data 16 bits Program Memory Register TBLH User Selected Register High Byte Low Byte Instruction Table Location Bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: b10~b0: Table location bits @7~@0: T able pointer (TBLP) bits @10~@8: T able pointer (TBHP) bits Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “700H” which refers to the start address of the last page within the 2K words Program Memory of the device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “706H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRDC [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “T ABRDC [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and Interrupt S ervice Routine us e table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

Rev. 1.61 20 April 11, 2017 Rev. 1.61 21 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a tabrdc tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “706H” transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdc tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address “705H” transferred to tempreg2 and TBLH in this ; example the data “1AH” is transferred to tempreg1 and data “0FH” to ; register tempreg2 org 700h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades a nd m odifications t o t heir p rograms o n t he sa me d evice. As a n a dditional c onvenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to W riter Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins Function ICPDA PA0 Serial Address and data -- read/write ICPCK PA2 Programming Serial Clock VDD VDD Power Supply (5.0V) VSS VSS Ground During the programming process, the user must there take care to ensure that no other outputs are connected to these two pins. The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire inte rface. Dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. T wo a dditional l ines a re re quired for t he powe r suppl y. T he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.

Rev. 1.61 22 April 11, 2017 Rev. 1.61 23 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU During the programming process the P A0 and P A2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. * * Writer_VDD ICPDA ICPCK Writer_VSS To other Circuit VDD PA0 PA2 VSS Writer Connector Signals MCU Programming Pins Note: * may be resistor or capacito r. The resistance of * must be great er than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip which is used to emulate the device. Each EV chip device also provides an “On- Chip Debug” function to debug the corresponding MCU device during the development process. The E V c hip a nd t he a ctual MCU de vice a re a lmost func tionally c ompatible e xcept for t he “ On- Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT -IDE development tools. The OCDSDA p in i s t he OC DS Da ta/Address i nput/output p in wh ile t he OC DSCK p in i s t he OC DS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pi ns in the actual MCU de vice will ha ve no ef fect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP . For a more detailed OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground

Rev. 1.61 22 April 11, 2017 Rev. 1.61 23 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. He re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. Ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory , which is reserved for general purpose use. All locatio ns within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks for the device s. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the dif ferent Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Device Capacity Bank 0 Bank 1 BS83B04A-4 128×8 60H~FFH E0H~FFH BS83B08A-3/BS83B08A-4 160×8 60H~FFH — BS83B12A-3/BS83B12A-4 288×8 60H~FFH 80H~FFH BS83B16A-3/BS83B16A-4 288×8 60H~FFH 80H~FFH General Purpose Data Memory Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation.

Rev. 1.61 24 April 11, 2017 Rev. 1.61 25 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 00H IAR0 01H MP0 02H IAR1 03H MP1 04H 05H ACC 06H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 19H 18H SFS 1BH 1AH 1DH 1CH 1FH LVRC13H 14H 15H 16H 17H 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 27H EEA I2CC1 I2CD I2CA I2CTOC 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H EED 1EH Bank 0,1 Bank 0 Bank 1 55H 56H TKM016DL TKM016DH 30H 31H 32H 38H 3CH 33H 34H 35H 36H 37H TKM0ROH TKM0C0 TKM0C1 3BH 39H 3AH PAWU PAC PAPU 3DH 3FH 3EH BP CTRL INTEG INTC0 INTC1 PA 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH SMOD TBC WDTC TMR TMRC TK16DH TKC1 TKTMR TKC0 TK16DL TKM0ROL I2CC0 EEC : Unused, read as "00" Special Purpose Data Memory – BS83B04A-4

Rev. 1.61 24 April 11, 2017 Rev. 1.61 25 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 00H IAR0 01H MP0 02H IAR1 03H MP1 04H 05H ACC 06H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 19H 18H 1BH 1AH 1DH 1CH 1FH LVRC SIMC0 13H 14H 15H 16H 17H 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 27H TKM1ROH TKM1C0 TKM1C1 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 1EH Bank 0,1 Bank 0 Bank 1 55H 56H TKM016DL TKM016DH 30H 31H 32H 38H 3CH 33H 34H 35H 36H 37H TKM0ROH TKM0C0 TKM0C1 3BH 39H 3AH PAWU PAC PAPU 3DH 3FH 3EH BP CTRL INTEG INTC0 INTC1 PA PB 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH SMOD TBC WDTC TMR TMRC TK16DH TKC1 TKTMR TKC0 TK16DL TKM0ROL TKM1ROL EEA EED PBC PBPU I2CTOC SIMC1 SIMD SIMC2/SIMA EEC TKM116DL TKM116DH : Unused, read as "00" Special Purpose Data Memory – BS83B08A-3/BS83B08A-4

Rev. 1.61 26 April 11, 2017 Rev. 1.61 27 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 00H IAR0 01H MP0 02H IAR1 03H MP1 04H 05H ACC 06H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 19H 18H 1BH 1AH 1DH 1CH 1FH LVRC SIMC0 13H 14H 15H 16H 17H 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 27H TKM1ROH TKM1C0 TKM1C1 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 1EH Bank 0,1 Bank 0 Bank 1 55H 56H TKM016DL TKM016DH 30H 31H 32H 38H 3CH 33H 34H 35H 36H 37H TKM0ROH TKM0C0 TKM0C1 3BH 39H 3AH PAWU PAC PAPU 3DH 3FH 3EH BP CTRL INTEG INTC0 INTC1 PA PB 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH SMOD TBC WDTC TMR TMRC TK16DH TKC1 TKTMR TKC0 TK16DL TKM0ROL TKM1ROL EEA EED PBC PBPU I2CTOC SIMC1 SIMD SIMC2/SIMA PC PCC PCPU EEC TKM116DL TKM116DH : Unused, read as "00" TKM2ROH TKM2C0 TKM2C1 TKM2ROL TKM216DL TKM216DH TKM3ROH TKM3C0 TKM3C1 TKM3ROL TKM316DL TKM316DH Special Purpose Data Memory – BS83B16A-3/BS83B16A-4 /G36/G30 /G48 /G46/G46 /G48 /G42/G61 /G6E/G6B /G30 /G36/G30 /G48 /G46/G46 /G48 /G46/G46 /G48 /G38/G30 /G48 /G42/G61 /G6E/G6B /G30 /G42/G61 /G6E/G6B /G31 /G42/G53 /G38/G33/G42 /G30/G38 /G41/G2D /G33/G2F /G42/G53 /G38/G33 /G42/G30 /G38/G41 /G2D/G34 /G42/G53 /G38/G33/G42 /G31/G32 /G41/G2D /G33/G2F /G42/G53 /G38/G33 /G42/G31 /G32/G41 /G2D/G34 /G2F /G42/G53 /G38/G33/G42 /G31/G36 /G41/G2D /G33/G2F /G42/G53 /G38/G33 /G42/G31 /G36/G41 /G2D/G34 /G36/G30 /G48 /G46/G46 /G48 /G46/G46 /G48 /G45/G30 /G48 /G42/G61 /G6E/G6B /G30 /G42/G61 /G6E/G6B /G31 /G42/G53 /G38/G33/G42 /G30/G34 /G41/G2D /G34 General Purpose Data Memory

Rev. 1.61 28 April 11, 2017 Rev. 1.61 29 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Memory Pointers – MP0, MP1 Two Me mory Po inters, k nown a s MP0 a nd MP1 a re p rovided. T hese Me mory Po inters a re physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the releva nt Indirect Addressing Registers is carried out, the actual address that the microcontroller is di rected to is the address specified by the relat ed Memory Pointer . MP0, together with Indirect Addressing Register , IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according t o BP register. Direct Ad dressing c an only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 ´code´ org00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Bank Pointer – BP For this device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the required Data Memory area is achieved using the Bank Pointer . Bit 0 of the Bank Pointer is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WD T time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaf fected. It should be noted that the Special Function Data Memory is not af fected by the bank selection, which means that the Special Function Regi sters ca n be ac cessed from wi thin any bank. Di rectly addressi ng the Da ta Me mory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer . Accessing data from Bank1 must be implemented using Indirect Addressing.

Rev. 1.61 28 April 11, 2017 Rev. 1.61 29 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU BP Register Bit 7 6 5 4 3 2 1 0 Bit 7~1 Unimplemented, read as "0" Bit 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The A ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. W ithout the Accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he Da ta Me mory resulting i n highe r program ming and t iming overheads. Da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he Ac cumulator; for e xample, wh en t ransferring da ta be tween one user-defined register and another , it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory . By manipulating this register , direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to cont rol operation of the look-up table which is stored i n t he Progra m Me mory. T BLP a nd T BHP a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.

Rev. 1.61 30 April 11, 2017 Rev. 1.61 31 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (T O). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exceptio n of the T O and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the T O or PDF flag. In addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. The T O flag can be af fected only by a system power -up, a WDT time-out or by executing the “CLR WDT” or “HAL T” instruction. The PDF flag is af fected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also af fected by a rotate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by a system power -up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction.
TO is cle ared by a system power -up or executing the “CLR WDT” or “HAL T” instruction. TO is set by a WDT time-out. In additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

Rev. 1.61 30 April 11, 2017 Rev. 1.61 31 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5 TO: W atchdog T ime-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction.

Rev. 1.61 32 April 11, 2017 Rev. 1.61 33 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU EEPROM Data Memory One of the s pecial features in the device is its internal EEP ROM D ata M emory. EEP ROM, w hich stands for Electrically Erasable Programmable Read Only Memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. By incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is up to 64×8 bits. Unlike the Program Memory and RAM Data Memory , the EEPROM Data Memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . Read and W rite operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device Capacity Address BS83B04A-4 32×8 00H~1FH BS83B08A-3/BS83B08A-4 64×8 00H~3FH BS83B12A-3/BS83B12A-4 64×8 00H~3FH BS83B16A-3/BS83B16A-4 64×8 00H~3FH EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory . These are the address register , EEA, the data register , EED and a single control register , EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same way as any other Special Functi on Regist er. The EEC register however , be ing located in Bank1, cannot be di rectly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register , IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register , BP, set to the value, 01H, before any operations on the EEC register are executed. Device Register Name Bit 7 6 5 4 3 2 1 0 BS83B04A-4 EEA — — — D4 D3 D2 D1 D0 Others EEA — — D5 D4 D3 D2 D1 D0 All devices EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Control Registers List EEA Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name — — — D4 D3 D2 D1 D0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as "0" Bit 4~0 Data EEPROM address Data EEPROM address bit 4~bit 0

Rev. 1.61 32 April 11, 2017 Rev. 1.61 33 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU EEA Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W “×” unknown Bit 7~6 Unimplemented, read as "0" Bit 5~0 Data EEPROM address Data EEPROM address bit 5~bit 0 EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Data EEPROM data Data EEPROM data bit 7~bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM W rite Enable 0: Disable 1: Enable This is the D ata EEP ROM W rite Enable Bit w hich mus t be s et high before D ata EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM W rite Control 0: W rite cycle has finished 1: Activate a write cycle This i s t he Da ta E EPROM W rite C ontrol B it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no ef fect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero w ill inhibit D ata EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set hi gh by the applic ation program will activ ate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no ef fect if the RDEN has not first been set high.

Rev. 1.61 34 April 11, 2017 Rev. 1.61 35 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The WR and RD can not be set to “1” at the same time. Reading Data from the EEPROM To read data from the EEP ROM, the read enable bit, RDEN , in the EEC register must firs t be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register . If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle term inates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register . The data will remain in the EED register until another read or write operation i s e xecuted. T he a pplication pr ogram c an po ll t he RD bi t t o de termine whe n t he da ta i s valid for reading. Writing Data to the EEPROM To wr ite da ta t o t he E EPROM, t he wr ite e nable bi t, W REN, i n t he E EC re gister m ust first be se t high to enable the w rite function. The EEP ROM addres s of the data to be w ritten mus t then be placed in the EEA register and the data placed in the EED register . If the WR bit in the EEC register is now set high, an internal write cycle will then be initiated. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has fini shed c an be i mplemented e ither by pol ling t he W R bi t i n t he E EC re gister or by usi ng t he EEPROM i nterrupt. W hen t he wr ite c ycle t erminates, t he W R b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on t he W rite E nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. Also at power -on the Bank Pointer , BP , will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the W rite Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register . When an EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM is enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is serviced, t he E EPROM i nterrupt fla g will a utomatically reset. Mo re d etails c an b e o btained i n t he Interrupt section.

Rev. 1.61 34 April 11, 2017 Rev. 1.61 35 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the W rite Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly . The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Programming Examples Reading Data from the EEPROM – Polling Method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A M O V A , 0 4 0 H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register M O V A , 0 1 H ; setup Bank Pointer MOV BP, A S E T I A R 1 . 1 ; set RDEN bit, enable read operations S E T I A R 1 . 0 ; start Read Cycle - set RD bit BACK: S Z I A R 1 . 0 ; check for read cycle end JMP BACK C L R I A R 1 ; disable EEPROM write CLR BP MOV A, EED ; move read data to register MOV READ_DATA, A Writing Data to the EEPROM – Polling Method CLR EMI MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, EEPROM_DATA ; user defined data MOV EED, A M O V A , 0 4 0 H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register M O V A , 0 1 H ; setup Bank Pointer MOV BP, A S E T I A R 1 . 3 ; set WREN bit, enable write operations S E T I A R 1 . 2 ; start Write Cycle - set WR bit SET EMI BACK: S Z I A R 1 . 2 ; check for write cycle end JMP BACK C L R I A R 1 ; disable EEPROM write CLR BP

Rev. 1.61 36 April 11, 2017 Rev. 1.61 37 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Oscillators Various oscillator options of fer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In additio n to being the source of the main system clock the oscillators also provide clock sources for the Watchdog T imer and T ime Base Interrupts. Fully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capabilit y of dynamically switching between fast and slow system clock, the device has the flexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. Device Type Name Freq. BS83B04A-4 Internal High Speed RC HIRC 8MHz Others Internal High Speed RC HIRC 8/12/16MHz All devices Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a low spee d oscillator. The high speed oscillator is the internal 8MHz RC oscillator for the BS83B04A-4 and 8MHz, 12MHz, 16MHz RC oscilla tor for the others. The low speed oscillator is the internal 32kHz (LIRC) oscillator . Selecting whether the low or high speed oscillator is used as the system oscillator is implem ented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actua l source clock used for the high speed and the low speed oscillators is chosen via registers. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bit s i n t he SMOD regist er. Note t hat t wo osci llator sel ections m ust be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator.

Rev. 1.61 36 April 11, 2017 Rev. 1.61 37 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G48/G49 /G52/G43 /G4C/G49 /G52/G43 /G48/G69 /G67/G68 /G20/G53 /G70/G65/G65/G64 /G20/G4F /G73/G63 /G69/G6C/G6C/G61 /G74/G6F /G72 /G4C/G6F /G77/G20 /G53/G70 /G65/G65/G64/G20 /G4F/G73 /G63/G69 /G6C/G6C /G61/G74 /G6F/G72 /G66 /G48 /G66 /G48 /G2F/G36 /G34 /G66 /G48 /G2F/G33 /G32 /G66 /G48 /G2F/G31 /G36 /G66 /G48 /G2F/G38 /G66 /G48 /G2F/G34 /G66 /G48 /G2F/G32 /G36/G2D /G73/G74 /G61/G67/G65/G20 /G50 /G72/G65 /G73/G63/G61 /G6C/G65 /G72 /G66 /G53/G55 /G42 /G66 /G53/G59/G53 /G48/G4C /G43/G4C /G4B/G2C /G20 /G43/G4B /G53/G32 /G7E/G43 /G4B/G53 /G30/G20 /G62/G69 /G74/G73 System Clock Configurations Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The i nternal RC osc illator ha s a powe r on de fault fre quency of 8MHz but c an be se lected t o be either 8MHz, 12MHz or 16MHz using the HIRCS1 and HIRCS0 bits in the CTRL register for the devices except BS83B04A-4. Device trimming during the manufacturi ng process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is the low frequency oscillator . It is a fully integrated RC osc illator wi th a t ypical fre quency of 32kHz a t 5V , re quiring no e xternal c omponents for i ts implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. After power on this LIRC oscillator will be permanently enabled; there is no provision to disable the oscillator using.

Rev. 1.61 38 April 11, 2017 Rev. 1.61 39 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Operating Modes and System Clocks Present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conflicting requirements that are especially true i n ba ttery powe red por table a pplications. T he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The main system clock, can come from either a high frequency , fH, or low frequency , fSUB, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register . Both the high and low speed system clocks are sourced from internal RC oscillators. /G54/G53 /G54/G69 /G6D/G65 /G20/G42 /G61/G73 /G65 /G57/G44 /G54 /G48/G49 /G52/G43 /G4C/G49 /G52/G43 /G48/G69 /G67/G68 /G20/G53 /G70/G65/G65/G64 /G20/G4F /G73/G63 /G69/G6C/G6C/G61 /G74/G6F /G72 /G4C/G6F /G77/G20 /G53/G70 /G65/G65/G64/G20 /G4F/G73 /G63/G69 /G6C/G6C /G61/G74 /G6F/G72 /G66 /G48 /G66 /G48 /G2F/G36 /G34 /G66 /G48 /G2F/G33 /G32 /G66 /G48 /G2F/G31 /G36 /G66 /G48 /G2F/G38 /G66 /G48 /G2F/G34 /G66 /G48 /G2F/G32 /G36/G2D /G73/G74 /G61/G67/G65/G20 /G50/G72 /G65 /G73/G63/G61 /G6C/G65 /G72 /G66 /G53/G55 /G42 /G66 /G53/G59/G53 /G48/G4C /G43/G4C /G4B/G2C /G20 /G43/G4B /G53/G32 /G7E/G43 /G4B/G53 /G30/G20 /G62/G69 /G74/G73 /G66 /G53/G59/G53 /G66 /G54/G50 /G66 /G53 System Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. System Operation Modes There a re five d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. There are two modes all owing normal operati on of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP , IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power.

Rev. 1.61 38 April 11, 2017 Rev. 1.61 39 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Operating Mode

Description

NORMAL mode On fH~fH/64 On On SLOW mode On fSUB On On ILDE0 mode Off Off On On IDLE1 mode Off On On On SLEEP mode Off Off On On NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . This mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD regis ter. A lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. T he c lock so urce u sed wi ll b e f rom fSUB. R unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP Mode The SLEEP Mode is entered when an HAL T instruction is executed and when the IDLEN bit in the SMOD register is low . In the SLEEP mode the CPU will be stopped. However the fSUB clocks will continue to run the W atchdog T imer will continue to operate. IDLE0 Mode The IDLE0 Mode is entered when a HAL T instruction is executed and when the IDLEN bit in the SMOD regi ster i s high and t he FSYSON bit i n t he CTRL register i s l ow. In t he IDLE 0 Mode t he system oscillator will be stop and will therefore be inhibited from driving the CPU. IDLE1 Mode The IDLE1 Mode is entered when a HAL T instruction is executed and when the IDLEN bit in the SMOD registe r is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator.

Rev. 1.61 40 April 11, 2017 Rev. 1.61 41 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Control Register The SMOD register is used to control the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7~5 CKS2~CKS0: The system clock selection when HLCLK is “0” 000: fSUB (fLIRC) 001: fSUB (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as “0” Bit 3 LTO: LIRC System OSC SST ready flag 0: Not ready 1: Ready This is the low speed system oscillator SST ready flag which indicate s when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will change to a high level after 1~2 cycles. Bit 2 HTO: HIRC System OSC SST ready flag 0: Not ready 1: Ready This is the high speed system oscill ator SST ready flag which indicates when the high speed system oscillator is stable after a wake-up has occurred. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the h igh sp eed sy stem o scillator i s stable. Therefore t his flag wi ll a lways b e r ead a s “1” by the application program after device power -on. The flag will be low when in the SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used. Bit 1 IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HAL T instruction is executed. If this bit is high, when a HAL T instruction is executed the device wi ll e nter t he IDLE Mo de. I n t he I DLE1 Mo de t he C PU wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HAL T instruction is executed. Bit 0 HLCLK: System Clock Selection 0: fH/2~fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power.

Rev. 1.61 40 April 11, 2017 Rev. 1.61 41 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU CTRL Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W “×” unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6~3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low V oltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1 LRF: LVRC Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the L VRC register contains any non defined L VR voltage register values. This in ef fect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application pr ogram. Not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.

Rev. 1.61 42 April 11, 2017 Rev. 1.61 43 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU CTRL Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — × 0 0 “×” unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 Unimplemented, read as "0" Bit 5~4 HIRCS1~HIRCS0: High frequency clock select 00: 8MHz 01: 16MHz 10: 12MHz 11: 8MHz Bit 3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low V oltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1 LRF: LVRC Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the L VRC register contains any non defined L VR voltage register values. This in ef fect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application pr ogram. Not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.

Rev. 1.61 42 April 11, 2017 Rev. 1.61 43 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Operating Mode Switching The devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. In this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HAL T instruction. When a HAL T instructio n is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condit ion of the IDL EN bit in the SMOD regi ster and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power . When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running. The accompanying flowchart shows what happens when the device moves between the various operating modes. NORMAL fSYS=fH~fH/64 fH on CPU run fSYS on fSUB on WDT on SLOW fSYS=fL fL on CPU run fSYS on fSUB on fH off fS on WDT on IDLE0 HALT instruction executed CPU stop IDLEN=1 FSYSON=0 fSYS off fSUB on fS on WDT on IDLE1 HALT instruction executed CPU stop IDLEN=1 FSYSON=1 fSYS on fSUB on fS on WDT on SLEEP HALT instruction executed fSYS off CPU stop IDLEN=0 fSUB on fS on WDT on

Rev. 1.61 44 April 11, 2017 Rev. 1.61 45 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU NORMAL Mode to SLOW Mode Switching When r unning i n t he NOR MAL Mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he SL OW Mode by se tting t he HLCLK bit to “0” and setting the CKS2~CKS0 bits to “000” or “001” in the SMOD register .This will then use the low speed system oscillator which will consume less power . Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses LIRC low speed system oscillator . T o switch back to the NORMAL Mode, w here the high s peed s ystem os cillator is us ed, the H LCLK bit s hould be s et to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “01 1”, “100”, “101”, “1 10” or “1 11”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO b it i s c hecked. T he a mount o f t ime r equired f or h igh sp eed sy stem o scillator st abilization depends upon which high speed system oscillator type is used. Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the “HAL T” instruction in the application program with the IDLEN bit in SMOD register equal to “0”. When this instruction is executed under the conditions described above, the following will occur:

The system clock and T ime Base clock will be stopped and the application program will stop at the “HALT” instruction, but the fSUB clock will be on.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting.
The I/O ports will maintain their present conditions.
In the status register , the Power Down flag, PDF , will be set and the W atchdog time-out flag, T O, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HAL T” instruction i n t he a pplication p rogram wi th t he I DLEN b it i n SMOD r egister e qual t o “ 1” a nd t he FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur:
The system clock will be stopped and the application program will stop at the “HAL T” instruction, but the T ime Base and the low frequency fSUB clock will be on.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting.
The I/O ports will maintain their present conditions.
In the status register , the Power Down flag, PDF , will be set and the W atchdog time-out flag, T O, will be cleared.

Rev. 1.61 44 April 11, 2017 Rev. 1.61 45 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HAL T” instruction i n t he a pplication p rogram wi th t he I DLEN b it i n SMOD r egister e qual t o “ 1” a nd t he FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur:

The system clock and the low frequency fSUB will be on and the applic ation program will stop at the “HALT” instruction.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting.
The I/O ports will maintain their present conditions.
In the status register , the Power Down flag, PDF , will be set and the W atchdog time-out flag, T O, will be cleared. /G53/G4C /G4F/G57 /G20/G4D /G6F/G64/G65 /G53/G4C /G45 /G45/G50/G20 /G4D /G6F/G64/G65 /G49/G44 /G45 /G4C/G30/G20 /G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G31/G20 /G4D /G6F/G64/G65 /G4E/G4F /G52/G4D /G41/G4C /G20/G4D /G6F/G64 /G65 /G43/G4B /G53/G32 /G20/G7E /G20/G43 /G4B/G53/G30 /G20/G3D /G20 /G30/G30/G78 /G42/G20 /G26 /G48/G4C /G43/G4C /G4B/G20 /G3D/G20 /G30 /G57/G44 /G54/G20 /G69/G73 /G20/G6F /G6E /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G30 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74 /G72/G75 /G63/G74 /G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53 /G4F/G4E /G3D/G30 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74 /G72/G75 /G63/G74 /G69/G6F /G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53/G4F /G4E/G3D /G31 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74 /G72/G75 /G63/G74 /G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74 /G65/G64

Rev. 1.61 46 April 11, 2017 Rev. 1.61 47 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G4E/G4F /G52/G4D /G41/G4C /G20/G4D /G6F/G64/G65 /G53/G4C /G45 /G45/G50/G20 /G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G30/G20 /G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G31/G20 /G4D /G6F/G64/G65 /G53/G4C /G4F/G57 /G20/G4D /G6F/G64 /G65 /G43/G4B /G53/G32 /G7E/G43 /G4B/G53/G30 /GB9 /G30/G30/G30/G42 /G2C/G20 /G30/G30/G31/G42 /G20/G61 /G73/G20 /G48/G4C /G43/G4C /G4B/G3D /G30 /G6F/G72 /G20/G48 /G4C/G43 /G4C/G4B /G3D/G31 /G57/G44 /G54/G20 /G69/G73 /G20/G6F /G6E /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G30 /G48/G41 /G4C/G54 /G20/G69 /G6E /G73/G74 /G72/G75 /G63/G74 /G69/G6F /G6E /G20/G69 /G73/G20 /G65/G78 /G65/G63 /G75/G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53 /G4F/G4E /G3D/G30 /G48/G41 /G4C/G54 /G20/G69 /G6E /G73/G74 /G72/G75 /G63/G74 /G69/G6F /G6E /G20/G69 /G73/G20 /G65/G78 /G65/G63 /G75/G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53/G4F /G4E/G3D /G31 /G48/G41 /G4C/G54 /G20/G69 /G6E /G73/G74 /G72/G75 /G63/G74 /G69/G6F /G6E /G20/G69 /G73/G20 /G65/G78 /G65/G63 /G75/G74 /G65/G64 Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have dif ferent package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. T hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps.

Rev. 1.61 46 April 11, 2017 Rev. 1.61 47 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:

An external falling edge on Port A
A system interrupt
A WDT overflow If the device is woken up by a WDT overflow , a W atchdog T imer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the T O and PDF flags. The PDF flag is cleared by a system power-up or executing the clear W atchdog T imer instructions and is set when executing the “HAL T” instruction. The T O flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the P AWU register to permit a negative transition on the pin to wake-up t he syste m. When a Port A pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he “ HALT” i nstruction. I f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HAL T” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag i s se t hi gh be fore e ntering t he SLE EP or IDL E Mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. System Oscillator Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) HIRC 15~16 HIRC cycles 1~2 HIRC cycles LIRC 1~2 LIRC cycles 1~2 LIRC cycles Wake-Up Time Programming Considerations The high speed and low speed oscillators both use the same SST counter . For example, if the system is woken up from the SLEEP Mode the HIRC oscillator needs to start-up from an off state. If the device is woken up from the SLEEP Mode to the NO RMAL Mode, the high speed system oscillator needs an SST period. The device will execute the first instruction after HTO is high.

Rev. 1.61 48 April 11, 2017 Rev. 1.61 49 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Watchdog Timer The W atchdog T imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The W atchdog T imer clock source is provided by the internal fSUB clock which is in turn supplied by the LIRC oscillator . The W atchdog T imer source clock is then subdivided by a ratio of 28 t o 218 t o gi ve l onger t imeouts, t he a ctual va lue be ing c hosen usi ng t he W S2~WS0 bi ts i n t he W DTC register. The LIRC internal oscillato r has an approximate period of 32kHz at a supply voltage of 5V . However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register , WDTC, controls the required timeout period as well as the enable operation. The WDTC register is initiated to 0101001 1B at any res et but keeps unchanged at the WD T time-out occurrence in a power down state. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4 ~ WE0: WDT function software control 10101B: Enabled 01010B: Enabled (Default) Other v alues: R eset MC U ( Reset wi ll b e a ctive a fter 2 ~3 L IRC c lock f or d ebounce t ime.) If the MCU reset caused by the WE [4:0] in WDTC software reset, the WRF flag of CTRL register will be set. Bit 2~0 WS2~WS0: WDT T ime-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three bits determine the divis ion ratio of the Watchdog T imer s ource clock, which in turn determines the timeout period.

Rev. 1.61 48 April 11, 2017 Rev. 1.61 49 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU CTRL Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W “×” unknown Bit 7 FSYSON: fSYS Control IDLE Mode Describe elsewhere Bit 6~3 Unimplemented, read as “0” Bit 2 LVRF: LVR function reset flag Describe elsewhere Bit 1 LRF: LVR Control register software reset flag Describe elsewhere Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application pr ogram. Not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. CTRL Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — × 0 0 “×” unknown Bit 7 FSYSON: fSYS Control IDLE Mode Describe elsewhere Bit 6 Unimplemented, read as “0” Bit 5~4 HIRCS1~HIRCS0: High frequency clock select Describe elsewhere Bit 3 Unimplemented, read as “0” Bit 2 LVRF: LVR function reset flag Describe elsewhere Bit 1 LRF: LVR Control register software reset flag Describe elsewhere Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application pr ogram. Not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.

Rev. 1.61 50 April 11, 2017 Rev. 1.61 51 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Watchdog Timer Operation In these devices the W atchdog T imer supplied by the fSUB oscillator and is therefore always on. The W atchdog T imer ope rates by provi ding a de vice re set whe n i ts t imer ove rflows. T his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he Watchdog T imer before it overflows to prevent the W atchdog T imer from executing a reset. This is done using the cle ar watchdog instructions. If the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear WDT instruction will not be executed in the correct manne r, in which case the W atchdog T imer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to enable the WDT function. When the WE4~WE0 bits value is equal to 01010B or 10101B, the WDT function is enabled. However , if the WE4~WE0 bits are changed to any other values except 01010B and 10101B, which is caused by the environmental noise, it will reset the microcontroller after 2~3 LIRC clock cycles. Under norm al progra m ope ration, a W atchdog T imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit T O. However , if the system is in the SLEEP or IDLE Mode, when a W atchdog T imer time-out occurs, the T O bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the W atchdog T imer. The first is a WDT reset, which means a certain value is written into the WE4~WE0 bit filed except 01010B a nd 10101B, the second i s usi ng t he W atchdog T imer soft ware c lear i nstructions a nd t he third is via a HALT instruction. There is only one method of using software instruction to clear the W atchdog T imer. That is to use the single “CLR WDT” instruction to clear the WDT . The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. /G37/G2D /G73/G74 /G61 /G67/G65/G20 /G44/G69 /G76/G69 /G64/G65 /G72 /G66 /G53 /G57/G44 /G54/G20 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G57/G53 /G5B/G32 /G3A/G30 /G5D/G3D /G30/G30/G30/G3A /G32 /G38 /G2F/G66 /G53 /G30/G30/G31/G3A /G32 /G31/G30 /G2F/G66 /G53 /G30/G31/G30/G3A /G32 /G31/G32 /G2F/G66 /G53 /G30/G31/G31/G3A /G32 /G31/G34 /G2F/G66 /G53 /G31/G30/G30/G3A /G32 /G31/G35 /G2F/G66 /G53 /G31/G30/G31/G3A /G32 /G31/G36 /G2F/G66 /G53 /G31/G31/G30/G3A /G32 /G31/G37 /G2F/G66 /G53 /G31/G31/G31/G3A /G32 /G31/G38 /G2F/G66 /G53 /G38/G2D /G74/G6F /G2D/G31 /G20/G4D /G55/G58 /G43/G4C /G52/G20 /G66 /G53/G55 /G42 /G57/G53 /G32/G20 /G7E/G20 /G57/G53 /G30 /G28/G66 /G53 /G2F/G32 /G31 /G20/G7E /G20/G66 /G53 /G2F/G32 /G31/G31 /G29 /G43/G4C /G52/G20 /G57/G44 /G54/G20 /G31/G31 /G20/G73 /G74/G61 /G67/G65/G20 /G44/G69 /G76/G69 /G64/G65 /G72 Watchdog Timer

Rev. 1.61 50 April 11, 2017 Rev. 1.61 51 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to s ome predetermined condition irres pective of outs ide parameters . The most important res et condition is after pow er is fi rst applied to the microcontroller . In this cas e, internal circuitry w ill ensure that the microcontroller , after a short delay , will be in a well defined state and ready to execute the first program instruction. After this power -on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, whi ch wi ll be reset t o zero fo rcing t he m icrocontroller t o begin program execution fr om t he lowest Program Memory address. Another type of reset is when the W atchdog T imer overflows and resets the microcontroller . All typesof reset operations result in dif ferent register conditions being setup. Another reset exists in the form of a Low V oltage Reset, L VR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring internally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the m icrocontroller. As we ll a s e nsuring t hat t he Progra m Me mory be gins e xecution from t he first memory address, a power -on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Power-on Reset SST Time-out tRSTD Power-On Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The L VR function is always enabled with a specific L VR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery , the L VR will automatically reset the device internally and the L VRF bit in the CTRL register will also be set to1. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteri stics. If the low voltage state does not exceed this value, the L VR will ignore the low supply voltage and will not perform a reset function. The actual VLVR is set by the L VRC register . When this happens, the LRF bit in the CTRL register will be set to 1. /G4C/G56 /G52 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 /G74 /G52/G53 /G54/G44 /G20/G2B /G20 /G74 /G53/G53/G54 Low Voltage Reset Timing Chart

Rev. 1.61 52 April 11, 2017 Rev. 1.61 53 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

LVRC Register – BS83B08A-3/BS83B12A-3/BS83B16A-3 Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 L VS7 ~ LVS0: LVR V oltage Select control 01010101: 2.55V(default) 00110011: 2.55V 10011001: 2.55V 10101010: 2.55V Other values: MCU reset (reset will be active after 2~3 LIRC clock for debounce time) Note: S/W can write 00H~FFH to control L VR voltage, even to S/W reset MCU. If the MCU reset caused L VRC software reset, the LRF flag of CTRL register will be set.
LVRC Register – BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 L VS7 ~ LVS0: LVR V oltage Select control 01010101: 2.10V(default) 00110011: 2.10V 10011001: 2.10V 10101010: 2.10V Other values: MCU reset (reset will be active after 2~3 LIRC clock for debounce time) Note: S/W can write 00H~FFH to control L VR voltage, even to S/W reset MCU. If the MCU reset caused L VRC software reset, the LRF flag of CTRL register will be set.
CTRL Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W “×” unknown Bit 7 FSYSON: fSYS Control IDLE Mode Describe elsewhere Bit 6~3 Unimplemented, read as “0” Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low V oltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program.

Rev. 1.61 52 April 11, 2017 Rev. 1.61 53 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Bit 1 LRF: LVR Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the L VRC register contains any non defined L VR voltage register values. This in ef fect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT Control register software reset flag Describe elsewhere

CTRL Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — × 0 0 “×” unknown Bit 7 FSYSON: fSYS Control IDLE Mode Describe elsewhere Bit 6 Unimplemented, read as “0” Bit 5~4 HIRCS1~HIRCS0: High frequency clock select Describe elsewhere Bit 3 Unimplemented, read as “0” Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low V oltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the L VRC register contains any non defined L VR voltage register values. This in ef fect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT Control register software reset flag Describe elsewhere Watchdog Time-out Reset during Normal Operation The W atchdog time-out Reset during normal operation is the same as a L VR reset except that the Watchdog time-out flag T O will be set to “1”. WDT Time-out Internal Reset tRSTD + tSST Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart

Rev. 1.61 54 April 11, 2017 Rev. 1.61 55 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Watchdog Time-out Reset during SLEEP or IDLE Mode The W atchdog time-out Reset during SLEEP or IDLE Mode is a little dif ferent from other kinds of re set. Mo st of t he c onditions re main unc hanged e xcept t hat t he Pro gram Count er a nd t he St ack Pointer will be cle ared to “0” and the T O flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. WDT Time-out Internal Reset tSST Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC. The tSST is 1~2 clock for the LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The dif ferent types of reset described af fect the reset flags in dif ferent ways. These flags, known as P DF and T O are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he SL EEP o r I DLE Mo de f unction o r W atchdog T imer. T he r eset f lags a re shown in the table: TO PDF RESET Conditions 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Eventer Counter Timer/Eventer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. BS83B04A-4 Register Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000

Rev. 1.61 54 April 11, 2017 Rev. 1.61 55 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- -xxx ---- -uuu ---- -uuu STATUS --00 xxxx --1u uuuu --11 uuuu SMOD 000- 0011 000- 0011 uuu- uuuu CTRL 0--- 0x00 0--- 0x00 u--- uuuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -uuu -uuu LVRC 0101 0101 0101 0101 uuuu uuuu PA 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 uuuu uuuu PAPU 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 uuuu uuuu WDTC 0101 0011 0101 0011 uuuu uuuu TMR 0000 0000 0000 0000 uuuu uuuu TMRC --00 -000 --00 -000 --uu -uuu EED 0000 0000 0000 0000 0000 0000 TKTMR 0000 0000 0000 0000 uuuu uuuu TKC0 -000 0000 -000 0000 -uuu uuuu TK16DL 0000 0000 0000 0000 uuuu uuuu TK16DH 0000 0000 0000 0000 uuuu uuuu TKM016DL 0000 0000 0000 0000 uuuu uuuu TKM016DH 0000 0000 0000 0000 uuuu uuuu TKM0ROL 0000 0000 0000 0000 uuuu uuuu TKM0C0 0000 0000 0000 0000 uuuu uuuu TKM0C1 0-00 0000 0-00 0000 u-uu uuuu IICC1 1000 0001 1000 0001 uuuu uuuu IICD 0000 0000 0000 0000 uuuu uuuu IICA 0000 0000 0000 0000 uuuu uuuu I2CTOC 0000 0000 0000 0000 uuuu uuuu Note: “-” not implement “u” stands for “unchanged” “x” stands for “unknown”

Rev. 1.61 56 April 11, 2017 Rev. 1.61 57 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU BS83B08A-3/BS83B08A-4 Register Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu STATUS --00 xxxx --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 uuuu uuuu CTRL 0-00 -x00 0-00 -x00 u-uu -uuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -uuu -uuu LVRC 0101 0101 0101 0101 uuuu uuuu PA 1--1 1111 1--1 1111 u--u uuuu PAC 1--1 1111 1--1 1111 u--u uuuu PAPU 0--0 0000 0--0 0000 u--u uuuu PAWU 0--0 0000 0--0 0000 u--u uuuu WDTC 0101 0011 0101 0011 uuuu uuuu TMR 0000 0000 0000 0000 uuuu uuuu TMRC --00 -000 --00 -000 --uu -uuu EEA --11 1111 --11 1111 --uu uuuu EED 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 uuuu uuuu I2CTOC 0000 0000 0000 0000 uuuu uuuu SIMC0 0000 -00- 0000 -00- uuuu -uu- SIMC1 0000 -000 0000 -000 uuuu -uuu SIMD 0000 0000 0000 0000 uuuu uuuu SIMC2 --11 1111 --11 1111 --uu uuuu SIMA 0000 0000 0000 0000 uuuu uuuu TKTMR 0000 0000 0000 0000 uuuu uuuu TKC0 -000 0000 -000 0000 -uuu uuuu TK16DL 0000 0000 0000 0000 uuuu uuuu TK16DH 0000 0000 0000 0000 uuuu uuuu TKM016DL 0000 0000 0000 0000 uuuu uuuu TKM016DH 0000 0000 0000 0000 uuuu uuuu TKM0ROL 0000 0000 0000 0000 uuuu uuuu TKM0C0 0000 0000 0000 0000 uuuu uuuu

Rev. 1.61 56 April 11, 2017 Rev. 1.61 57 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) TKM0C1 0-00 0000 0-00 0000 u-uu uuuu TKM116DL 0000 0000 0000 0000 uuuu uuuu TKM116DH 0000 0000 0000 0000 uuuu uuuu TKM1ROL 0000 0000 0000 0000 uuuu uuuu TKM1C0 0000 0000 0000 0000 uuuu uuuu TKM1C1 0000 0000 0000 0000 uuuu uuuu Note: “-” not implement “u” stands for “unchanged” “x” stands for “unknown” BS83B12A-3/BS83B12A-4 Register Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu STATUS --00 xxxx --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 uuuu uuuu CTRL 0-00 -x00 0-00 -x00 u-uu -uuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -uuu -uuu LVRC 0101 0101 0101 0101 uuuu uuuu PA 1--1 1111 1--1 1111 u--u uuuu PAC 1--1 1111 1--1 1111 u--u uuuu PAPU 0--0 0000 0--0 0000 u--u uuuu PAWU 0--0 0000 0--0 0000 u--u uuuu WDTC 0101 0011 0101 0011 uuuu uuuu TMR 0000 0000 0000 0000 uuuu uuuu TMRC --00 -000 --00 -000 --uu -uuu EEA --11 1111 --11 1111 --uu uuuu EED 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 uuuu uuuu I2CTOC 0000 0000 0000 0000 uuuu uuuu SIMC0 0000 -00- 0000 -00- uuuu -uu-

Rev. 1.61 58 April 11, 2017 Rev. 1.61 59 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) SIMC1 0000 -000 0000 -000 uuuu -uuu SIMD 0000 0000 0000 0000 uuuu uuuu SIMC2 --11 1111 --11 1111 --uu uuuu SIMA 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 uuuu uuuu TKTMR 0000 0000 0000 0000 uuuu uuuu TKC0 -000 0000 -000 0000 -uuu uuuu TK16DL 0000 0000 0000 0000 uuuu uuuu TK16DH 0000 0000 0000 0000 uuuu uuuu TKM016DL 0000 0000 0000 0000 uuuu uuuu TKM016DH 0000 0000 0000 0000 uuuu uuuu TKM0ROL 0000 0000 0000 0000 uuuu uuuu TKM0C0 0000 0000 0000 0000 uuuu uuuu TKM0C1 0-00 0000 0-00 0000 u-uu uuuu TKM116DL 0000 0000 0000 0000 uuuu uuuu TKM116DH 0000 0000 0000 0000 uuuu uuuu TKM1ROL 0000 0000 0000 0000 uuuu uuuu TKM1C0 0000 0000 0000 0000 uuuu uuuu TKM1C1 0000 0000 0000 0000 uuuu uuuu TKM216DL 0000 0000 0000 0000 uuuu uuuu TKM216DH 0000 0000 0000 0000 uuuu uuuu TKM2ROL 0000 0000 0000 0000 uuuu uuuu TKM2C0 0000 0000 0000 0000 uuuu uuuu TKM2C1 0000 0000 0000 0000 uuuu uuuu Note: “-” not implement “u” stands for “unchanged” “x” stands for “unknown”

Rev. 1.61 58 April 11, 2017 Rev. 1.61 59 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU BS83B16A-3/BS83B16A-4 Register Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu STATUS --00 xxxx --1u uuuu --11 uuuu SMOD 0000 0011 0000 0011 uuuu uuuu CTRL 0-00 -x00 0-00 -x00 u-uu -uuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -uuu -uuu LVRC 0101 0101 0101 0101 uuuu uuuu PA 1--1 1111 1--1 1111 u--u uuuu PAC 1--1 1111 1--1 1111 u--u uuuu PAPU 0--0 0000 0--0 0000 u--u uuuu PAWU 0--0 0000 0--0 0000 u--u uuuu WDTC 0101 0011 0101 0011 uuuu uuuu TMR 0000 0000 0000 0000 uuuu uuuu TMRC --00 -000 --00 -000 --uu -uuu EEA --11 1111 --11 1111 --uu uuuu EED 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 uuuu uuuu I2CTOC 0000 0000 0000 0000 uuuu uuuu SIMC0 0000 -00- 0000 -00- uuuu -uu- SIMC1 0000 -000 0000 -000 uuuu -uuu SIMD 0000 0000 0000 0000 uuuu uuuu SIMC2 --11 1111 --11 1111 --uu uuuu SIMA 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 uuuu uuuu TKTMR 0000 0000 0000 0000 uuuu uuuu TKC0 -000 0000 -000 0000 -uuu uuuu TK16DL 0000 0000 0000 0000 uuuu uuuu TK16DH 0000 0000 0000 0000 uuuu uuuu TKM016DL 0000 0000 0000 0000 uuuu uuuu TKM016DH 0000 0000 0000 0000 uuuu uuuu

Rev. 1.61 60 April 11, 2017 Rev. 1.61 61 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Register LVR&power on WDT Overflow (Normal Mode) WDT Overflow (HALT Mode) TKM0ROL 0000 0000 0000 0000 uuuu uuuu TKM0C0 0000 0000 0000 0000 uuuu uuuu TKM0C1 0-00 0000 0-00 0000 u-uu uuuu TKM116DL 0000 0000 0000 0000 uuuu uuuu TKM116DH 0000 0000 0000 0000 uuuu uuuu TKM1ROL 0000 0000 0000 0000 uuuu uuuu TKM1C0 0000 0000 0000 0000 uuuu uuuu TKM1C1 0000 0000 0000 0000 uuuu uuuu TKM216DL 0000 0000 0000 0000 uuuu uuuu TKM216DH 0000 0000 0000 0000 uuuu uuuu TKM2ROL 0000 0000 0000 0000 uuuu uuuu TKM2C0 0000 0000 0000 0000 uuuu uuuu TKM2C1 0000 0000 0000 0000 uuuu uuuu TKM316DL 0000 0000 0000 0000 uuuu uuuu TKM316DH 0000 0000 0000 0000 uuuu uuuu TKM3ROL 0000 0000 0000 0000 uuuu uuuu TKM3C0 0000 0000 0000 0000 uuuu uuuu TKM3C1 0000 0000 0000 0000 uuuu uuuu Note: “-” not implement “u” stands for “unchanged” “x” stands for “unknown”

Rev. 1.61 60 April 11, 2017 Rev. 1.61 61 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Input/Output Ports Holtek m icrocontrollers of fer c onsiderable fle xibility on t heir I/ O port s. W ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names P A~PC. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. A ll of thes e I/O ports can be used for input and output operations. For input operation, these ports are non-latch ing, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List

BS83B04A-4 Register Name Bit 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0
BS83B08A-3/BS83B08A-4 Register Name Bit 7 6 5 4 3 2 1 0 PAWU D7 — — D4 D3 D2 D1 D0 PAPU D7 — — D4 D3 D2 D1 D0 PA D7 — — D4 D3 D2 D1 D0 PAC D7 — — D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0
BS83B12A-3/BS83B12A-4 Register Name Bit 7 6 5 4 3 2 1 0 PAWU D7 — — D4 D3 D2 D1 D0 PAPU D7 — — D4 D3 D2 D1 D0 PA D7 — — D4 D3 D2 D1 D0 PAC D7 — — D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU — — — — D3 D2 D1 D0 PC — — — — D3 D2 D1 D0 PCC — — — — D3 D2 D1 D0

Rev. 1.61 62 April 11, 2017 Rev. 1.61 63 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

BS83B16A-3/BS83B16A-4 Register Name Bit 7 6 5 4 3 2 1 0 PAWU D7 — — D4 D3 D2 D1 D0 PAPU D7 — — D4 D3 D2 D1 D0 PA D7 — — D4 D3 D2 D1 D0 PAC D7 — — D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . T o eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor . These pull-high resistors are selected using registers P APU~PCPU, and are implemented using weak PMOS transistors. PAPU Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port A bit 7~bit 0 Pull-High Control 0: Disable 1: Enable PAPU Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name D7 — — D4 D3 D2 D1 D0 R/W R/W — — R/W R/W R/W R/W R/W POR 0 — — 0 0 0 0 0 Bit 7 I/O Port A bit 7 Pull-High Control 0: Disable 1: Enable Bit 6~5 Unimplemented, read as “0” Bit 4~0 I/O Port A bit 4~bit 0 Pull-High Control 0: Disable 1: Enable

Rev. 1.61 62 April 11, 2017 Rev. 1.61 63 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU PBPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port B bit 7~bit 0 Pull-High Control 0: Disable 1: Enable PCPU Register – BS83B12A-3/BS83B12A-4 Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0 I/O Port C bit 3~bit 0 Pull-High Control 0: Disable 1: Enable PCPU Register – BS83B16A-3/BS83B16A-4 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port C bit 7~bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HAL T instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. V arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low . This function is especially suitable for applications that can be woken up via extern al switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port A bit 7~bit 0 Pull-High Control 0: Disable 1: Enable

Rev. 1.61 64 April 11, 2017 Rev. 1.61 65 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU PAWU Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name D7 — — D4 D3 D2 D1 D0 R/W R/W — — R/W R/W R/W R/W R/W POR 0 — — 0 0 0 0 0 Bit 7 I/O Port A bit 7 Pull-High Control 0: Disable 1: Enable Bit 6~5 Unimplemented, read as “0” Bit 4~0 I/O Port A bit 4~bit 0 W ake Up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as P AC~PCC, to control the input/output configuration. W ith this control register , each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register . For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 0 0 1 1 1 1 1 Bit 7 I/O Port A bit 7 Input/Output Control 0: Output 1: Input PAC Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name D7 — — D4 D3 D2 D1 D0 R/W R/W — — R/W R/W R/W R/W R/W POR 1 — — 1 1 1 1 1 Bit 7 I/O Port A bit 7 Input/Output Control 0: Output 1: Input Bit 6~5 Unimplemented, read as “0” Bit 4~0 I/O Port A bit 4~bit 0 Input/Output Control 0: Output 1: Input

Rev. 1.61 64 April 11, 2017 Rev. 1.61 65 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU PBC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O Port B bit 7~bit 0 Input/Output Control 0: Output 1: Input PCC Register – BS83B12A-3/BS83B12A-4 Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Unimplemented, read as “0” Bit 3~0 I/O Port C bit 3~bit 0 Input/Output Control 0: Output 1: Input PCC Register – BS83B16A-3/BS83B16A-4 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O Port C bit 7~bit 0 Input/Output Control 0: Output 1: Input Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by application program control. External Interrupt Input The exter nal inter rupt pin, INT , is pin-shared with an I/O pin. T o use the pin as an external interrupt input t he c orrect b its i n t he I NTC0 r egister m ust b e p rogrammed. T he p in m ust a lso b e se t a s a n input by setting the corresponding bit in the SFS Register . A pull-high resistor can also be selected via the appropriate port pull-high resistor register . Note that even if the pin is set as an external interrupt input the I/O function still remains.

Rev. 1.61 66 April 11, 2017 Rev. 1.61 67 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

SFS Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Bit 7~1 Unimplemented, read as “0” Bit 5 SFS0: INT source selection 0: PA0 1: PA6 I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. /G56 /G44/G44 /G4D /G55 /G58 /G57/G61 /G6B/G65 /G2D /G75/G70/G20 /G53/G65 /G6C/G65 /G63/G74 /G53 /G79/G73/G74 /G65/G6D /G20/G57 /G61/G6B /G65/G2D /G75/G70 /G52 /G65/G61/G64/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G44 /G51 /G43/G4B /G53 /G44 /G51 /G43/G4B /G53 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G42/G69 /G74 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G57/G72 /G69/G74 /G65/G20 /G43 /G6F/G6E/G74 /G72/G6F /G6C/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G43/G68 /G69/G70 /G20/G52 /G65/G73 /G65/G74 /G52/G65 /G61/G64 /G20/G43 /G6F/G6E /G74/G72 /G6F/G6C /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G57/G72 /G69/G74 /G65/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G44/G61 /G74/G61 /G20/G42 /G69/G74 /G49/G2F/G4F /G20/G70 /G69/G6E /G51 /G51 /G57/G65 /G61/G6B /G50/G75 /G6C/G6C/G2D /G75/G70 /G50/G75 /G6C/G6C /G2D/G48 /G69/G67 /G68 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G53/G65 /G6C/G65 /G63/G74 /G50/G41/G20 /G6F/G6E /G6C/G79 Generic Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initi alisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. If the port control registers, P AC~PCC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, P A~PC, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming individual b its i n t he p ort c ontrol r egister u sing t he “ SET [ m].i” a nd “CLR [m ].i” i nstructions. Not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

Rev. 1.61 66 April 11, 2017 Rev. 1.61 67 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Timer/Event Counter The provision of timers form an important part of any microcontroller , giving the designer a means of carrying out time related functions. The devices contain one 8-bit. The provision of an internal prescaler to the clock circuitry on gives added range to the timer. There are two types of registers related to the T imer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the T imer/Event Counter. The second type of associated register is the T imer Control Register which defines the timer options. /G4D/G55 /G58 /G66 /G54/G50 /G66 /G53/G55 /G42 /G66 /G53/G59/G53 /G54/G69 /G6D/G65 /G72/G20 /G50/G72 /G65/G73 /G63/G61 /G6C/G65 /G72 /G30 /G31 /G54 /G50/G53/G43 /G20/G5B /G32/G3A /G30/G5D /G37/G20 /G53/G74 /G61/G67/G65/G20 /G43/G6F /G75/G6E /G74/G65 /G72 /G54/G69 /G6D/G65 /G2D /G42/G61 /G73/G65 /G20/G43 /G6F/G6E /G74/G72 /G6F/G6C /G54/G69 /G6D/G65 /G2D /G42/G61 /G73/G65 /G20/G65 /G76/G65 /G6E/G74 /G20/G69 /G6E/G74 /G65/G72 /G72/G75 /G70/G74 /G20/G50 /G65/G72 /G69 /G6F/G64/G20 /G38/G2D /G31/G20 /G4D/G55 /G58 /G37 /G54/G53 /G50/G72 /G65/G6C /G6F/G61/G64 /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G55/G70 /G20/G43 /G6F/G75/G6E /G74/G65 /G72 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G4F/G76 /G65/G72 /G66/G6C /G6F/G77 /G74/G6F /G20/G49 /G6E/G74 /G65/G72 /G72/G75 /G70/G74 /G52/G65 /G6C /G6F/G61/G64 Timer/Event Counter Configuring the Timer/Event Counter Input Clock Source The T imer/Event Count er c lock sourc e c an ori ginate from e ither t he syst em c lock fSYS or t he fSUB oscillator, the choice of which is determined by the TS bit in the TMRC register . This internal clock source is first divided by a prescaler , the division ratio of which is conditioned by the T imer Control Register bits TPSC0~TPSC2. Timer Register – TMR The time r register is a special function register located in the Special Purpose Data Memory and is the place where the actual timer value is stored, it is known as TMR. The value in the timer register increases by one each time an inter nal clock pulse is received The tim er will count from the initial value loaded by the preload register to the full count of FFH at which point the timer overflows and an internal inte rrupt signal is generated. The timer value will then be reset with the init ial preload register value and continue counting. Note that to achie ve a maximum full range count of FFH, the preload register must first be cleared to all z eros. I t sh ould b e n oted t hat a fter p ower-on, t he p reload r egisters wi ll b e i n a n u nknown condition. Note that if the T imer/Event Counter is in an OFF condition and data is written to its preload register , this data will be immediately written into the actual counter . However , if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs.

Rev. 1.61 68 April 11, 2017 Rev. 1.61 69 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Timer Control Register – TMRC The T imer Control Register is known as TMRC. It is the T imer Control Register together with the corresponding t imer r egister t hat c ontrol t he f ull o peration o f t he T imer/Event C ounter. B efore the timer c an b e u sed, i t i s e ssential t hat t he T imer C ontrol R egister i s fu lly p rogrammed wi th t he right data to ensure its correct operation, a process that is normally carried out during program initialisation. The timer -on bit, which is bit 4 of the T imer Control Register and known as T ON, provides the basic on/off control of the timer . Setting the bit high allows the counter to run, clearing the bit stops the counter. Bits 0~2 of the T imer Control Register determine the division ratio of the input clock prescaler. The TS bit selects the internal clock source. TMRC Register Bit 7 6 5 4 3 2 1 0 Name — — TS TON — TPSC2 TPSC1 TPSC0 R/W — — R/W R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 TS: T imer/Event Counter Clock Source 0: fSYS 1: fSUB Bit 4 TON: T imer/Event Counter Counting Enable 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bits 2~0 TPSC2~TPSC0: T imer prescaler rate selection Timer internal clock= 000: fTP 001: fTP/2 010: fTP/4 011: fTP/8 100: fTP/16 101: fTP/32 110: fTP/64 111: fTP/128 Timer Operation The T imer/Event Counter is utilised to measure fixed time intervals, providing an internal interrupt signal e ach t ime t he T imer/Event Count er ove rflows. T he t imer i nput c lock sourc e i s e ither fSYS or fSUB, however, this timer clock source is further divided by a prescaler , the value of which is determined by the bits TPSC2~TPSC0 in the T imer Control Register . The timer -on bit, T ON must be set high to enable the timer to run. Each time an internal clock transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however , the internal i nterrupts c an be disabled by e nsuring t hat t he t imer e nable bi t i n t he i nterrupt re gister i s reset to zero.

Rev. 1.61 68 April 11, 2017 Rev. 1.61 69 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Prescaler Bits T PSC0~TPSC2 of t he T MRC re gister c an be use d t o de fine a di vision ra tio for t he i nternal clock source of the T imer/Event Counter enabling longer time out periods to be setup. Programming Considerations When t he T imer/Event C ounter i s r ead, o r i f d ata i s wr itten t o t he p reload r egister, t he c lock i s inhibited to avoid errors, however as this may result in a counting error , this should be taken into account by the programmer. Care must be taken to ensure that the timer is properly initialised before using it for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialized the timer can be turned on and of f by controlling the enable bit in the timer control regis ter. When the T imer/Event Counter overfl ows, its corres ponding interrupt request flag in the interrupt control register will be set. If the T imer/Event Counter interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabl ed or not, a T imer/Event Counter overflow will also generate a wake-up signal if the device is in a Power-down condition. T o prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Idle/Sleep Mode. Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin s hared w ith the P A, P B and P C logic I/O pins , w ith the des ired function chosen via register bits. Keys are or ganised into groups of four , with each group known as a module and having a module number , M0 to M3. Each module is a fully indepe ndent set of four T ouch Keys and each T ouch Key has its own oscillator . Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Device Keys - n Touch Key Module Touch Key Shared I/O Pin BS83B04A-4 4 M0 K1~K4 PA5, PA1, PA3, PA4 BS83B08A-3/BS83B08A-4 8 M0 K1~K4 PB0~PB3 M1 K5~K8 PB4~PB7 BS83B12A-3/BS83B12A-4 12 M0 K1~K4 PB0~PB3 M1 K5~K8 PB4~PB7 M2 K9~K12 PC0~PC3 BS83B16A-3/BS83B16A-4 16 M0 K1~K4 PB0~PB3 M1 K5~K8 PB4~PB7 M2 K9~K12 PC0~PC3 M3 K13~K16 PC4~PC7

Rev. 1.61 70 April 11, 2017 Rev. 1.61 71 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Touch Key Register Definition Each t ouch k ey m odule, wh ich c ontains f our t ouch k ey f unctions, h as i ts o wn su ite r egisters. T he following table shows the register set for each touch key module. The Mn within the register name refers to the T ouch Key module number, BS83B04A-4 has a M0, BS83B08A-3/BS83B08A-4 has a range of M0 to M1, BS83B12A-3/BS83B12A-4 has a range of M0 to M2, BS83B16A-3/ BS83B16A-4 has a range of M0 to M3. Name Usage TKTMR Touch Key 8-bit timer/counter register TKC0 Counter on-off and clear control/reference clock control/Start bit TK16DL Touch key module 16-bit counter low byte contents TK16DH Touch key module 16-bit counter high byte contents TKC1 Touch key OSC frequency select TKMn16DL Module n 16-bit counter low byte contents TKMn16DH Module n 16-bit counter high byte contents TKMnROL Reference OSC internal capacitor select TKMnROH Reference OSC internal capacitor select TKMnC0 Control Register 0 Multiplexer Key Select TKMnC1 Control Register 1 Key oscillator control/Reference oscillator control/Touch key or I/O select Register Listing Device Register Name Bit 7 6 5 4 3 2 1 0 BS83B04A-4 TKC0 — TKRCOV TKST TKCFOV TK16OV — TK16S1 TK16S0 TKM0C1 M0TSS — M0ROEN M0KOEN M0K4IO M0K3IO M0K2IO M0K1IO Others TKC0 — TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 TKMnC1 MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnK2IO MnK1IO All devices TKTMR D7 D6 D5 D4 D3 D2 D1 D0 TK16DL D7 D6 D5 D4 D3 D2 D1 D0 TK16DH D15 D14 D13 D12 D11 D10 D9 D8 TKMn16DL D7 D6 D5 D4 D3 D2 D1 D0 TKMn16DH D15 D14 D13 D12 D11 D10 D9 D8 TKMnROL D7 D6 D5 D4 D3 D2 D1 D0 TKMnC0 MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 MnSOF1 MnSOF0 Touch Key Module (n=0~3) TKTMR Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch Key 8-bit timer/counter register Time slot counter overflow set-up time is (256-TKTMR[7:0]) × 32

Rev. 1.61 70 April 11, 2017 Rev. 1.61 71 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TKC0 Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name — TKRCOV TKST TKCFOV TK16OV — TK16S1 TK16S0 R/W — R/W R/W R/W R/W — R/W R/W POR — 0 0 0 0 — 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TKRCOV: T ime slot counter overflow flag 0: No overflow 1: Overflow If m odule 0 or Al l m odule (se lect by T SCS bi t) t ime sl ot c ounter i s ove rflow, t he Touch Key Interrupt request flag will be set (TKMF) and all module key OSC and ref OSC auto stop. All module 16-bit C/F counter , 16-bit counter , 5-bit tim e slot counter and 8-bit time slot timer counter will be automatically off. Bit 5 TKST: Start T ouch Key detection control bit 0: Stopped 0→1: Started In all modules the16-bit C/F counter , 16-bit counter , 5-bit time slot counter will be a utomatically c leared whe n t his bi t i s c leared t o “ 0” (8-bi t progra mmable t ime slot counter will not be cleared, which overflow time is setup by user). When this bit changes from low to high, the 16-bit C/F counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically on and enable key OSC and ref OSC output clock input these counters. Bit 4 TKCFOV: T ouch key module 16-bit C/F counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by software. Bit 3 TK16OV: T ouch key module 16-bit counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by software. Bit 2 Unimplemented, read as "0" Bit 1~0 TK16S1~TK16S0: The touch key module 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8

Rev. 1.61 72 April 11, 2017 Rev. 1.61 73 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TKC0 Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name — TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TKRCOV: T ime slot counter overflow flag 0: No overflow 1: Overflow If m odule 0 or Al l m odule (se lect by T SCS bi t) t ime sl ot c ounter i s ove rflow, t he Touch Key Interrupt request flag will be set (TKMF) and all module key OSC and ref OSC auto stop. All module 16-bit C/F counter , 16-bit counter , 5-bit tim e slot counter and 8-bit time slot timer counter will be automatically off. Bit 5 TKST: Start T ouch Key detection control bit 0: Stopped 0→1: Started In all modules the16-bit C/F counter , 16-bit counter , 5-bit time slot counter will be a utomatically c leared whe n t his bi t i s c leared t o “ 0” (8-bi t progra mmable t ime slot counter will not be cleared, which overflow time is setup by user). When this bit changes from low to high, the 16-bit C/F counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically on and enable key OSC and ref OSC output clock input these counters. Bit 4 TKCFOV: T ouch key module 16-bit C/F counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by software. Bit 3 TK16OV: T ouch key module 16-bit counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by software. Bit 2 TSCS: T ouch Key time slot counter select 0: Each Module use own time slot counter. 1: All T ouch Key Module use Module 0 time slot counter. Bit 1~0 TK16S1~TK16S0: The touch key module 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 TKC1 Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~2 Unimplemented, read as "0" Bit 1~0 TKFS1~TKFS0: T ouch key OSC frequency select 00: 500kHz 01: 1000kHz 10: 1500kHz 11: 2000kHz

Rev. 1.61 72 April 11, 2017 Rev. 1.61 73 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TK16DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch key module 16-bit counter low byte contents TK16DH Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch key module 16-bit counter high byte contents TKMn16DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Module n 16-bit counter low byte contents TKMn16DH Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Module n 16-bit counter high byte contents TKMnROL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Reference OSC inernal capacitor select OSC inernal capacitor select : (TKMnRO[9:0] × 50pF)/1024 TKMnROH Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~2 Unimplemented, read as "0" Bit 1~0 Reference OSC inernal capacitor select OSC inernal capacitor select : (TKMnRO[9:0] × 50pF)/1024

Rev. 1.61 74 April 11, 2017 Rev. 1.61 75 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TKMnC0 Register Bit 7 6 5 4 3 2 1 0 Name MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2 MnSOF1 MnSOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~6 MnMXS1~MnMXS0: Multiplexer Key Select Bit 5 MnDFEN: Multi-frequency control 0: Disable 1: Enable Bit 4 MnFILEN: Filter function control 0: Disable 1: Enable Bit3 MnSOFC: C to F OSC frequency hopping function control 0: The frequency hopping function is controlled by MnSOF2~ MnSOF0 bits 1: The frequency hopping function is controlled by hardware regardless of what is the state of MnSOF2~ MnSOF0 bits Bit 2~0 MnSOF2~ MnSOF0: Selecting key OSC and ref OSC frequency as C to F OSC is controlled by software 000: 1380kHz 001: 1500kHz 010: 1670kHz 011: 1830kHz 100: 2000kHz 101: 2230kHz 110: 2460kHz 111: 2740kHz The frequency which is mentioned here willl be changed when the exte rnal or internal capacitor is with dif ferent value. if the touch key operates at a frequency of 2MHz, users can adjust the frequency in scale when select other frequency.

Rev. 1.61 74 April 11, 2017 Rev. 1.61 75 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TKM0C1 Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name M0TSS — M0ROEN M0KOEN M0K4IO M0K3IO M0K2IO M0K1IO R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7 M0TSS: T imer slot counter clock select 0: Ref oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 M0ROEN: Reference OSC control 0: Disable 1: Enable Bit 4 M0KOEN: Key OSC control 0: Disable 1: Enable Bit 3~0 M0K4IO~M0K1IO: I/O pin or touch key function select M0K4IO PA4/Key4

0 I/O

1 Touch key

Rev. 1.61 76 April 11, 2017 Rev. 1.61 77 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TKMnC1 Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnK2IO MnK1IO R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7 MnTSS: T imer slot counter clock select 0: Ref oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 MnROEN: Reference OSC control 0: Disable 1: Enable Bit 4 MnKOEN: Key OSC control 0: Disable 1: Enable Bit 3~0 MnK4IO~MnK1IO: I/O pin or touch key function select MnK4IO M0 M1 M2 M3 PB3/Key4 PB7/Key8 PC3/Key12 PC7/Key16 PB2/Key3 PB6/Key7 PC2/Key11 PC6/Key15 PB1/Key2 PB5/Key6 PC1/Key10 PC5/Key14 PB0/Key1 PB4/Key5 PC0/Key9 PC4/Key13

Rev. 1.61 76 April 11, 2017 Rev. 1.61 77 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Touch Key Operation When a finge r t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. By using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch actions can be sensed by mea suring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. During this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not.These devic e s contain four touch key inputs which are shared with logical I/O pins, with the desired function selected using register bits. Using the TSCS bit in the TKC0 register can select the module 0 time slot counter as the time slot counter for a ll m odules. Al l m odules use t he sa me st arted si gnal. T he16-bit C/ F c ounter, 16- bit counter, 5-bit time slot counter in all modules will be automatically cleared when this bit is cleared to "0", but the 8-bit programmable time slot counter will not be cleared. The overflow time is setup by user. When this bit changes from low to high, the 16-bit C/F counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be automatically stopped and the 16-bit C/F counte r, 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched of f when the 5-bit time slot counter overflows. The clock source for the time slot c ounter and 8+5 bi t count er, i s sourc ed from t he refe rence osc illator or fSYS/4. The refe rence oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register . When the time s lot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module, which consists of four touch keys, Key 1~Key 4 is contained in module 0, Key 5~Key 8 is contained in module 1, Key 9~Key 12 is contained in module 2 and Key 13~Key 16 is contained in the module 3. Each touch key module has an identical structure.

Rev. 1.61 78 April 11, 2017 Rev. 1.61 79 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU KEY 1 KEY 2 KEY 3 KEY 4 KEY OSC KEY OSC KEY OSC KEY OSC MUX. Filter Overflow 16-bit counter OverflowfSYS,fSYS/2,fSYS/4,fSYS/8 TK16S1~TK16S0 5-bit time slot counter Overflow8-bit time slot timer counter Ref OSC MUX. fSYS/4 MnTSS 8-bit time slot timer counter preload register Overflow Multi-frequency 16-bit C/F counter Note: Each touch key module contains the content in the dash line. Touch Switch Module Block Diagram The touch key sense oscilltor and reference oscillator timing diagram is shown in the following figure: TKST ENCK fTMCK (DFEN=0) fTMCK (DFEN=1) Time slot counter overflow flag Set Touch Key Interrupt request flag Hardware set to “0” TSTMR overflow * 32 fREF KEY OSC EN KEY OSC CLK REF OSC EN

Rev. 1.61 78 April 11, 2017 Rev. 1.61 79 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G54 /G6F/G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G4D/G30 /G4B/G34 /G49/G4F /G20/G62 /G69/G74 /G4D/G30 /G4B/G33 /G49/G4F /G20/G62 /G69/G74 /G4D/G30 /G4B/G32 /G49/G4F /G20/G62 /G69/G74 /G4D/G30 /G4B/G31 /G49/G4F /G20/G62 /G69/G74 /G45/G78 /G74/G65 /G72 /G6E/G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54 /G6F/G75/G63 /G68/G20 /G4B/G65 /G79 /G54 /G6F/G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G45/G78 /G74/G65 /G72 /G6E/G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54 /G6F/G75/G63 /G68/G20 /G4B/G65 /G79 /G54 /G6F/G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G45/G78 /G74/G65 /G72 /G6E/G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54 /G6F/G75/G63 /G68/G20 /G4B/G65 /G79 /G54 /G6F/G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G45/G78 /G74/G65 /G72 /G6E/G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54 /G6F/G75/G63 /G68/G20 /G4B/G65 /G79 Touch Key or I/O Function Select Touch Key Interrupt The touch key only has single inter rupt, when the time slot counter in all the touch key modules or in t he t ouch ke y m odule 0 ove rflow s, an a ctual touch key i nterrupt wi ll t ake pl ace. T he 16-bit C/ F counter, 1 6-bit c ounter, 5 -bit t ime sl ot c ounter and 8-bit t ime sl ot c ounter i n a ll m odule s wi ll b e automatically cleared. The TKCFOV flag, which is the 16-bit C/F counter overflow flag will go high when any of the Touch K ey M odule 16-bit C/F counter overfl ows. As this fl ag w ill not be automatically cleared, it has to be cleared by the application program. Module 0 only contains one 16-bit counter. The TK16OV flag, which is the 16-bit counter overflow flag will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the appl ication program. More details regarding the touch key interrupt is located in the interrupt section of the datasheet. Programming Considerations After t he rel evant regi sters are se tup, t he t ouch key det ection process i s i nitiated t he cha nging t he TKST bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag, whi ch i s t he t ime sl ot c ounter fla g wi ll go hi gh a nd re main hi gh unt il t he c ounter ove rflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.

Rev. 1.61 80 April 11, 2017 Rev. 1.61 81 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Serial Interface Module – SIM These devices except BS83B04A-4 contain a Serial Interface Module, which include both the four line SPI interface and the two line I2C interface types while BS83B04A-4 only contains the I2C interface, to allow an easy method of communication with external peripheral hardware. Having relatively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow t he m icrocontroller to i nterface t o e xternal SPI o r I2C b ased h ardware su ch a s se nsors, Fl ash m emory o r E EPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register . As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or s lave. A lthough the S PI interface s pecification can control multiple s lave devices from a single master , but this device provided only one SCS pin. If the mas ter needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. I t i s a f our l ine i nterface wi th p in names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by setting the correct bits in the SIMC0 and SIMC2 registers. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations b eing i mplemented by t he m aster. T he Ma ster a lso c ontrols t he c lock si gnal. As t he d evice only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to "1" to enable SCS pin function, set CSEN bit to "0" the SCS pin will be as I/O function. /G53/G50 /G49/G20/G4D /G61/G73/G74 /G65/G72 /G53/G50 /G49/G20/G53 /G6C /G61/G76/G65 /G53/G43 /G4B /G53/G44 /G4F /G53/G44 /G49 /G53/G43 /G53 /G53/G43 /G4B /G53/G44 /G49 /G53/G44 /G4F /G53/G43 /G53 SPI Master/Slave Connection

Rev. 1.61 80 April 11, 2017 Rev. 1.61 81 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G53/G44 /G49/G20 /G50/G69 /G6E /G53/G44 /G4F/G20 /G50/G69 /G6E /G53/G49 /G4D/G44 /G54/G78 /G2F/G52 /G78/G20 /G53/G68 /G69 /G66/G74/G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G42/G75 /G73/G79 /G53/G74 /G61/G74 /G75/G73 /G54/G52 /G46/G20 /G46/G6C /G61/G67 /G57/G43 /G4F/G4C /G20/G46 /G6C/G61 /G67 /G43/G6C /G6F/G63 /G6B /G45/G64 /G67/G65 /G2F/G50 /G6F/G6C /G61/G72 /G69/G74 /G79 /G43/G6F /G6E/G74 /G72/G6F /G6C /G43/G6C /G6F/G63 /G6B /G53/G6F /G75/G72 /G63/G65 /G20/G53 /G65/G6C /G65/G63 /G74 /G66 /G53/G59 /G53 /G66 /G53/G55 /G42 /G54/G69 /G6D/G65 /G72/G20 /G6F/G76 /G65/G72 /G66/G6C /G6F/G77 /G20/G66/G72 /G65/G71/G75/G65/G6E/G63 /G79/G2F /G32 /G53/G43 /G4B/G20 /G50/G69 /G6E /G53/G43 /G53/G20 /G50/G69 /G6E /G43/G53 /G45/G4E /G20/G62 /G69/G74 /G43/G4B /G45/G4E /G20/G62 /G69/G74 /G43 /G4B/G50/G4F /G4C/G42 /G20/G62 /G69/G74 SPI Block Diagram The SPI function in this device offers the following features:

Full duplex synchronous data transfer
Both Master and Slave modes
LSB first or MSB first data transmission modes
Transmission complete flag
Rising or falling active clock edge The status of the SPI interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 — — — SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 — — CKPOLB CKEG MLS CSEN WCOL TRF SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register . After the data is received from the SPI bus, the device can read it from the SIMD register . Any transmission or reception of data from the SPI bus must be made via the SIMD register.

Rev. 1.61 82 April 11, 2017 Rev. 1.61 83 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI functio n, only by the I2C function. Register SIMC0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. Al though not c onnected wi th t he SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler . Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc.
SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 — — — SIMEN — R/W R/W R/W R/W — — — R/W — POR 1 1 1 — — — 0 — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is TMR frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operatin g mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slav e selection and the SPI Master clock frequency . The SPI clock is a function of the system clock but can also be chosen to be sourced from the Timer/Event counter. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4~2 Unimplemented, read as "0" Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bi t is the overa ll on/of f control for the SIM interface. Whe n the SIMEN bi t is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be as I/O function and the SIM operating current will be reduced to a minimum value. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low tohigh, the contents of t he I2C c ontrol bi ts such a s HT X a nd T XAK wi ll re main a t t he pre vious settings and should therefore be first initialised by the application program while the relevant I2C flags s uch as H CF, H AAS, H BB, S RW and RX AK w ill be s et to their default states. Bit 0 Unimplemented, read as "0"

Rev. 1.61 82 April 11, 2017 Rev. 1.61 83 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name — — CKPOLB CKEG MLS CSEN WCOL TRF R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 CKPOLB: Determines the base condition of the clock line 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bi t determines the ba se condition of the clock line, if the bi t is hi gh, then t he SCK line wi ll be l ow whe n t he c lock i s i nactive. W hen t he CKPOL B bi t i s low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. T he CKPOL B bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he SCK l ine will be low when the clock is inact ive. When the CKPOLB bit is low , then the SCK line will be high when the clock is inactive. Bit 3 MLS: SPI Data shift order This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low , then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI W rite Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation . This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Bit 0 TRF: SPI T ransmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the T ransmit/Receive Complete flag and is set “1” automatically when an SPI data transmission is completed, but must set to “0” by the application program. It can be used to generate an interrupt.

Rev. 1.61 84 April 11, 2017 Rev. 1.61 85 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU SPI Communication After t he SPI i nterface i s e nabled by se tting t he SIME N bi t hi gh, t hen i n t he Ma ster Mode , whe n data is written to the SIMD register , transmission/reception will begin simultaneously . When the data t ransfer is c omplete, t he T RF fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register . The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G2C/G20/G43 /G4B/G45/G47 /G3D/G30 /G29 /G53/G49 /G4D/G45 /G4E/G2C /G20/G43 /G53/G45 /G4E/G3D /G31 /G53/G49 /G4D/G45 /G4E/G3D /G31/G2C /G20/G43 /G53/G45/G4E /G3D/G30 /G20/G28 /G45/G78 /G74/G65 /G72/G6E /G61/G6C /G20/G50 /G75/G6C /G6C/G2D /G48/G69 /G67/G68 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G2C/G20 /G43/G4B /G45/G47 /G3D/G30 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G2C/G20 /G43/G4B /G45/G47 /G3D/G31 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G2C/G20 /G43/G4B /G45/G47 /G3D/G31 /G29 /G53/G44 /G4F/G20 /G28/G43 /G4B/G45/G47 /G3D/G30 /G29 /G53/G44 /G4F/G20 /G28/G43 /G4B/G45/G47 /G3D/G31 /G29 /G53/G43 /G53 /G53/G44 /G49/G20/G44 /G61/G74 /G61/G20 /G43 /G61/G70/G74 /G75/G72 /G65 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G57/G72 /G69/G74 /G65/G20 /G74/G6F /G20/G53 /G49/G4D /G44 SPI Master Mode Timing /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G29 /G53/G44 /G4F /G53/G43 /G53 /G53/G44 /G49/G20 /G44/G61 /G74/G61 /G20/G43 /G61/G70/G74 /G75/G72 /G65 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G57/G72 /G69/G74 /G65/G20 /G74/G6F /G20/G53 /G49/G4D /G44 /G28/G53 /G44/G4F /G20/G64 /G6F/G65 /G73/G20 /G6E/G6F/G74 /G20/G63 /G68/G61/G6E/G67/G65 /G20/G75 /G6E/G74 /G69/G6C /G20/G66 /G69/G72 /G73/G74 /G20/G53 /G43/G4B /G20 /G65/G64/G67/G65/G29 SPI Slave Mode Timing – CKEG=0

Rev. 1.61 84 April 11, 2017 Rev. 1.61 85 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G29 /G53/G44 /G4F /G53/G43 /G53 /G53/G44 /G49/G20/G44 /G61/G74 /G61/G20 /G43 /G61/G70/G74 /G75/G72 /G65 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G57/G72 /G69/G74 /G65/G20 /G74/G6F /G20/G53 /G49/G4D /G44 /G28/G53 /G44/G4F /G20/G63 /G68 /G61/G6E/G67/G65/G73 /G20/G61 /G73/G20 /G73/G6F /G6F/G6E /G20/G61 /G73/G20 /G77/G72 /G69/G74 /G69 /G6E/G67/G20 /G6F /G63/G63/G75 /G72/G73 /G3B/G20 /G53/G44 /G4F/G20 /G69/G73 /G20/G66/G6C /G6F/G61 /G74/G69 /G6E/G67 /G20/G69 /G66/G20 /G53/G43 /G53/G3D /G31/G29 /G4E/G6F /G74/G65 /G3A /G46/G6F /G72/G20 /G53/G50 /G49/G20 /G73/G6C /G61/G76 /G65/G20 /G6D/G6F /G64/G65 /G2C/G20/G69 /G66/G20 /G53/G49 /G4D /G45/G4E /G3D/G31 /G20/G61 /G6E/G64 /G20/G43 /G53/G45 /G4E/G3D /G30/G2C /G20/G53 /G50/G49 /G20/G69 /G73/G20 /G61/G6C /G77/G61 /G79/G73 /G20/G65 /G6E /G61/G62/G6C /G65/G64 /G20/G61 /G6E/G64 /G20/G69 /G67 /G6E/G6F/G72 /G65/G73 /G20/G74/G68 /G65/G20 /G53/G43 /G53/G20 /G6C/G65 /G76/G65 /G6C/G2E SPI Slave Mode Timing – CKEG=1 /G53/G49 /G4D/G45 /G4E/G20 /G3D/G31 /G57/G72 /G69/G74 /G65/G20 /G44/G61 /G74/G61 /G69/G6E /G74/G6F /G20/G53 /G49/G4D /G44 /G57/G43 /G4F/G4C /G3D/G31 /G3F /G43/G6C /G65/G61 /G72/G20 /G57/G43 /G4F/G4C /G59 /G54/G72 /G61/G6E /G73/G6D /G69/G73 /G73/G69 /G6F/G6E /G63/G6F /G6D/G70 /G6C/G65 /G74 /G65/G64/G20 /G3F /G28/G54 /G52/G46 /G3D/G31 /G20/G3F /G29/G20 /G4E /G59 /G52 /G65/G61/G64 /G20/G44 /G61/G74 /G61 /G66/G72 /G6F/G6D /G20/G53 /G49/G4D /G44 /G43/G6C /G65/G61 /G72/G20 /G54/G52 /G46 /G54/G72 /G61/G6E /G73/G66 /G65/G72 /G46 /G69/G6E /G69/G73 /G68 /G65/G64/G3F /G4E /G59 /G45/G4E /G44 /G6D/G61 /G73/G74 /G65/G72 /G20/G6F /G72 /G73/G6C /G61/G76 /G65 /G3F /G4D/G61 /G73/G74 /G65/G72 /G53/G6C /G61/G76 /G65 /G41 /G41 /G53/G50/G49 /G20/G74/G72 /G61/G6E /G73/G66 /G65/G72 /G20 /G43 /G6F/G6E/G66 /G69 /G67/G75/G72 /G65/G20 /G43 /G4B/G50/G4F /G4C/G42 /G2C /G43/G4B /G45/G47 /G2C/G20/G43 /G53/G45/G4E /G20/G61 /G6E/G64 /G20/G4D /G4C/G53 /G20 /G53/G49 /G4D/G5B /G32/G3A /G30/G5D /G3D /G30/G30/G30 /G2C /G30/G30/G31/G2C /G30/G31/G30 /G2C/G30 /G31/G31/G20 /G6F/G72 /G20/G31 /G30/G30/G20 /G53/G49 /G4D/G5B /G32/G3A /G30/G5D /G3D /G31/G30/G31 /G4E SPI Transfer Control Flowchart

Rev. 1.61 86 April 11, 2017 Rev. 1.61 87 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory e tc. Or iginally d eveloped b y Ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. /G44/G65 /G76/G69 /G63/G65 /G53/G6C /G61/G76 /G65 /G44/G65 /G76/G69 /G63/G65 /G4D/G61 /G73/G74 /G65/G72 /G44/G65 /G76/G69 /G63/G65 /G53/G6C /G61/G76 /G65 /G56/G44 /G44 /G53/G44 /G41 /G53/G43 /G4C I2C Master/Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interf ace, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two device s communicate with each other on the bidirectional I2C bus, one is known as the master de vice a nd one a s t he sl ave de vice. Bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. For t his de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. The debounce tim e of the I2C interf ace uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time is 2 system clocks for the devices except BS83B04A-4, while the debounce time is selected via the IICC0 register for the BS83B04A-4. T o achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C St andard or Fast m ode op eration, use rs m ust t ake c are of t he se lected syst em c lock fr equency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) 2 system clock debounce fSYS > 4MHz fSYS > 10MHz I2C Minimum fSYS Frequency (except BS83B04A-4)

Rev. 1.61 86 April 11, 2017 Rev. 1.61 87 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G53/G54 /G41/G52 /G54/G20 /G73/G69 /G67/G6E/G61/G6C /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G53/G65 /G6E/G64 /G20/G73 /G6C/G61 /G76/G65 /G20 /G61/G64/G64 /G72/G65 /G73/G73 /G61/G6E/G64/G20 /G52/G2F /G57/G20 /G62/G69 /G74/G20/G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G41 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65 /G66/G72 /G6F/G6D /G20/G73 /G6C/G61 /G76/G65 /G53 /G65/G6E/G64/G20 /G64/G61/G74 /G61/G20 /G62/G79 /G74/G65 /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G41 /G63/G6B /G6E/G6F/G77 /G6C /G65/G64/G67 /G65 /G66/G72 /G6F/G6D /G20/G73 /G6C/G61 /G76/G65 /G53/G54 /G4F/G50 /G20/G73 /G69/G67 /G6E/G61 /G6C /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 I2C Registers (except BS83B04A-4) There are four control registers associated with the I2C bus, SIMC0, SIMC1, SIMA and I2CT OC and one data register , SIMD. The SIMD register , which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register . After the data is received from the I2C bus, the micro controller can read it from the SIMD register . Any transmission or reception of data from the I2C bus must be made via the SIMD register . The SIM pins are pin shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 — — — SIMEN — SIMC1 HCF HAAS HBB HTX TXAK SRW RNIC RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA A6 A5 A4 A3 A2 A1 A0 — I2CTOC I2CTOEN I2CTOF I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 I2C Registers List

Rev. 1.61 88 April 11, 2017 Rev. 1.61 89 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 — — — SIMEN — R/W R/W R/W R/W — — — R/W — POR 1 1 1 — — — 0 — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is TMR frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operatin g mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slav e selection and the SPI Master clock frequency . The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4~2 Unimplemented, read as "0" Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bi t is the overa ll on/of f control for the SIM interface. Whe n the SIMEN bi t is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be as I/O function and the SIM operating current will be reduced to a minimum value. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low tohigh, the contents of t he I2C c ontrol bi ts such a s HT X a nd T XAK wi ll re main a t t he pre vious settings and should therefore be first initialised by the application program while the relevant I2C flags s uch as H CF, H AAS, H BB, S RW and RX AK w ill be s et to their default states. Bit 0 Unimplemented, read as "0"

Rev. 1.61 88 April 11, 2017 Rev. 1.61 89 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW RNIC RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HASS flag i s t he a ddress m atch flag. T his flag i s used t o de termine i f t he sla ve device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy which will occur when a ST ART signal is detected. The flag will be set to “0” when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to “0” before further data is received. Bit 2 SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SR W f lag i s t he I2C Sl ave R ead/Write f lag. T his f lag d etermines wh ether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SR W flag to determine whether it should be in transmit mode or receive mode. If the SR W flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SR W flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 RNIC: I2C running using Internal Clock Control 0: I2C running using internal clock 1: I2C running not using Internal Clock The I2C module can run w ithout us ing internal clock, and generate an interrupt if the SIM interrupt is enabled, which can be used in SLEEP Mode, IDLE Mode, NORMAL(SLOW) Mode.If this bit is set to “1” and MCU is in “HALT”, slave-receiver can work well but slave-transmitter doesn’t work since it needs system clock .

Rev. 1.61 90 April 11, 2017 Rev. 1.61 91 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Bit 0 RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The R XAK fl ag i s t he r eceiver a cknowledge f lag. W hen t he R XAK f lag i s “ 0”, i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. T he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus.

I2CTOC Register Bit 7 6 5 4 3 2 1 0 Name I2CTOEN I2CTOF I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 I2CTOEN: I2C Time-out Countrol 0: Disable 1: Enable Bit 6 HAAS: T ime-out flag 0: No time-out 1: Time-out occurred Bit 5~0 I2CTOS5~I2CTOS0: T ime-out Definition I2C time-out clock source is fSUB/32 I2C time-out time is given by: ([I2CTOS5 : I2CTOS0]+1) × (32/fSUB)
SIMA Register Bit 7 6 5 4 3 2 1 0 Name A6 A5 A4 A3 A2 A1 A0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR x x x x x x x — “x” unknown Bit 7~1 A6~A0: I2C slave address A6~A0 is the I2C slave address bit 6~bit 0. The SI MA r egister i s a lso u sed b y t he SPI i nterface b ut h as t he n ame SI MC2. T he SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address . Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register , the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Unimplemented, read as "0" I2C Registers – BS83B04A-4 There are four control registers associated with the I2C bus, IICC0, IICC1, IICA and I2CT OC and one data register , IICD. The IICD register is used to store the data being transmitted and received on the I2C bus. Before the microcontro ller writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register . After the data is received from the I2C bus, the microcontroller can read it from the IICD register . Any transmission or reception of data from the I2C bus must be made via the IICD register.

Rev. 1.61 90 April 11, 2017 Rev. 1.61 91 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Register Name Bit 7 6 5 4 3 2 1 0 IICC0 — — — — IICDEB1 IICDEB0 IICEN — IICC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK IICD D7 D6 D5 D4 D3 D2 D1 D0 IICA A6 A5 A4 A3 A2 A1 A0 — I2CTOC I2CTOEN I2CTOF I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 I2C Registers List

IICC0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — IICDEB1 IICDEB0 IICEN — R/W — — — — R/W R/W R/W — Bit 7~4 Unimplemented, read as “0” Bit 3~2 IICDEB1~ IICDEB0: I2C Debounce T ime Selection 00: No debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce Bit 1 IICEN: I2C enable control 0: Disable 1: Enable Bit 0 Unimplemented, read as “0”.
IICC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R FOR 1 0 0 0 0 0 0 1 Bit 7~2 The same as the bit 7~bit 2 of the SIMC1 register. Bit 1 IAMWU: I2C Address Match W ake-up Control 0: Disable 1: Enable – must be cleared by the application program after wake-up. This bit should be set to “1” to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by application program after wake-up to ensure correction device operation. Bit 0 The same as the bit 0 of the SIMC1 register.
IICD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W FOR x x x x x x x x “x” unknown Bit 7~0 The same as the bit 7~bit 0 of the SIMD register.

Rev. 1.61 92 April 11, 2017 Rev. 1.61 93 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

IICA Register Bit 7 6 5 4 3 2 1 0 Name A6 A5 A4 A3 A2 A1 A0 — R/W R/W R/W R/W R/W R/W R/W R/W — FOR 0 0 0 0 0 0 0 — Bit 7~0 The same as the bit 7~bit 0 of the SIMA register. /G49 /G32 /G43/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G28/G53 /G49/G4D /G44/G20 /G6F/G72 /G20/G49/G49 /G43/G44/G29 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G28/G53 /G49/G4D /G41/G20 /G6F/G72 /G20/G49/G49/G43 /G41/G29 /G53/G68 /G69/G66 /G74/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G44/G69 /G72/G65 /G63/G74 /G69/G6F /G6E/G20 /G43/G6F /G6E/G74 /G72/G6F /G6C /G4D /G55 /G58 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G4D/G61 /G74/G63 /G68 /G48/G41 /G41/G53 /G20/G42 /G69/G74 /G49 /G32 /G43/G20 /G49/G6E /G74/G65 /G72/G72 /G75/G70 /G74 /G44/G61 /G74/G61 /G20/G69 /G6E/G20 /G4C/G53 /G42/G20 /G44/G61 /G74/G61 /G20/G4F /G75 /G74/G20/G20 /G4D/G53 /G42 /G54/G72 /G61/G6E /G73/G6D /G69/G74 /G2F/G52 /G65/G63 /G65/G69 /G76/G65 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G55/G6E /G69/G74 /G38/G2D /G62/G69 /G74/G20/G44 /G61/G74 /G61/G20 /G43/G6F /G6D/G70 /G6C/G65 /G74/G65 /G44/G65 /G74/G65 /G63/G74 /G20/G53 /G74/G61 /G72/G74 /G20/G6F /G72/G20 /G53/G74 /G6F/G70 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G41/G64 /G64/G72 /G65/G73 /G73 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G45 /G6E/G61/G62 /G6C/G65 /G2F/G44 /G69/G73 /G61/G62 /G6C/G65 /G20/G41 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65 /G52/G65 /G61/G64 /G2F/G77 /G72/G69 /G74/G65 /G20/G53 /G6C/G61 /G76/G65 /G53/G52 /G57/G20 /G42/G69 /G74 /G48/G42 /G42/G20 /G42/G69 /G74 /G48/G54 /G58/G20 /G42/G69 /G74 /G48/G43 /G46/G20 /G42/G69 /G74 /G53/G43 /G4C/G20 /G50/G69 /G6E /G53/G44 /G41/G20 /G50/G69 /G6E /G53/G49 /G4D/G54 /G4F/G46 /G20/G62 /G69/G74 I2C Block Diagram I2C Bus Communication Communication on the I2C bus requires four separate steps, a ST ART signal, a slave device address transmission, a data transmission and finally a ST OP signal. When a ST ART signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 or IICC1 register will be set and an I2C interrupt will be generated. After ent ering the interrupt s ervice routine, the s lave device mus t firs t check the condition of the H AAS bit to determine wh ether t he i nterrupt sou rce o riginates f rom a n a ddress m atch o r f rom t he c ompletion of an 8-bit data transfer . During a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this:
Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to “1” for the devices except BS83B04A-4 or set the IICEN bit in the IICC0 register to "1" for the BS83B04A-4 to enable the I2C bus.
Step 2 Write the slave address of the device to the I2C bus address register SIMA or IICA.
Step 3 Set the SIME or I2CE interrupt enable bit of the interrupt control register to enable the SIM interrupt .

Rev. 1.61 92 April 11, 2017 Rev. 1.61 93 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Set SIM[2:0]=110 Set SIMEN or IICEN Write Slave Address to SIMA or IICA I2C Bus Interrupt=? CLR SIME or I2CE Poll SIMF or I2CF to decide when to go to I2C Bus ISR No Yes SET SIME or I2CE Wait for Interrupt Goto Main Program Goto Main Program Start I2C Bus Initialisation Flow Chart I2C Bus Start Signal The ST ART signal can only be generated by the master device connected to the I2C bus and not by the slave device. This ST ART signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A ST ART condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The t ransmission o f a ST ART si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he I2C b us. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the ST ART signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SR W bit of the SIMC1 or IICC1 register . The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, t he HAAS bi t shoul d be e xamined t o se e whe ther t he i nterrupt sourc e ha s c ome from a matching slave address or from the completion of a data byte transfer . When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD or IICD regis ter, or in the receive mode w here it mus t implement a dummy read from the S IMD or IICC1 register to release the SCL line.

Rev. 1.61 94 April 11, 2017 Rev. 1.61 95 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU I2C Bus Read/Write Signal The SR W bit in the SIMC1 or IICC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver . If the SR W flag is “1” then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter . If the SR W flag is “0” then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the mas ter has trans mitted a calling addres s, any s lave device on the I2C bus , w hose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a ST OP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SR W flag to determine if it is to be a transmitter or a receiver . If the SR W flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 or IICC1 register should be set to “1”. If the SR W flag is low , then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 or IICC1 register should be set to “0”. I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of i ts sla ve a ddress. T he orde r of seri al bi t t ransmission i s t he MSB fi rst a nd t he L SB l ast. Afte r receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver , then the slave transmitter will release the SDA line to allow the master to send a ST OP signal to releas e the I2C Bus . The corresponding data will be stored in the SIMD or IICD register. If setup as a transmitter , the slave device must first write the data to be transmitted into the SIMD or IICD register . If setup as a receiver , the slave device must read the transmitted data from the SIMD or IICD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 or IICC1 register to determine if it is to send anothe r data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master.

Rev. 1.61 94 April 11, 2017 Rev. 1.61 95 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G44/G61 /G74/G61 /G31/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30 /G30 /G31 /G30 /G30/G31/G30/G31/G30 /G31 /G31 /G53/G3D /G53/G74 /G61/G72 /G74/G20/G28 /G31/G20 /G62/G69 /G74/G29 /G53/G41 /G3D/G53 /G6C/G61 /G76/G65 /G20/G41 /G64/G64 /G72/G65 /G73/G73 /G20/G28 /G37/G20 /G62/G69 /G74/G73 /G29 /G53/G52 /G3D/G53 /G52/G57 /G20/G62 /G69/G74 /G20/G28 /G31/G20 /G62/G69 /G74/G29 /G4D/G3D /G53/G6C /G61/G76 /G65/G20 /G64/G65 /G76/G69 /G63/G65 /G20/G73 /G65/G6E/G64/G20 /G61 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65/G20 /G62/G69 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G44/G3D /G44/G61 /G74/G61 /G20/G28 /G38/G20 /G62/G69 /G74/G73 /G29 /G41/G3D /G41/G43 /G4B /G20/G28 /G52/G58 /G41/G4B /G20/G62 /G69/G74 /G20/G66 /G6F/G72 /G20/G74/G72 /G61/G6E /G73/G6D /G69 /G74/G74/G65 /G72/G2C /G20/G54 /G58/G41/G4B /G20/G62 /G69/G74 /G20/G66/G6F /G72/G20 /G72/G65 /G63/G65 /G69/G76 /G65/G72 /G20/G31 /G20/G62 /G69/G74 /G29 /G50/G3D /G53/G74 /G6F/G70 /G20/G28 /G31/G20 /G62/G69 /G74/G29 /G53/G43 /G4C /G53/G74 /G61/G72 /G74 /G53/G44 /G41 /G53/G52 /G57 /G41/G43 /G4B /G41/G43 /G4B /G53/G74 /G6F/G70 /G53/G43 /G4C /G53/G44 /G41 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73 /G53/G53 /G41/G53 /G52 /G4D/G44 /G41/G44 /G41 /G53/G53 /G41/G53 /G52 /G4D/G44 /G41/G44 /G41/G50 I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD or IICD register , or in the receive mode where it must implement a dummy read from the SIMD or IICD register to release the SCL line. /G48/G41 /G41/G53 /G3D/G31 /G3F /G48/G54 /G58/G3D /G31 /G20/G20/G20/G20 /G3F /G53/G52 /G57/G3D /G31 /G20/G20/G20/G20/G20/G3F /G59/G65 /G73 /G4E/G6F /G59/G65 /G73 /G4E/G6F /G52/G58 /G41/G4B/G3D /G31 /G3F /G59/G65 /G73 /G4E/G6F /G4E/G6F /G52 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G53/G49 /G4D/G44 /G20/G74 /G6F/G20 /G72/G65 /G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G6C/G69 /G6E/G65 /G52/G45 /G54/G49 /G59/G65 /G73 /G44/G75 /G6D/G6D /G79/G20 /G72 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G53/G49 /G4D/G44 /G20/G74/G6F /G20/G72 /G65/G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G52/G45 /G54/G49 /G52/G45 /G54/G49 /G57/G72 /G69/G74 /G65/G20 /G64/G61 /G74/G61 /G20/G74 /G6F/G20 /G53/G49 /G4D/G44 /G72/G65 /G6C /G65/G61/G73 /G65/G20 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G53/G45 /G54/G20 /G48/G54 /G58 /G57/G72 /G69/G74 /G65/G20 /G64/G61 /G74/G61 /G20/G74 /G6F/G20 /G53/G49 /G4D/G44 /G74/G6F /G20/G72 /G65/G6C /G65/G61 /G73/G65 /G20/G53 /G43/G4C /G20/G4C /G69/G6E /G65 /G52/G45 /G54/G49 /G43/G4C /G52/G20 /G48/G54 /G58 /G43/G4C /G52/G20 /G54 /G58/G41/G4B /G44/G75 /G6D/G6D /G79/G20 /G72 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G53/G49 /G4D/G44 /G20/G74 /G6F/G20 /G72/G65 /G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G43/G4C /G52/G20 /G48/G54 /G58 /G43/G4C /G52/G20 /G54 /G58/G41/G4B /G52/G45 /G54/G49 /G53/G74 /G61/G72 /G74 I2C Bus ISR Flow Chart

Rev. 1.61 96 April 11, 2017 Rev. 1.61 97 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU I2C Time-out Control In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, clock, a time-out function is provided. If the clock source to the I2C is not received then after a fixed time period, the I2C circuitry and registers will be reset. The time-out counter starts counting on an I2C bus “ST ART” and “address match” condition, and is cleared b y a n SC L f alling e dge. B efore t he n ext SC L f alling e dge a rrives, i f t he t ime e lapsed i s greater than the time-out setup by the I2CT OC regis ter, then a time-out condition w ill occur . The time-out function will stop when an I2C “STOP” condition occurs. When an I2C time -out counte r overflow occurs, the counter will stop and the I2CT OEN bit will be cleared to zero and the I2CTOF bit will be set high to indicate that a time-out condition as occurred. The time-out c ondition wi ll a lso ge nerate a n i nterrupt whi ch use s t he I2C i nterrrupt ve ctor. W hen an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Device Register After I2C Time-out BS83B04A-4 IICD, IICA, IICC0 No change IICC1 Reset to POR condition Others SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I2C Registers After Time-out The I2CT OF fl ag can be cleared by the application program. There are 64 time-out periods w hich can be selected using bits in the I2CTOC register. The time-out time is given by the formula: ((1~64) × 32)/fSUB This gives a range of about 1ms to 64ms. Note also that the LIRC oscillator is continuously enabled.

Rev. 1.61 96 April 11, 2017 Rev. 1.61 97 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Interrupts Interrupts are an important part of any microcontroller s ystem. When an external event or an internal function such as a T ouch Action or T imer/Event Counter overflow requires microcontroller attention, their corres ponding interrupt w ill enforce a temporary s uspension of the main program allowing the microcontroller to direct attention to their respective needs. The devices contain several external interrupt and internal interr upts functions. The external interru pt is generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the T ouch Keys, T imer/Event Counter, T ime Base, SIM etc. Interrupt Registers Overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the Special Purpose Data Memory , as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC1 registers which setup the primary interrupts, the second is the INTEG registers to setup the external interrupt trigger edge type. Each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/disable bit or “F” for request flag. Function Enable Bit Request Flag Notes Global EMI — — INT Pin INTE INTF — Touch Key Module TKME TKMF — SIM (except BS83B04A-4) SIME SIMF — I2C (BS33B04A-4) I2CE I2CF — EEPROM DEE DEF — Time Base TBE TBF — Timer/Event Counter TE TF — Interrupt Register Bit Naming Conventions Device Register Name Bit 7 6 5 4 3 2 1 0 BS83B04A-4 INTC1 — DEF TBF I2CF — DEE TBE I2CE Others INTC1 — DEF TBF SIMF — DEE TBE SIME All devices INTC0 — TF TKMF INTF TE TKME INTE EMI Interrupt Register List

Rev. 1.61 98 April 11, 2017 Rev. 1.61 99 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU INTEG Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 INTS1, INTS0: Defines INT interrupt active edge 00: Disabled interrupt 01: Rising Edge interrupt 10: Falling Edge interrupt 11: Dual Edge interrupt INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — TF TKMF INTF TE TKME INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TF: T imer/Event Counter interrupt request flag 0: No request 1: Interrupt request Bit 5 TKMF: T ouch key module interrupt request flag 0: No request 1: Interrupt request Bit 4 INTF: INT pin interrupt request flag 0: No request 1: Interrupt request Bit 3 TE: T imer/Event Counter interrupt control 0: Disable 1: Enable Bit 2 TKME: T ouch key module interrupt control 0: Disable 1: Enable Bit 1 INTE: INT pin interrupt control 0: Disable 1: Enable Bit 0 EMI: Global Interrupt control 0: Disable 1: Enable

Rev. 1.61 98 April 11, 2017 Rev. 1.61 99 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU INTC1 Register – BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name — DEF TBF I2CF — DEE TBE I2CE R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 5 TBF: T ime Base interrupt request flag 0: No request 1: Interrupt request Bit 4 I2CF: I2C interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2 DEE: Data EEPROM control 0: Disable 1: Enable Bit 1 TBE: T ime Base interrupt control 0: Disable 1: Enable Bit 0 I2CE: I2C interrupt control 0: Disable 1: Enable INTC1 Register – except BS83B04A-4 Bit 7 6 5 4 3 2 1 0 Name — DEF TBF SIMF — DEE TBE SIME R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 5 TBF: T ime Base interrupt request flag 0: No request 1: Interrupt request Bit 4 SIMF:SIM interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2 DEE: Data EEPROM control 0: Disable 1: Enable Bit 1 TBE: T ime Base interrupt control 0: Disable 1: Enable Bit 0 SIME: SIM interrupt control 0: Disable 1: Enable

Rev. 1.61 100 April 11, 2017 Rev. 1.61 101 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Interrupt Operation When the conditions for an interrupt event occur , such as a T ouch Key Counter overflow , Timer/Event Counter overflow , etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . The microcontroller will then fetch its next instruction from this interrupt vector . The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated w ith a “RETI”, w hich retrieves the original P rogram Counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . Some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically . This will prevent any further interrupt nesting from occurring. However, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. All o f t he i nterrupt r equest fla gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n SL EEP o r IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.

Rev. 1.61 100 April 11, 2017 Rev. 1.61 101 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 04H 14H 08H 0CH 10H Vector Low Priority HighRequest Flags Enable Bits Master Enable EMI auto disabled in ISR Interrupt Name EMI EMI EMI EMI EMIINTFExternal INTE TBFTime Base TBE TKMFTouch Key Module TKME TFTimer/Event Counter TE I2CFI2C I2CE xxF Legend Request Flag – no auto reset in ISR xxF Request Flag – auto reset in ISR xxE Enable Bit DEFEEPROM DEE EMI 18H Interrupt Structure(BS83B04A-4) 04H 14H 08H 0CH 10H Vector Low Priority HighRequest Flags Enable Bits Master Enable EMI auto disabled in ISR Interrupt Name EMI EMI EMI EMI EMIINTFExternal INTE TBFTime Base TBE TKMFTouch Key Module TKME TFTimer/Event Counter TE SIMFSIM SIME xxF Legend Request Flag – no auto reset in ISR xxF Request Flag – auto reset in ISR xxE Enable Bit DEFEEPROM DEE EMI 18H Interrupt Structure(except BS83B04A-4)

Rev. 1.61 102 April 11, 2017 Rev. 1.61 103 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU External Interrupt The e xternal i nterrupt is c ontrolled by si gnal t ransitions on t he pi n INT . An e xternal i nterrupt request will take place when the external interrupt request flag, INTF , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correc t i nterrupt edge t ype must be se lected usi ng t he INT EG regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, its can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register . When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Time Base Interrupt The function of the T ime Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its timer function. When this happens its interrupt request flags TBF will be set. T o allow the program to branch to its interrupt vector address, the global interrupt enable bit, EMI and T ime Base enable bit, TBE, must first be set. When the interrupt is enabled, the stack is not full and the T ime Base overflows, a subroutine call to its vector location will take place. When the interrupt is serviced, the interrupt request flag, TBF , will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the T ime Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source originate from the internal clock source fSYS or fSUB. This fTP input clock passes through a di vider, t he di vision ra tio of whi ch i s se lected by progra mming t he a ppropriate bi ts i n t he T BC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTP, which in turn controls the T ime Base interrupt period, can originate from several dif ferent sources, as shown in the System Operating Mode section. TBC Register Bit 7 6 5 4 3 2 1 0 Bit 7~6 Unimplemented, read as "0" Bit 5~4 TB1~TB0: Select T ime Base T ime-out Period 00: 1024/fTP 01: 2048/fTP 10: 4096/fTP 11: 8192/fTP Bit 3~0 Unimplemented, read as "0"

Rev. 1.61 102 April 11, 2017 Rev. 1.61 103 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU /G4D /G55 /G58 /G66 /G53/G59 /G53 /GB8 /G32/G20 /G20/G20 /G7E/G20 /G32 /G31/G30 /G31/G33 /G54/G69 /G6D/G65 /G20/G42 /G61/G73 /G65 /G54/G53 /G20/G42 /G69/G74 /G54/G42 /G31/G7E /G54/G42 /G30 /G66 /G54/G50 /G66 /G53/G55 /G42 /G30 /G31 Time Base Structure Timer/Event Counter Interrupt For a T imer/Event Counter interrupt to occur , the global interrupt enable bit, EM I, and the corresponding timer interrupt enable bit, TE, must first be set. An actual T imer/Event Counter interrupt will take place when the T imer/Event Counter request flag, TF , is set, a situation that will occur when the relevant T imer/Event Counter overflows. When the interrupt is enabled, the stack is not ful l and a T imer/Event Counte r n overfl ow oc curs, a subrouti ne c all t o t he relevant t imer interrupt vector , will take place. When the interrupt is serviced, the timer interrupt request flag, TF , will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM W rite cycle ends. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM W rite cycle ends, a subroutine call to the respective EEPROM Interrupt vect or, will take place. When the EEPROM Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. Touch Key Interrupt For a T ouch Key interrupt to occur , the global interrupt enable bit, EMI, and the corresponding Touch Key interru pt enable TKME must be first set. An actual T ouch Key interrupt will take place when the Touch Key request flag. TKMF , is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector , will take place. When the interrupt is serviced, the T ouch Key interrupt request flag, TKMF , will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. The TKCFOV flag, which is the 16-bit C/F counter overflow flag will go high when any of the Touch K ey M odule 16-bit C/F counter overfl ows. As this fl ag w ill not be automatically cleared, it has to be cleared by the application program. Module 0 only contains one 16-bit counter. The TK16OV flag, which is the 16-bit counter overflow flag will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. SIM Interrupt (except BS83B04A-4) A SIM In terrupt re quest wi ll t ake pl ace whe n t he SIM In terrupt re quest fla g, SIMF , i s se t, whi ch occurs when a byte of data has been received or transmitted by the SIM interface. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the st ack i s not full a nd a byt e of da ta ha s be en t ransmitted or re ceived by t he SIM i nterface, a subroutine call to the respective interrupt vector , will take place. When the Serial Interface Interrupt is service d, the SIM interrupt request flag, SIMF, will be automatically cleared and the EMI bit will

Rev. 1.61 104 April 11, 2017 Rev. 1.61 105 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU be automatically cleared to disable other interrupts. I2C Interrupt (BS83B04A-4) An I2C Interrupt request will take place when the I2C Interrupt request flag, I2CF , is set when the I2C time-out occurs, slave address matches or data byte transfer completes. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the I2C Interrupt enable bit, I2CE, must first be set. When the interrupt is enabled, the stack is not full and one of the I2C interrupt event occurs, a subroutine call to the respective Interrupt vector , will take place. When the Interrupt is service d, the interrupt request flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. Interrupt Wake-up Function Each of the int errupt funct ions has the capabi lity of waking up the mi crocontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt flag to be set high and consequent ly generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no ef fect on the interrupt wake-up function. Programming Considerations By di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately . If only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n SL EEP o r I DLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.

Rev. 1.61 104 April 11, 2017 Rev. 1.61 105 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Application Circuits VDD VSS VDD 0.1uF Key3 Key4 PAD PAD I2C Key1 Key2 PAD PAD I/O BS83B04A-4 I2C Device Control Device VDD VSS VDD 0.1uF Keyn-1 Keyn PAD PAD SPI/I2C I/O Key1 Key2 PAD PAD BS83B08A-3/BS83B08A-4 BS83B12A-3/BS83B12A-4 BS83B16A-3/BS83B16A-4 SPI/I2C Device Control Device Note: “*” It is recommended that this component is added for added ESD protection. “**” It is recommended that this component is added in environments where power line noise is significant.

Rev. 1.61 106 April 11, 2017 Rev. 1.61 107 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Instruction Set Instruction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. In the case of Holtekmicrocontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator , most instructions would be i mplemented wi thin 0.5 μs a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1us. Alt hough i nstructions whi ch re quire one m ore c ycle t o i mplement a re ge nerally l imited t o the JMP , CALL, RET , RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. E xamples of suc h i nstructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Ac cumulator. One of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. W ithin t he Hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified.

Rev. 1.61 106 April 11, 2017 Rev. 1.61 107 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within t he Hol tek m icrocontroller i nstruction se t. As wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he Ac cumulator wh ich m ay i nvolve a dditional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Dif ferent rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he Ca rry bit from where it can be examined and the necessary serial bit set high or low . Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping of f poi nt as in the case of the CALL instruct ion. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The abili ty to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers . This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively . The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data st orage i s norm ally i mplemented by usi ng re gisters. However , whe n worki ng wi th l arge amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory . T o overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HAL T” instruction for Power -down operations and instructions to control the operation of the W atchdog T imer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections.

Rev. 1.61 108 April 11, 2017 Rev. 1.61 109 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV ADD A,x Add immediate data to ACC 1 Z, C, AC, OV ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A,[m] Logical AND Data Memory to ACC 1 Z OR A,[m] Logical OR Data Memory to ACC 1 Z XOR A,[m] Logical XOR Data Memory to ACC 1 Z ANDM A,[m] Logical AND ACC to Data Memory 1Note Z ORM A,[m] Logical OR ACC to Data Memory 1Note Z XORM A,[m] Logical XOR ACC to Data Memory 1Note Z AND A,x Logical AND immediate Data to ACC 1 Z OR A,x Logical OR immediate Data to ACC 1 Z XOR A,x Logical XOR immediate Data to ACC 1 Z CPL [m] Complement Data Memory 1Note Z CPLA [m] Complement Data Memory with result in ACC 1 Z Increment & Decrement INCA [m] Increment Data Memory with result in ACC 1 Z INC [m] Increment Data Memory 1 Note Z DECA [m] Decrement Data Memory with result in ACC 1 Z DEC [m] Decrement Data Memory 1Note Z Rotate RRA [m] Rotate Data Memory right with result in ACC 1 None RR [m] Rotate Data Memory right 1Note None RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C RRC [m] Rotate Data Memory right through Carry 1Note C RLA [m] Rotate Data Memory left with result in ACC 1 None RL [m] Rotate Data Memory left 1Note None RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C RLC [m] Rotate Data Memory left through Carry 1Note C

Rev. 1.61 108 April 11, 2017 Rev. 1.61 109 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] Move Data Memory to ACC 1 None MOV [m],A Move ACC to Data Memory 1Note None MOV A,x Move immediate data to ACC 1 None Bit Operation CLR [m].i Clear bit of Data Memory 1Note None SET [m].i Set bit of Data Memory 1Note None Branch Operation JMP addr Jump unconditionally 2 None SZ [m] Skip if Data Memory is zero 1Note None SZA [m] Skip if Data Memory is zero with data movement to ACC 1Note None SZ [m].i Skip if bit i of Data Memory is zero 1Note None SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None SIZ [m] Skip if increment Data Memory is zero 1Note None SDZ [m] Skip if decrement Data Memory is zero 1Note None SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None CALL addr Subroutine call 2 None RET Return from subroutine 2 None RET A,x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD [m] Read table (specific page) to TBLH and Data Memory 2Note None TABRDC [m] Read table (current page) to TBLH and Data Memory 2Note None TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR [m] Clear Data Memory 1Note None SET [m] Set Data Memory 1Note None CLR WDT Clear Watchdog Timer 1 TO, PDF CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF SWAP [m] Swap nibbles of Data Memory 1Note None SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None HALT Enter power down mode 1 TO, PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the T O and PDF flags may be af fected by the execution sta tus. T he T O a nd PDF fl ags a re c leared a fter bot h “ CLR W DT1” a nd “ CLR W DT2” instructions are consecutively executed. Otherwise the T O and PDF flags remain unchanged.

Rev. 1.61 110 April 11, 2017 Rev. 1.61 111 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Instruction Definition ADC A,[m] Add D ata M emory to A CC w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C ADCM A,[m] Add A CC to D ata M emory w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C ADD A,[m] Add D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C ADD A,x Add im mediate data to A CC Description The c ontents o f t he A ccumulator a nd t he s pecified im mediate data a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + x Affected fl ag(s) OV, Z , A C, C ADDM A,[m] Add A CC to D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C AND A,[m] Logical A ND D ata M emory t o A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ [ m] Affected fl ag(s) Z AND A,x Logical A ND im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b it w ise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ x Affected fl ag(s) Z ANDM A,[m] Logical A ND A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ AND″ [ m] Affected fl ag(s) Z

Rev. 1.61 110 April 11, 2017 Rev. 1.61 111 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU CALL addr Subroutine c all Description Unconditionally c alls a s ubroutine a t t he s pecified a ddress. Th e P rogram C ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. T he sp ecified a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. A s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. Operation Stack ← P rogram Counter + 1 Program C ounter ← a ddr Affected fl ag(s) None CLR [m] Clear D ata M emory Description Each b it o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m] ← 00H Affected fl ag(s) None CLR [m].i Clear bi t o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m].i ← 0 Affected fl ag(s) None CLR WDT Clear W atchdog T imer Description The T O, P DF fl ags a nd t he W DT a re al l c leared. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CLR WDT1 Pre-clear W atchdog T imer Description The T O, P DF fl ags a nd t he W DT a re a ll c leared. N ote t hat t his instruction w orks in conjunction w ith C LR W DT2 a nd m ust b e e xecuted al ternately w ith C LR W DT2 to h ave effect. R epetitively e xecuting t his i nstruction w ithout al ternately e xecuting C LR W DT2 w ill have no e ffect. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CLR WDT2 Pre-clear W atchdog T imer Description The T O, P DF fl ags and t he W DT are all cleared. N ote t hat t his i nstruction w orks i n conjunction with C LR W DT1 a nd m ust b e e xecuted al ternately w ith C LR W DT1 to h ave e ffect. R epetitively e xecuting t his i nstruction w ithout al ternately e xecuting C LR W DT1 w ill h ave n o e ffect. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CPL [m] Complement D ata M emory Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Operation [m] ← [m] Affected fl ag(s) Z

Rev. 1.61 112 April 11, 2017 Rev. 1.61 113 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU CPLA [m] Complement D ata M emory w ith r esult i n A CC Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Th e c omplemented r esult i s s tored i n the A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] Affected fl ag(s) Z DAA [m] Decimal-Adjust A CC f or addition w ith r esult i n D ata M emory Description Convert t he c ontents o f t he A ccumulator v alue to a B CD ( Binary C oded D ecimal) v alue resulting f rom t he p revious a ddition o f t wo B CD v ariables. I f t he low n ibble is greater t han 9 or i f A C fl ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. O therwise t he l ow n ibble remains u nchanged. I f t he h igh n ibble i s g reater t han 9 o r i f t he C fl ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. E ssentially, t he decimal c onversion i s p erformed b y a dding 00H, 0 6H, 6 0H o r 6 6H depending o n t he A ccumulator a nd fl ag c onditions. O nly t he C fl ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal B CD s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. Operation [m] ← A CC + 00H or [m] ← A CC + 06 H o r [m] ← A CC + 60H o r [m] ← A CC + 66H Affected fl ag(s) C DEC [m] Decrement D ata M emory Description Data i n t he s pecified D ata M emory i s d ecremented b y 1 . Operation [m] ← [ m] − 1 Affected fl ag(s) Z DECA [m] Decrement D ata M emory wi th r esult i n A CC Description Data in t he sp ecified D ata M emory is d ecremented b y 1 . T he re sult is s tored in t he Accumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] − 1 Affected fl ag(s) Z HALT Enter p ower down m ode Description This i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. Th e c ontents o f the D ata M emory a nd r egisters a re r etained. Th e W DT a nd p rescaler a re c leared. Th e p ower down fl ag P DF i s s et a nd t he W DT t ime-out fl ag T O i s c leared. Operation TO ← 0 PDF ← 1 Affected fl ag(s) TO, P DF INC [m] Increment D ata M emory Description Data in t he sp ecified D ata M emory is incremented b y 1 . Operation [m] ← [ m] + 1 Affected fl ag(s) Z INCA [m] Increment D ata M emory wi th r esult i n A CC Description Data i n t he sp ecified D ata M emory i s i ncremented b y 1 . Th e re sult i s s tored i n t he A ccumulator. The c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] + 1 Affected fl ag(s) Z

Rev. 1.61 112 April 11, 2017 Rev. 1.61 113 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU JMP addr Jump u nconditionally Description The c ontents o f t he P rogram C ounter a re re placed w ith t he sp ecified a ddress. P rogram execution t hen c ontinues f rom t his n ew a ddress. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. Operation Program Counter ← addr Affected fl ag(s) None MOV A,[m] Move D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. Operation ACC ← [ m] Affected fl ag(s) None MOV A,x Move im mediate data to A CC Description The im mediate data s pecified i s l oaded i nto t he A ccumulator. Operation ACC ← x Affected fl ag(s) None MOV [m],A Move A CC to D ata M emory Description The c ontents o f t he A ccumulator a re c opied to t he s pecified D ata M emory. Operation [m] ← A CC Affected fl ag(s) None NOP No o peration Description No o peration i s p erformed. E xecution c ontinues w ith t he n ext i nstruction. Operation No operation Affected fl ag(s) None OR A,[m] Logical O R D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise logical O R op eration. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ [ m] Affected fl ag(s) Z OR A,x Logical OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical O R operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ x Affected fl ag(s) Z ORM A,[m] Logical OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical O R operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ OR″ [ m] Affected fl ag(s) Z RET Return from s ubroutine Description The P rogram C ounter is re stored f rom t he s tack. P rogram e xecution c ontinues a t t he re stored a ddress. Operation Program Counter ← S tack Affected fl ag(s) None

Rev. 1.61 114 April 11, 2017 Rev. 1.61 115 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU RET A,x Return f rom su broutine and l oad im mediate data to A CC Description The P rogram C ounter i s r estored f rom t he s tack a nd t he A ccumulator l oaded w ith t he s pecified immediate data. P rogram e xecution c ontinues a t t he r estored a ddress. Operation Program Counter ← S tack ACC ← x Affected fl ag(s) None RETI Return from i nterrupt Description The P rogram C ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he EMI b it. E MI i s t he m aster i nterrupt g lobal e nable b it. I f a n i nterrupt w as p ending w hen t he RETI instruction is e xecuted, t he p ending In terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. Operation Program Counter ← S tack EMI ← 1 Affected fl ag(s) None RL [m] Rotate D ata M emory l eft Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← [ m].7 Affected fl ag(s) None RLA [m] Rotate D ata M emory left w ith re sult in A CC Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← [ m].7 Affected fl ag(s) None RLC [m] Rotate D ata M emory l eft t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated l eft b y 1 b it. B it 7 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← C C ← [ m].7 Affected fl ag(s) C RLCA [m] Rotate D ata M emory left t hrough C arry w ith re sult in A CC Description Data i n t he s pecified D ata M emory and t he carry fl ag are r otated l eft b y 1 b it. B it 7 r eplaces t he Carry b it a nd t he o riginal c arry fl ag i s r otated i nto t he b it 0 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← C C ← [ m].7 Affected fl ag(s) C RR [m] Rotate D ata M emory r ight Description The contents of t he s pecified D ata M emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← [ m].0 Affected fl ag(s) None

Rev. 1.61 114 April 11, 2017 Rev. 1.61 115 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU RRA [m] Rotate D ata M emory right with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . Th e r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he Data M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← [ m].0 Affected fl ag(s) None RRC [m] Rotate D ata M emory r ight t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← C C ← [ m].0 Affected fl ag(s) C RRCA [m] Rotate D ata M emory right th rough C arry with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 r eplaces the C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← C C ← [ m].0 Affected fl ag(s) C SBC A,[m] Subtract D ata M emory from A CC wi th C arry Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C SBCM A,[m] Subtract D ata M emory from A CC wi th C arry a nd r esult i n D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he D ata M emory. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C SDZ [m] Skip i f decrement D ata M emory i s 0 Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] − 1 Skip if [ m]=0 Affected fl ag(s) None

Rev. 1.61 116 April 11, 2017 Rev. 1.61 117 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU SDZA [m] Skip i f decrement D ata M emory i s z ero w ith r esult i n A CC Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] − 1 Skip if A CC=0 Affected fl ag(s) None SET [m] Set D ata M emory Description Each b it o f t he s pecified D ata M emory i s s et t o 1 . Operation [m] ← F FH Affected fl ag(s) None SET [m].i Set b it o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s s et t o 1 . Operation [m].i ← 1 Affected fl ag(s) None SIZ [m] Skip i f i ncrement D ata M emory i s 0 Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] + 1 Skip if [ m]=0 Affected fl ag(s) None SIZA [m] Skip if increment D ata M emory is z ero w ith re sult in A CC Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] + 1 Skip if A CC=0 Affected fl ag(s) None SNZ [m].i Skip i f b it i of D ata M emory i s n ot 0 Description If b it i o f t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m].i ≠ 0 Affected fl ag(s) None SUB A,[m] Subtract D ata M emory from A CC Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C

Rev. 1.61 116 April 11, 2017 Rev. 1.61 117 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU SUBM A,[m] Subtract D ata M emory from A CC wi th r esult i n D ata M emory Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he D ata M emory. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C SUB A,x Subtract im mediate data f rom A CC Description The im mediate data s pecified b y t he c ode i s s ubtracted f rom t he c ontents o f t he A ccumulator. The re sult is s tored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C flag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − x Affected fl ag(s) OV, Z , A C, C SWAP [m] Swap ni bbles of D ata M emory Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Operation [m].3~[m].0 ↔ [ m].7~[m].4 Affected fl ag(s) None SWAPA [m] Swap ni bbles of D ata M emory w ith r esult i n A CC Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Th e result i s s tored i n t he A ccumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.3~ACC.0 ← [ m].7~[m].4 ACC.7~ACC.4 ← [ m].3~[m].0 Affected fl ag(s) None SZ [m] Skip i f D ata M emory i s 0 Description If t he contents of t he s pecified D ata M emory i s 0, t he following i nstruction i s s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m]=0 Affected fl ag(s) None SZA [m] Skip i f D ata M emory i s 0 w ith data m ovement to A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. I f t he v alue i s z ero, the f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] Skip if [ m]=0 Affected fl ag(s) None SZ [m].i Skip i f b it i of D ata M emory i s 0 Description If b it i o f t he sp ecified D ata M emory is 0 , t he f ollowing instruction is s kipped. A s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m].i=0 Affected fl ag(s) None

Rev. 1.61 118 April 11, 2017 Rev. 1.61 119 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU TABRD [m] Read ta ble ( specific p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( specific p age) a ddressed b y t he t able p ointer p air (TBHP a nd T BLP) i s mo ved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None TABRDC [m] Read ta ble ( current p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( TBLP) is moved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None TABRDL [m] Read t able (last p age) t o T BLH a nd D ata M emory Description The l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (TBLP) i s mo ved to t he s pecified D ata M emory a nd t he h igh b yte m oved to T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None XOR A,[m] Logical X OR D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ [ m] Affected fl ag(s) Z XORM A,[m] Logical X OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ XOR″ [ m] Affected fl ag(s) Z XOR A,x Logical X OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ x Affected fl ag(s) Z

Rev. 1.61 118 April 11, 2017 Rev. 1.61 119 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU

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The Operation Instruction of Packing Materials
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Rev. 1.61 120 April 11, 2017 Rev. 1.61 121 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 8-pin SOP (150mil) Outline Dimensions /G44 /G46 /G43/G27 /G47 /G48 /G61 /G45 /G38 /G31 /G41 /G42 /G43 /G34 /G35 Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.012 — 0.020 C′ — 0.193 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 6.00 BSC — B — 3.90 BSC — C 0.31 — 0.51 C′ — 4.90 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8°

Rev. 1.61 120 April 11, 2017 Rev. 1.61 121 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 10-pin MSOP Outline Dimensions /G41/G31 /G41 /G45/G31 /G65 /G42 /G41/G32 /G52/G20 /G30/G2E /G31/G30 /G28/G34 /G20/G43 /G4F/G52 /G4E/G45 /G52/G53 /G29 /G4C /G45 /G43 /G71 /G44 /G31 /G35 /G36 /G31/G30 /G4C/G31 Symbol Dimensions in inch Min. Nom. Max. A — — 0.043 A1 0.000 — 0.006 A2 0.030 0.033 0.037 B 0.007 — 0.013 C 0.003 — 0.009 D — 0.118 BSC — E — 0.193 BSC — E1 — 0.118 BSC — e — 0.020 BSC — L 0.016 0.024 0.031 L1 — 0.037 BSC — y — 0.004 — θ 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — — 1.10 A1 0.00 — 0.15 A2 0.75 0.85 0.95 B 0.17 — 0.33 C 0.08 — 0.23 D — 3.00 BSC — E — 4.90 BSC — E1 — 3.00 BSC — e — 0.50 BSC — L 0.40 0.60 0.80 L1 — 0.95 BSC — y — 0.10 — θ 0° — 8°

Rev. 1.61 122 April 11, 2017 Rev. 1.61 123 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 16-pin NSOP (150mil) Outline Dimensions /G31/G36 /G31 /G39 /G38 /G61 /G41 /G42 /G43 /G44 /G45 /G46 /G47 /G48 /G43/G27 Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.012 — 0.020 C' — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° ― 8° Symbol Dimensions in mm Min. Nom. Max. A — 6.00 BSC — B — 3.90 BSC — C 0.31 — 0.51 C' — 9.90 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° ― 8°

Rev. 1.61 122 April 11, 2017 Rev. 1.61 123 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 16-pin SSOP (150mil) Outline Dimensions /G31/G36 /G31 /G39 /G38 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.193 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 6.000 BSC — B — 3.900 BSC — C 0.20 — 0.30 C’ — 4.900 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8°

Rev. 1.61 124 April 11, 2017 Rev. 1.61 125 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 20-pin SOP (300mil) Outline Dimensions /G32/G30 /G31 /G31/G31 /G31/G30 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.504 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.50 BSC — C 0.31 — 0.51 C’ — 12.80 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8°

Rev. 1.61 124 April 11, 2017 Rev. 1.61 125 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 20-pin SSOP (150mil) Outline Dimensions /G32/G30 /G31 /G31/G31 /G31/G30 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.155 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.0098 G 0.016 — 0.05 H 0.004 — 0.01 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 6.000 BSC — B — 3.900 BSC — C 0.20 — 0.30 C’ — 8.660 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8°

Rev. 1.61 126 April 11, 2017 Rev. 1.61 127 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 24-pin SOP (300mil) Outline Dimensions /G32/G34 /G31 /G31/G33 /G31/G32 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.606 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.50 BSC — C 0.31 — 0.51 C’ — 15.40 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° ― 8°

Rev. 1.61 126 April 11, 2017 Rev. 1.61 127 April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU 24-pin SSOP (150mil) Outline Dimensions /G32/G34 /G31 /G31/G33 /G31/G32 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.341 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 6.000 BSC — B — 3.900 BSC — C 0.20 — 0.30 C’ — 8.660 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8°

Rev. 1.61 128 April 11, 2017 Rev. 1.61 PB April 11, 2017 BS83B08A-3/BS83B12A-3/BS83B16A-3 BS83B04A-4/BS83B08A-4/BS83B12A-4/BS83B16A-4 Touch Flash MCU Copyright© 2017 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.

Product Information

BS83B08A-4 specifications and overview.

Summary

Touch Flash MCU

Description

Touch Flash MCU

Source title BS83B08A-4 Datasheet(PDF) - Holtek Semiconductor Inc

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