Microcontroller

BS82B12A-3

Holtek Semiconductor In...

Touch Flash MCU with LED/LCD Driver December 15, 2016

Manufacturer: Holtek Semiconductor In...

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Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Revision: V1.60 Date: Deee 1 016Deee 1 016

Rev. 1.60 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Table of Contents

Rev. 1.60 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver

Rev. 1.60 4 Deee 1 016 Rev. 1.60 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver

Rev. 1.60 6 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver

Features

Operating voltage ♦ fSYS = 8MHz: VLVR~5.5V ♦ fSYS = 12MHz: 2.7V~5.5V ♦ fSYS = 16MHz: 4.5V~5.5V
Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
Power down and wake-up functions to reduce power consumption
Three Oscillators ♦ High Speed Internal RC -- HIRC: 8/12/16MHz ♦ Low Speed Internal RC -- LIRC: 32kHz ♦ Low speed External Crystal -- LXT: 32768Hz (only for BS82C16A-3 and BS82D20A-3)
Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
All instructions executed in one or two instruction cycles
Table read instructions
63 powerful instructions
Up to 8-level subroutine nesting
Bit manipulation instruction Peripheral Features
Flash Program Memory: 2K×16 ~ 8K×16
RAM Data Memory: 384×8 ~ 768×8
Ture EEPROM Memory: 64×8
Fully integrated 12/16/20 touch key functions -- require no external components
Watchdog T imer function
Up to 26 bidirectional I/O lines
PMOS Source Current Adjustable
Software controlled 4-SCOM lines LCD driver with 1/3 bias
One external interrupt line shared with I/O pin
Multiple T imer Module for time measure, input capture, compare match output, PWM output or single pulse output function
Dual T ime-Base functions for generation of fixed time interrupt signals
I2C Interface Module
UART Interface
Low voltage reset function
Low voltage detect function
Package: 20/24/28-pin SOP, 28-pin SSOP

Rev. 1.60 6 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver General Description These devices are a series of Flash Memory type 8-bit high performance RISC architecture microcontrollers with fully integrated touch key functions. W ith all touch key functions provided internally and with the convenience of Flash Memory multi-programming features, these devices has a ll the features to offer designers a reliable and easy m eans of i mplementing T ouch Keyes within their products applications. The t ouch ke y func tions a re ful ly i ntegrated c ompletely e liminating t he ne ed for e xternal components. In addition to the flash program memory , other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Protective features such as an internal W atchdog T imer, Low Voltage Reset and Low V oltage Detector functions coupled with excell ent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HIRC, LIRC and LXT oscillators are provided includ ing a fully intefrated system oscillator whi ch re quire no e xternal components fo r their i mplementation. T he a bility t o op erate and swi tch dy namically be tween a ra nge of op erating m odes usi ng di fferent c lock sourc es gi ves users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the fully integrated I2C interface functions, while t he i nclusion of fle xible I/ O pr ogramming fe atures, T imer Mod ules a nd m any ot her fe atures further enhance device functionality and flexibility. The UAR T module is contained in these devices. It can support the applications such as data communication networks between microcontrollers, low-cost data links between PCs and peripheral devices, portable and battery operated device communication, etc. These touch key devices will find excellent use in a huge range of modern T ouch Key product applications such as instrumentatio n, household appliances, electronic ally controlled tools to name but a few. Selection Table Most fe atures a re c ommon t o these de vices , the m ain features distinguishing them are Memory capacity, I/O count, LCD segment count, Touch Key count, stack capa city and package types. The following table summarises the main features of each device. Part No. VDD Program Memory Data Memory Data EEPROM I/O Ext. Int. LCD Driver Timer Module Touch Key I2C UART Time Base Stack Package BS8B1A-3 .7V~ .V K×16 384×8 64×8 1 16×4 10-it CTM×1 10-it PTM×1 1 √ √ 6 0/4SOP 4QFN BS8C16A-3 .7V~ .V 4K×16 1×8 64×8 6 1 0×4 10-it CTM×1 10-it PTM×1 16 √ √ 6 4/8SOP 3QFN BS8D0A-3 .7V~ .V 8K×16 768×8 64×8 6 1 0×4 10-it CTM×1 10-it PTM×1 0 √ √ 8 4/8SOP 8SSOP

Rev. 1.60 8 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Block Diagram 8-it RISC MCU Coe Tie Modules Flash Poga Meoy EEPROM Data Meoy Flash/EEPROM Pogaing Ciuity (ICP/OCDS) RAM Data Meoy Tie Bases Low Voltage Detet Wathdog Tie Inteupt Contolle Reset Ciuit LXT Osillato LED Dive LCD Dive Touh Keys HIRC/LIRC Osillatos Low Voltage Reset UARTICI/O Note: The LXT oscillator is only for the BS82C16A-3 and BS82D20A-3. Pin Assignment PA3/SDA/RX PA0/TCK1/SCOM/ICPDA/OCDSDA PA/SCOM3/ICPCK/OCDSCK PA7/SCL/TX VDD VSS PA1/SCOM0 PA4/INT/TCK0/SCOM1 PC/TP0_0/SSEG13 PC4/TP1_0/SSEG1 BS82B12A-3/BS82BV12A-3

20 SOP-A

PA0/TCK1/SCOM/ICPDA/OCDSDA BS82B12A-3/BS82BV12A-3

24 SOP-A

PC7/TP0_1/SSEG1 PC6/TP1_1/SSEG14 PC/TP0_0/SSEG13 PC4/TP1_0/SSEG1PC3/SSEG11/KEY1 PC/SSEG10/KEY11 PC1/SSEG9/KEY10 PC0/SSEG8/KEY9 PB7/SSEG7/KEY8 PB6/SSEG6/KEY7 PB/SSEG/KEY6 PB4/SSEG4/KEY PB3/SSEG3/KEY4 PB/SSEG/KEY3 PB1/SSEG1/KEY PB0/SSEG0/KEY1

Rev. 1.60 8 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver PA/SCOM3/ICPCK/OCDSCK PA0/TCK1/SCOM/ICPDA/OCDSDA PA3/SDA/RX PB0/SSEG0/KEY1 PB1/SSEG1/KEY PB/SSEG/KEY3 PC6/TP1_1/SSEG14 PC/TP0_0/SSEG13 PC4/TP1_0/SSEG1 PC3/SSEG11/KEY1 PC/SSEG10/KEY11 PC1/SSEG9/KEY10 PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/SSEG/KEY6 PB6/SSEG6/KEY7 PB7/SSEG7/KEY8 PC0/SSEG8/KEY9 PA7/SCL/TX VDD VSS PA1/SCOM0 PA4/INT/TCK0/SCOM1 PC7/TP0_1/SSEG1 BS82B12A-3 BS82BV12A-3

24 QFN-A

PA0/TCK1/SCOM/ICPDA/OCDSDA BS82C16A-3/BS82CV16A-3 PC7/TP0_1/SSEG1/KEY16 PC6/TP1_1/SSEG14/KEY1 PC/SSEG13/KEY14 PC4/SSEG1/KEY13 PC3/SSEG11/KEY1 PC/SSEG10/KEY11 PC1/SSEG9/KEY10 PC0/SSEG8/KEY9 PB7/SSEG7/KEY8 PB6/SSEG6/KEY7 PB/SSEG/KEY6 PB4/SSEG4/KEY PB3/SSEG3/KEY4 PB/SSEG/KEY3 PB1/SSEG1/KEY PB0/SSEG0/KEY1

28 SOP-A

PC7/TP0_1/SSEG1/KEY16 PC6/TP1_1/SSEG14/KEY1 PC/SSEG13/KEY14 PC4/SSEG1/KEY13 PD1/TP0_0/SSEG17/XT PD0/TP1_0/SSEG16/XT1 PC3/SSEG11/KEY1 PC/SSEG10/KEY11 PC1/SSEG9/KEY10 PC0/SSEG8/KEY9 PB7/SSEG7/KEY8 PB6/SSEG6/KEY7 PB/SSEG/KEY6 PB4/SSEG4/KEY PB3/SSEG3/KEY4 PB/SSEG/KEY3 PB1/SSEG1/KEY PB0/SSEG0/KEY1 PD/SSEG18 PD3/SSEG19 PA/SCOM3/ICPCK/OCDSCK PA0/TCK1/SCOM/ICPDA/OCDSDA PA3/SDA/RX NC NC PB0/SSEG0/KEY1 PB1/SSEG1/KEY PB/SSEG/KEY3 PC6/TP1_1/SSEG14/KEY1 PC/SSEG13/KEY14 PC4/SSEG1/KEY13 NC NC PC3/SSEG11/KEY1 PC/SSEG10/KEY11 PC1/SSEG9/KEY10 PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/SSEG/KEY6 PB6/SSEG6/KEY7 PB7/SSEG7/KEY8 PD3/SSEG19 PD/SSEG18 PC0/SSEG8/KEY9 PA7/SCL/TX VDD PD1/TP0_0/SSEG17/XT PD0/TP1_0/SSEG16/XT1 VSS PA1/SCOM0 PA4/INT/TCK0/SCOM1 PC7/TP0_1/SSEG1/KEY16 BS82C16A-3 BS82CV16A-3

32 QFN-A

Rev. 1.60 10 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver PA3/SDA/RX PA0/TCK1/SCOM/ICPDA/OCDSDA BS82D20A-3/BS82DV20A-3 PC7/TP0_1/SSEG1/KEY18 PC6/TP1_1/SSEG14/KEY17 PC/SSEG13/KEY16 PC4/SSEG1/KEY1PC3/SSEG11/KEY14 PC/SSEG10/KEY13 PC1/SSEG9/KEY1 PC0/SSEG8/KEY11 PB7/SSEG7/KEY8 PB6/SSEG6/KEY7 PB/SSEG/KEY6 PB4/SSEG4/KEY PB3/SSEG3/KEY4 PB/SSEG/KEY3 PB1/SSEG1/KEY PB0/SSEG0/KEY1 PA3/SDA/RX PA0/TCK1/SCOM/ICPDA/OCDSDA BS82D20A-3/BS82DV20A-3

28 SOP-A/SSOP-A

PC7/TP0_1/SSEG1/KEY18 PC6/TP1_1/SSEG14/KEY17 PC/SSEG13/KEY16 PC4/SSEG1/KEY1PC3/SSEG11/KEY14 PC/SSEG10/KEY13 PC1/SSEG9/KEY1 PC0/SSEG8/KEY11 PB7/SSEG7/KEY8 PB6/SSEG6/KEY7 PB/SSEG/KEY6 PB4/SSEG4/KEY PB3/SSEG3/KEY4 PB/SSEG/KEY3 PB1/SSEG1/KEY PB0/SSEG0/KEY1 PD1/TP0_0/SSEG17/XT PD0/TP1_0/SSEG16/XT1 PD/SSEG18/KEY10 PD3/SSEG19/KEY9 Note: 1. If the pin-shared pin functi ons have multiple outputs simultaneously , its pin names at the right side of the "/" sign can be used for higher priority. 2. T he OCDSDA a nd OCDSCK pins a re t he OCDS de dicated pins a nd onl y a vailable for t he BS82BV12A-3, B S82CV16A-3 a nd B S82DV20A-3 d evices, wh ich a re t he OC DS E V c hips f or t he BS82B12A-3, BS82C16A-3 and BS82D20A-3 devices respectively.

Rev. 1.60 1 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their Port name, e.g. P A0, P A1, etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the T ouch Key function, T imer Modules, etc. The function of each pin is listed in the following tables, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. BS82B12A-3 Pin Name Function OP I/T O/T Description PA0/TCK1/ SCOM/ ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. TCK1 PTM0C0 ST — PTM0 lok input SCOM SLCDC0 — SCOM LCD dive output fo LCD panel oon ICPDA — ST CMOS In-iuit pogaing addess/data pin OCDSDA — ST CMOS On-hip deug suppot data/addess pin fo EV hip only. PA1/SCOM0 PA1 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM0 SLCDC0 — SCOM LCD dive output fo LCD panel oon PA/ SCOM3/ ICPCK/ OCDSCK PA PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM3 SLCDC0 — SCOM LCD dive output fo LCD panel oon ICPCK — ST — In-iuit pogaing lok pin OCDSCK — ST — On-hip deug suppot lok pin fo EV hip only. PA3/SDA/ RX PA3 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDA IICC0 ST NMOS IC Data RX UCR1 ST — UART eeive data input PA4/INT/ TCK0/ SCOM1 PA4 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. INT INTC0 INTEG ST — Extenal inteupt TCK0 CTM0C0 ST — CTM0 lok input SCOM1 SLCDC0 — SCOM LCD dive output fo LCD panel oon PA7/SCL/TX PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCL IICC0 ST NMOS IC Clok TX UCR1 — CMOS UART tansitte data output PB0/ SSEG0/ KEY1 PB0 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG0 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY1 TKM0C1 NSI — Touh key input PB1/ SSEG1/ KEY PB1 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY TKM0C1 NSI — Touh key input

Rev. 1.60 1 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Name Function OP I/T O/T Description PB/ SSEG/ KEY3 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY3 TKM0C1 NSI — Touh key input PB3/ SSEG3/ KEY4 PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY4 TKM0C1 NSI — Touh key input PB4/ SSEG4/ KEY PB4 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG4 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY TKM1C1 NSI — Touh key input PB/ SSEG/ KEY6 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY6 TKM1C1 NSI — Touh key input PB6/ SSEG6/ KEY7 PB6 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG6 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY7 TKM1C1 NSI — Touh key input PB7/ SSEG7/ KEY8 PB7 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG7 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY8 TKM1C1 NSI — Touh key input PC0/ SSEG8/ KEY9 PC0 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG8 SLCDC — CMOS LCD dive output fo LCD panel segent KEY9 TKMC1 NSI — Touh key input PC1/ SSEG9/ KEY10 PC1 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG9 SLCDC — CMOS LCD dive output fo LCD panel segent KEY10 TKMC1 NSI — Touh key input PC/ SSEG10/ KEY11 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG10 SLCDC — CMOS LCD dive output fo LCD panel segent KEY11 TKMC1 NSI — Touh key input PC3/ SSEG11/ KEY1 PC3 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG11 SLCDC — CMOS LCD dive output fo LCD panel segent KEY1 TKMC1 NSI — Touh key input PC4/TP1_0/ SSEG1 PC4 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP1_0 TMPC — CMOS PTM0 output SSEG1 SLCDC — CMOS LCD dive output fo LCD panel segent PC/TP0_0/ SSEG13 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP0_0 TMPC — CMOS CTM0 output SSEG13 SLCDC — CMOS LCD dive output fo LCD panel segent PC6/TP1_1/ SSEG14 PC6 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP1_1 TMPC — CMOS PTM0 output SSEG14 SLCDC — CMOS LCD dive output fo LCD panel segent PC7/TP0_1/ SSEG1 PC7 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP0_1 TMPC — CMOS CTM0 output SSEG1 SLCDC — CMOS LCD dive output fo LCD panel segent

Rev. 1.60 14 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Name Function OP I/T O/T Description VDD VDD — PWR — Powe supply VSS VSS — PWR — Gound Note: I/T: Input type; O/T : Output type OP: Optional by configuration option (CO) or register selection PWR: Power; ST: Schmitt T rigger input CMOS: CMOS output; NMOS : NMOS output; SCOM: SCOM output AN: Analog input; NSI: Non-standard input The PTM pin names and output pin control bits use "1" as their serial number , but other PTM related regiter names or bit names use "0". BS82C16A-3 Pin Name Function OP I/T O/T Description PA0/TCK1/ SCOM/ ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. TCK1 PTM0C0 ST — PTM0 lok input SCOM SLCDC0 — SCOM LCD dive output fo LCD panel oon ICPDA — ST CMOS In-iuit pogaing addess/data pin OCDSDA — ST CMOS On-hip deug suppot data/addess pin fo EV hip only. PA1/SCOM0 PA1 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM0 SLCDC0 — SCOM LCD dive output fo LCD panel oon PA/ SCOM3/ ICPCK/ OCDSCK PA PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM3 SLCDC0 — SCOM LCD dive output fo LCD panel oon ICPCK — ST — In-iuit pogaing lok pin OCDSCK — ST — On-hip deug suppot lok pin fo EV hip only. PA3/SDA/ RX PA3 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDA IICC0 ST NMOS IC Data RX UCR1 ST — UART eeive data input PA4/INT/ TCK0/ SCOM1 PA4 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. INT INTC0 INTEG ST — Extenal inteupt TCK0 CTM0C0 ST — CTM0 lok input SCOM1 SLCDC0 — SCOM LCD dive output fo LCD panel oon PA7/SCL/TX PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCL IICC0 ST NMOS IC Clok TX UCR1 — CMOS UART tansitte data output PB0/ SSEG0/ KEY1 PB0 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG0 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY1 TKM0C1 NSI — Touh key input PB1/ SSEG1/ KEY PB1 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY TKM0C1 NSI — Touh key input

Rev. 1.60 14 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Name Function OP I/T O/T Description PB/ SSEG/ KEY3 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY3 TKM0C1 NSI — Touh key input PB3/ SSEG3/ KEY4 PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY4 TKM0C1 NSI — Touh key input PB4/ SSEG4/ KEY PB4 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG4 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY TKM1C1 NSI — Touh key input PB/ SSEG/ KEY6 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY6 TKM1C1 NSI — Touh key input PB6/ SSEG6/ KEY7 PB6 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG6 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY7 TKM1C1 NSI — Touh key input PB7/ SSEG7/ KEY8 PB7 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG7 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY8 TKM1C1 NSI — Touh key input PC0/ SSEG8/ KEY9 PC0 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG8 SLCDC — CMOS LCD dive output fo LCD panel segent KEY9 TKMC1 NSI — Touh key input PC1/ SSEG9/ KEY10 PC1 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG9 SLCDC — CMOS LCD dive output fo LCD panel segent KEY10 TKMC1 NSI — Touh key input PC/ SSEG10/ KEY11 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG10 SLCDC — CMOS LCD dive output fo LCD panel segent KEY11 TKMC1 NSI — Touh key input PC3/ SSEG11/ KEY1 PC3 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG11 SLCDC — CMOS LCD dive output fo LCD panel segent KEY1 TKMC1 NSI — Touh key input PC4/ SSEG1/ KEY13 PC4 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC — CMOS LCD dive output fo LCD panel segent KEY13 TKM3C1 NSI — Touh key input PC/ SSEG13/ KEY14 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG13 SLCDC — CMOS LCD dive output fo LCD panel segent KEY14 TKM3C1 NSI — Touh key input PC6/TP1_1/ SSEG14/ KEY1 PC6 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP1_1 TMPC — CMOS PTM0 output SSEG14 SLCDC — CMOS LCD dive output fo LCD panel segent KEY1 TKM3C1 NSI — Touh key input

Rev. 1.60 16 Deee 1 016 Rev. 1.60 17 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Name Function OP I/T O/T Description PC7/TP0_1/ SSEG1/ KEY16 PC7 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP0_1 TMPC — CMOS CTM0 output SSEG1 SLCDC — CMOS LCD dive output fo LCD panel segent KEY16 TKM3C1 NSI — Touh key input PD0/TP1_0/ SSEG16/ XT1 PD0 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP1_0 TMPC — CMOS PTM0 output SSEG16 SLCDC3 — CMOS LCD dive output fo LCD panel segent XT1 CO LXT — LXT pin PD1/TP0_0/ SSEG17/ XT PD1 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP0_0 TMPC — CMOS CTM0 output SSEG17 SLCDC3 — CMOS LCD dive output fo LCD panel segent XT CO — LXT LXT pin PD/ SSEG18 PD PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG18 SLCDC3 — CMOS LCD dive output fo LCD panel segent PD3/ SSEG19 PD3 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG19 SLCDC3 — CMOS LCD dive output fo LCD panel segent VDD VDD — PWR — Powe supply VSS VSS — PWR — Gound Note: I/T: Input type; O/T : Output type; OP: Optional by configuration option (CO) or register selection; PWR: Power; ST: Schmitt T rigger input; C MOS: CMOS output; NMOS: NMOS output; SCOM: SCOM output; AN: Analog input; NSI: Non-standard input; LXT: Low frequency crystal oscillator; The PTM pin names and output pin control bits use "1" as their serial number , but other PTM related regiter names or bit names use "0". BS82D20A-3 Pin Name Function OP I/T O/T Description PA0/TCK1/ SCOM/ ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. TCK1 PTM0C0 ST — PTM0 lok input SCOM SLCDC0 — SCOM LCD dive output fo LCD panel oon ICPDA — ST CMOS In-iuit pogaing addess/data pin OCDSDA — ST CMOS On-hip deug suppot data/addess pin fo EV hip only. PA1/ SCOM0/ KEY0 PA1 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM0 SLCDC0 — SCOM LCD dive output fo LCD panel oon KEY0 TKM4C1 NSI — Touh key input PA/ SCOM3/ ICPCK/ OCDSCK PA PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM3 SLCDC0 — SCOM LCD dive output fo LCD panel oon ICPCK — ST — In-iuit pogaing lok pin OCDSCK — ST — On-hip deug suppot lok pin fo EV hip only.

Rev. 1.60 16 Deee 1 016 Rev. 1.60 17 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Name Function OP I/T O/T Description PA3/SDA/RX PA3 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDA IICC0 ST NMOS IC Data RX UCR1 ST — UART eeive data input PA4/INT/ TCK0/ SCOM1/ KEY19 PA4 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. INT INTC0 INTEG ST — Extenal inteupt TCK0 CTM0C0 ST — CTM0 lok input SCOM1 SLCDC0 — SCOM LCD dive output fo LCD panel oon KEY19 TKM4C1 NSI — Touh key input PA7/SCL/TX PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCL IICC0 ST NMOS IC Clok TX UCR1 — CMOS UART tansitte data output PB0/SSEG0/ KEY1 PB0 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG0 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY1 TKM0C1 NSI — Touh key input PB1/SSEG1/ KEY PB1 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY TKM0C1 NSI — Touh key input PB/SSEG/ KEY3 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY3 TKM0C1 NSI — Touh key input PB3/SSEG3/ KEY4 PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY4 TKM0C1 NSI — Touh key input PB4/SSEG4/ KEY PB4 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG4 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY TKM1C1 NSI — Touh key input PB/SSEG/ KEY6 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY6 TKM1C1 NSI — Touh key input PB6/SSEG6/ KEY7 PB6 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG6 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY7 TKM1C1 NSI — Touh key input PB7/SSEG7/ KEY8 PB7 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG7 SLCDC1 — CMOS LCD dive output fo LCD panel segent KEY8 TKM1C1 NSI — Touh key input PC0/SSEG8/ KEY11 PC0 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG8 SLCDC — CMOS LCD dive output fo LCD panel segent KEY11 TKMC1 NSI — Touh key input PC1/SSEG9/ KEY1 PC1 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG9 SLCDC — CMOS LCD dive output fo LCD panel segent KEY1 TKMC1 NSI — Touh key input

Rev. 1.60 18 Deee 1 016 Rev. 1.60 19 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pin Name Function OP I/T O/T Description PC/ SSEG10/ KEY13 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG10 SLCDC — CMOS LCD dive output fo LCD panel segent KEY13 TKMC1 NSI — Touh key input PC3/ SSEG11/ KEY14 PC3 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG11 SLCDC — CMOS LCD dive output fo LCD panel segent KEY14 TKM3C1 NSI — Touh key input PC4/ SSEG1/ KEY1 PC4 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC — CMOS LCD dive output fo LCD panel segent KEY1 TKM3C1 NSI — Touh key input PC/ SSEG13/ KEY16 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG13 SLCDC — CMOS LCD dive output fo LCD panel segent KEY16 TKM3C1 NSI — Touh key input PC6/TP1_1/ SSEG14/ KEY17 PC6 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP1_1 TMPC — CMOS PTM0 output SSEG14 SLCDC — CMOS LCD dive output fo LCD panel segent KEY17 TKM4C1 NSI — Touh key input PC7/TP0_1/ SSEG1/ KEY18 PC7 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP0_1 TMPC — CMOS CTM0 output SSEG1 SLCDC — CMOS LCD dive output fo LCD panel segent KEY18 TKM4C1 NSI — Touh key input PD0/TP1_0/ SSEG16/ XT1 PD0 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP1_0 TMPC — CMOS PTM0 output SSEG16 SLCDC3 — CMOS LCD dive output fo LCD panel segent XT1 CO LXT — LXT pin PD1/TP0_0/ SSEG17/ XT PD1 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. TP0_0 TMPC — CMOS CTM0 output SSEG17 SLCDC3 — CMOS LCD dive output fo LCD panel segent XT CO — LXT LXT pin PD/ SSEG18/ KEY10 PD PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG18 SLCDC3 — CMOS LCD dive output fo LCD panel segent KEY10 TKMC1 NSI — Touh key input PD3/ SSEG19/ KEY9 PD3 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG19 SLCDC3 — CMOS LCD dive output fo LCD panel segent KEY9 TKMC1 NSI — Touh key input VDD VDD — PWR — Powe supply VSS VSS — PWR — Gound Note: I/T: Input type; O/T : Output type OP: Optional by configuration option (CO) or register selection PWR: Power; ST: Schmitt T rigger input CMOS: CMOS output; NMOS : NMOS output AN: Analog input; NSI: Non-standard input; SCOM: SCOM output LXT: Low frequency crystal oscillator The PTM pin names and output pin control bits use "1" as their serial number , but other PTM related regiter names or bit names use "0".

Rev. 1.60 18 Deee 1 016 Rev. 1.60 19 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Absolute Maximum Ratings Note: T hese a re st ress ra tings onl y. St resses e xceeding t he ra nge spe cified und er "Absol ute Ma ximum Ratings" m ay c ause su bstantial d amage t o t hese d evices. Fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cification i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. D.C. Characteristics Ta=°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VDD Opeating Voltage (HIRC) — fSYS = 8MHz .7 — . V fSYS = 1MHz .7 — . V fSYS = 16MHz 4. — . V IDD Opeating Cuent (Noal) (HIRC fSYS=fH fS=fSUB) 3V No load fH = 8MHz WDT enale — 1. 1.8 A V — . 3.3 A 3V No load fH = 1MHz WDT enale — 1.6 .4 A V — 3.3 .0 A V No load fH = 16MHz WDT enale — 4.0 6.0 A Opeating Cuent (Noal) (HIRC fSYS=fL fS=fSUB) 3V No load fH =1MHz fL= fH/ WDT enale — 1. .0 A V — . 3.3 A 3V No load fH =1MHz fL= fH/4 WDT enale — 1.0 1. A V — 1.8 .7 A 3V No load fH =1MHz fL= fH/8 WDT enale — 0.9 1.4 A V — 1.6 .4 A 3V No load fH =1MHz fL= fH/16 WDT enale — 0.8 1. A V — 1. .3 A 3V No load fH =1MHz fL= fH/3 WDT enale — 0.8 1. A V — 1. .3 A V No load fH =1MHz fL= fH/64 WDT enale — 0.8 1. A 3V — 1. .3 A Opeating Cuent (Slow) (LXT/LIRC fSYS=fL fS=fSUB) 3V No load fSYS=LXT WDT enale LXTLP=0 — 19 38 μA V — 48 96 μA 3V No load fSYS=LXT WDT enale LXTLP=1 — 16 3 μA V — 36 7 μA 3V No load fSYS=LIRC WDT enale — 10 0 μA V — 30 0 μA

Rev. 1.60 0 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions ISTB IDLE1 Mode Standy Cuent (HIRC fSYS=fH fS=fSUB) 3V No load syste HALT WDT enale fSYS = 1MHz — 0.9 1.4 A V — 1.4 .1 A IDLE0 Mode Standy Cuent (HIRC fSYS=off fS=fSUB) 3V No load syste HALT WDT enale fSYS = 1MHz — 1.4 3.0 μA V — .7 .0 μA IDLE1 Mode Standy Cuent (HIRC fSYS= fL fS=fSUB) 3V No load syste HALT WDT enale fSYS = 1MHz/64 — 0.7 1.1 A V — 1.4 .1 A IDLE0 Mode Standy Cuent (HIRC fSYS=off fS=fSUB) 3V No load syste HALT WDT enale fSYS = 1MHz/64 — 1.3 3.0 μA V — .3 .0 μA IDLE1 Mode Standy Cuent (LIRC fSYS=fL=fLIRC fS=fSUB=fLIRC) 3V No load syste HALT WDT enale fSYS = LIRC — 1.9 4.0 μA V — 3.3 7.0 μA IDLE0 Mode Standy Cuent (LXT/LIRC fSYS=off fS=fSUB) 3V No load syste HALT WDT enale LXTLP=0 (LXT on) — 10 μA V — 18 30 μA 3V No load syste HALT WDT enale LXTLP=1 (LXT on) — . μA V — 6 10 μA 3V No load syste HALT WDT enale (LIRC on) — 1.3 3.0 μA V — .4 .0 μA SLEEP Mode Standy Cuent (HIRC fSYS=off fS=fSUB=off) 3V No load syste HALT WDT disale (LXT and LIRC off) — 0.1 1 μA V — 0.3 μA SLEEP Mode Standy Cuent (LXT/LIRC fSYS=off fS=fSUB=off) 3V No load syste HALT WDT disale (LXT and LIRC off) — 0.1 1 μA V — 0.3 μA VIL Input Low Voltage fo I/O Pots o Input Pins V 0 — 1. V — 0 — 0.VDD V VIH Input High Voltage fo I/O Pots o Input Pins V 3. — .0 V — 0.8VDD — VDD V VLVR Low Voltage Reset Voltage — LVR enale .V -% . +% V VLVD Low Voltage Deteto Voltage — LVDEN = 1 VLVD = .7V -% .7 +% V LVDEN = 1 VLVD = 3.0V -% 3.0 +% V LVDEN = 1 VLVD = 3.3V -% 3.3 +% V LVDEN = 1 VLVD = 3.6V -% 3.6 +% V LVDEN = 1 VLVD = 4.0V -% 4.0 +% V IOL I/O Pot Sink Cuent 3V VOL=0.1VDD 16 3 — A V VOL=0.1VDD 3 64 — A IOH I/O Pot Soue Cuent 3V VOH = 0.9VDD PxPS=00 -1.0 -.0 — A V VOH = 0.9VDD PxPS=00 -.0 -4.0 — A 3V VOH = 0.9VDD PxPS=01 -1.7 -3. — A V VOH = 0.9VDD PxPS=01 -3. -7.0 — A 3V VOH = 0.9VDD PxPS=10 -. -.0 — A V VOH = 0.9VDD PxPS=10 -.0 -10 — A 3V VOH = 0.9VDD PxPS=11 -. -11 — A V VOH = 0.9VDD PxPS=11 -11 - — A

Rev. 1.60 0 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions RPH Pull-high Resistane fo I/O Pots 3V — 0 60 100 kΩ V — 10 30 0 kΩ VBG Bandgap Refeene with Buffe Voltage — — -3% 1.09 +3% V A.C. Characteristics Ta=°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS Syste Clok (HIRC) 3V/V Ta=°C -% 8 +% MHz -% 1 +% MHz V -% 16 +% MHz tTIMER Tie Input Pulse Width — — 0.3 — — μs fLIRC Syste Clok (3kHz) V Ta=°C -10% 3 +10% kHz fLXT Syste Clok (LXT) — — — 3768 — Hz tINT Inteupt Pulse Width — — 1 10 μs tLVR Low Voltage Width to Reset — — 10 40 480 μs tLVD Low Voltage Width to Inteupt — — 60 10 40 μs tLVDS LVDO stale tie — — — — 1 μs tEERD EEPROM Read Tie — — 1 4 tSYS tEEWR EEPROM W ite Ti e — — 1 4 s tRSTD Syste Reset Delay Tie (Powe on eset LVR eset WDT S/W eset (WDTC)) — — 0 100 s Syste Reset Delay Tie (WDT noal eset) — — 8.3 16.7 33.3 s tSST Syste Stat-up Tie Peiod (Wake-up fo HALT) — fSYS=LXT 104 — — tSYS fSYS=HIRC 16 — — fSYS=LIRC — — Syste Stat-up Tie Peiod (Wake-up fo HALT fSYS on at HALT state) — — — — Note: tSYS = 1/fSYS

Rev. 1.60 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Sensor Oscillator Electrical Characteristics Ta=°C Touch Key RC OSC = 500kHz Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Condition IKEYOSC Only Senso (KEY) Osillato Opeating Cuent *fSENOSC=00kHz MnFILEN=0 — 30 60 μA V — 60 10 *fSENOSC=00kHz MnFILEN=1 — 40 80 μA V — 80 160 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC=00kHz MnTSS=0 MnFILEN=0 — 30 60 μA V — 60 10 3V *fREFOSC=00kHz MnTSS=0 MnFILEN=1 — 30 60 μA V — 60 10 3V *fREFOSC=00kHz MnTSS=1 MnFILEN=0 — 30 60 μA V — 60 10 3V *fREFOSC=00kHz MnTSS=1 MnFILEN=1 — 40 80 μA V — 80 160 CKEYOSC Senso (KEY) Osillato Extenal Capaitane V *fSENOSC=00kHz 10 0 pF CREFOSC Refeene Osillato Intenal Capaitane V *fSENOSC=00kHz 10 0 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny V *Extenal Capaitane =7891011113141 … 0pF 100 00 1000 kHz fREFYOSC Refeene Osillato Opeating Fequeny V *Intenal Capaitane =7891011113141 … 0pF 100 00 1000 kHz Note: *fSENOSC=500kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =500kHz. *fREFOSC=500kHz: adjust t he Re ference Osc illator internal c apacitor t o m ake t he Re ference Osc illator frequency =500kHz.

Rev. 1.60 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Touch Key RC OSC = 1000kHz Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Condition IKEYOSC Only Senso (KEY) Osillato Opeating Cuent *fSENOSC=1000kHz MnFILEN=0 — 40 80 μA V — 80 160 *fSENOSC=1000kHz MnFILEN=1 — 60 10 μA V — 100 00 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC=1000kHz MnTSS=0 MnFILEN=0 — 40 80 μA V — 80 160 3V *fREFOSC=1000kHz MnTSS=0 MnFILEN=1 — 40 80 μA V — 80 160 3V *fREFOSC=1000kHz MnTSS=1 MnFILEN=0 — 40 80 μA V — 80 160 3V *fREFOSC=1000kHz MnTSS=1 MnFILEN=1 — 60 10 μA V — 10 300 CKEYOSC Senso (KEY) Osillato Extenal Capaitane V *fSENOSC=1000kHz 10 0 pF CREFOSC Refeene Osillato Intenal Capaitane V *fSENOSC=1000kHz 10 0 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny V *Extenal Capaitane =13467891011113141 … 0pF 10 1000 00 kHz fREFYOSC Refeene Osillato Opeating Fequeny V *Intenal Capaitane =13467891011113141 … 0pF 10 1000 00 kHz Note: *fSENOSC=1000kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =1000kHz. *fREFOSC=1000kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =1000kHz.

Rev. 1.60 4 Deee 1 016 Rev. 1.60 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Touch Key RC OSC =1500kHz Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Condition IKEYOSC Only Senso (KEY) Osillato Opeating Cuent *fSENOSC=100kHz MnFILEN=0 — 60 10 μA V — 10 40 *fSENOSC=100kHz MnFILEN=1 — 90 180 μA V — 10 300 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC=100kHz MnTSS=0 MnFILEN=0 — 60 10 μA V — 10 40 3V *fREFOSC=100kHz MnTSS=0 MnFILEN=1 — 60 10 μA V — 10 40 3V *fREFOSC=100kHz MnTSS=1 MnFILEN=0 — 60 10 μA V — 10 40 3V *fREFOSC=100kHz MnTSS=1 MnFILEN=1 — 90 180 μA V — 40 CKEYOSC Senso (KEY) Osillato Extenal Capaitane *fSENOSC=100kHz 4 8 16 pF V 10 0 CREFOSC Refeene Osillato Intenal Capaitane *fSENOSC=100kHz 4 8 16 pF V 10 0 fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V *Extenal Capaitane =13467891011113141 … 0pF 10 100 3000 kHz V 10 100 3000 fREFYOSC Refeene Osillato Opeating Fequeny 3V *Intenal Capaitane =13467891011113141 … 0pF 10 100 3000 kHz V 10 100 3000 Note: *fSENOSC=1500kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =1500kHz. *fREFOSC=1500kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =1500kHz.

Rev. 1.60 4 Deee 1 016 Rev. 1.60 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Touch Key RC OSC =2000kHz Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Condition IKEYOSC Only Senso (KEY) Osillato Opeating Cuent *fSENOSC=000kHz MnFILEN=0 — 80 160 μA V — 160 30 *fSENOSC=000kHz MnFILEN=1 — 10 40 μA V — 00 400 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC=000kHz MnTSS=0 MnFILEN=0 — 80 160 μA V — 160 30 3V *fREFOSC=000kHz MnTSS=0 MnFILEN=1 — 80 160 μA V — 160 30 3V *fREFOSC=000kHz MnTSS=1 MnFILEN=0 — 80 160 μA V — 160 30 3V *fREFOSC=000kHz MnTSS=1 MnFILEN=1 — 10 40 μA V — 300 600 CKEYOSC Senso (KEY) Osillato Extenal Capaitane *fSENOSC=000kHz 4 8 16 pF V 10 0 CREFOSC Refeene Osillato Intenal Capaitane *fSENOSC=000kHz 4 8 16 pF V 10 0 fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V *Extenal Capaitane =13467891011113141 … 0pF 10 000 4000 kHz V 10 000 4000 fREFYOSC Refeene Osillato Opeating Fequeny 3V *Intenal Capaitane =13467891011113141 … 0pF 10 000 4000 kHz V 10 000 4000 Note: *fSENOSC=2000kHz: adjust the KEYn capacitor to make the Sensor Oscillator frequency =2000kHz. *fREFOSC=2000kHz: adjust the Reference Oscillator internal capacitor to make the Reference Oscillator frequency =2000kHz Power-on Reset Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VPOR VDD Stat Voltage to eEnsue Powe-on Reset — — — — 100 V RRVDD VDD Raising Rate to Ensue Powe-on Reset — — 0.03 — — V/s tPOR Miniu Tie fo VDD Stays at VPOR to Ensue Powe-on Reset — — 1 — — s /G54/G69 /G6D/G65 /G56 /G44/G44 /G56 /G50/G4F /G52 /G52/G52 /G56/G44 /G44 /G74 /G50/G4F /G52

Rev. 1.60 6 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver System Architecture A key factor in the high-performan ce features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantag e of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. An 8-bi t wi de AL U i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the D ata M emory and can be directly or indirectly addressed. The simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum relia bility and flexibility . This makes these devices suitable for low- cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way , one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G28 /G50/G43 /G29 /G45/G78 /G65/G63 /G75/G74 /G65 /G20/G49/G6E /G73/G74 /G2E/G20 /G28/G50 /G43/G2D /G31/G29 /G46/G65 /G74/G63 /G68/G20 /G49/G6E /G73/G74 /G2E/G20/G28 /G50/G43 /G2B/G31 /G29 /G45/G78 /G65/G63 /G75/G74 /G65 /G20/G49/G6E /G73/G74 /G2E/G20 /G28/G50 /G43/G29 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73 /G74/G2E/G20 /G28/G50 /G43/G2B /G32/G29 /G45/G78 /G65/G63 /G75/G74 /G65/G20 /G49/G6E /G73/G74 /G2E/G20 /G28/G50 /G43/G2B /G31/G29 /G50/G43 /G50/G43 /G2B/G31 /G50/G43 /G2B/G32 /G4F /G73/G63/G69 /G6C/G6C /G61/G74 /G6F/G72 /G20/G43 /G6C/G6F /G63/G6B /G28/G53 /G79/G73/G74 /G65/G6D /G20/G43 /G6C/G6F /G63/G6B/G29 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G31 /G50/G72 /G6F/G67 /G72/G61 /G6D/G20 /G43 /G6F/G75/G6E /G74/G65 /G72 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G32 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G33 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G34 /G50/G69 /G70/G65/G6C /G69/G6E /G69/G6E /G67 System Clock and Pipelining

Rev. 1.60 6 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle t o first obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20 /G31/G45 /G78/G65 /G63/G75 /G74/G65 /G20/G49 /G6E/G73 /G74/G2E/G20/G31 /G46/G65 /G74/G63 /G68/G20 /G49/G6E /G73/G74 /G2E/G20/G32 /G46/G6C /G75/G73 /G68/G20 /G50/G69 /G70/G65/G6C /G69/G6E /G65 /G31 /G32 /G33 /G34 /G35 /G36 /G44/G45 /G4C/G41 /G59/G3A /G4D/G4F /G56/G20 /G41/G2C /G5B/G31 /G32/G48 /G5D /G43/G41 /G4C/G4C /G20/G44 /G45/G4C /G41/G59 /G43/G50 /G4C/G20 /G5B /G31/G32/G48 /G5D /G3A /G3A /G4E/G4F /G50 /G45/G78 /G65/G63 /G75/G74 /G65/G20 /G49/G6E /G73/G74 /G2E/G20 /G32 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G33 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G36 /G45/G78 /G65/G63 /G75/G74 /G65/G20 /G49/G6E /G73 /G74/G2E/G20/G36 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G37 Instruction Fetching Program Counter During pro gram e xecution, t he Progr am Co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. It is automatically incremented by one each time an instruction is e xecuted e xcept for i nstructions, suc h a s "JMP" or "CAL L" t hat de mand a j ump t o a non- consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the Program Counter . For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High Byte PCL Register BS8B1A-3 PC10~PC8 PCL7~PCL0BS8C16A-3 PC11~PC8 BS8D0A-3 PC1~PC8 The lower byte of the Program Counter , known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register . By transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch.

Rev. 1.60 8 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer , and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily . However , when the stack is full, a CALL subroutine instruction can still be exec uted whic h wi ll result in a st ack overflow . Prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. If the stack is overflow , the first Program Counter save in the stack will be lost. /G50/G72 /G6F/G67 /G72/G61 /G6D/G20 /G43/G6F /G75/G6E /G74/G65 /G72 /G53/G74 /G61/G63 /G6B/G20 /G4C/G65 /G76/G65 /G6C/G20 /G31 /G53/G74 /G61/G63 /G6B/G20 /G4C/G65 /G76/G65 /G6C/G20 /G32 /G50/G72 /G6F/G67 /G72/G61 /G6D /G4D/G65 /G6D/G6F /G72/G79 /G54 /G6F/G70/G20 /G6F /G66/G20/G53 /G74/G61 /G63/G6B /G53/G74 /G61/G63 /G6B /G50/G6F /G69/G6E /G74/G65 /G72 /G42/G6F /G74/G74 /G6F/G6D /G20/G6F /G66/G20 /G53/G74 /G61/G63 /G6B /G53/G74 /G61/G63 /G6B/G20 /G4C/G65 /G76/G65 /G6C/G20 /G4E Device Stack Levels BS8B1A-3 6 BS8C16A-3 6 BS8D0A-3 8 Arithmetic and Logic Unit – ALU The arith metic-logic unit or ALU is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. Connected to the main micro controller data bus, the ALU receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register . As these ALU calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:

Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
Increment and Decrement: INCA, INC, DECA, DEC
Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Rev. 1.60 8 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. By using the appropriate programming tools, these Flash device s of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. Structure The Program Memory has a capacity of 2K×16 bits to 8K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, tabl e informati on and interrupt entries. Table data, which can be setup in any location within the Program Memory , is addressed by a separate table pointer register. Device Capacity BS8B1A-3 K×16 BS8C16A-3 4K×16 BS8D0A-3 8K×16 0000H 0004H 07FFH 0FFFH Reset Inteupt Veto 16 its Reset Inteupt Veto 16 its1FFFH BS8C16A-3 BS8D0A-3 Reset Inteupt Veto 16 its BS8B1A-3 0030H Program Memory Structure

Rev. 1.60 30 Deee 1 016 Rev. 1.60 31 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Special Vectors Within the Program Memory , certai n locations are reserved for the reset and interrupts. The location 0000H i s reserved for use by t he de vice re set for progra m i nitialisation. Aft er a de vice re set i s initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. T o use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register , TBLP and TBHP . These registers define the total address of the look-up table. After setting up the table pointer pair, the table data can be retrieved from the Program Memory using t he "T ABRD[m]" or "T ABRDL[m]" i nstructions respectively. W hen t he i nstruction i s executed, the low er order table byte from the Program Memory will be transferred to the user defined Data Memory regis ter [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register . Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G20/G54 /G42/G4C /G48 /G55/G73 /G65/G72 /G20/G53 /G65/G6C /G65/G63 /G74/G65 /G64 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G48/G69 /G67/G68 /G20/G42 /G79/G74 /G65/G4C /G6F/G77 /G20/G42 /G79/G74 /G65 /G54/G42 /G4C/G50 /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G44/G61 /G74/G61 /G41/G64 /G64/G72 /G65/G73 /G73 /G31/G36 /G20/G62 /G69/G74 /G73 /G50/G72 /G6F/G67 /G72/G61 /G6D/G20 /G4D/G65 /G6D/G6F /G72/G79 /G4C/G61/G73 /G74/G20/G70 /G61/G67/G65 /G20/G6F /G72 /G54/G42 /G48/G50 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "0700H" which refers to the start address of the last page within the 2K words Program Memory of the BS82B12A-3. The table pointer is setup here to have an init ial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0706H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the specific page if the "T ABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "T ABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be res tored, care s hould be taken to ensure its protection if both the main routine and Interrupt S ervice Routine us e table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

Rev. 1.60 30 Deee 1 016 Rev. 1.60 31 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a tabrd tempreg1 ; transfers value in table referenced by table pointer, ; data at program memory address "0706H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer, ; data at program memory address "F05H" transferred to tempreg2 and TBLH ; in this example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 org 07 00h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades a nd m odifications t o t heir p rograms o n t he sa me d evice. As a n a dditional c onvenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to W riter Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins Function ICPDA PA0 Seial data/addess input/output ICPCK PA Seial Clok input VDD VDD Powe Supply VSS VSS Gound The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire inte rface. Dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. T wo a dditional l ines a re re quired for t he powe r suppl y. T he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.

Rev. 1.60 3 Deee 1 016 Rev. 1.60 33 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver During the programming process the P A0 and P A2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. /G2A /G2A /G57/G72 /G69/G74 /G65/G72 /G5F/G56 /G44/G44 /G49/G43 /G50/G44 /G41 /G49/G43 /G50/G43 /G4B /G57/G72 /G69/G74 /G65/G72 /G5F/G56 /G53/G53 /G54/G6F /G20/G6F /G74/G68 /G65/G72 /G20/G43 /G69/G72 /G63/G75 /G69/G74 /G50/G41/G30 /G50/G41/G32 /G56/G53 /G53 /G56/G44 /G44 /G57/G72 /G69/G74 /G65/G72 /G20/G43 /G6F/G6E/G6E/G65 /G63/G74 /G6F/G72 /G53/G69 /G67/G6E/G61/G6C /G73 /G4D/G43 /G55/G20 /G50/G72 /G6F/G67 /G72/G61 /G6D/G6D /G69/G6E /G67 /G50/G69 /G6E/G73 Note: * may be resistor or capacito r. The resistance of * must be great er than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There are three EV chips named BS82BV12A-3, BS82CV16A-3 and BS82D V20A-3 which are used to emulate the B S82B12A-3, B S82C16A-3 a nd B S82D20A-3 d evices r espectively. E ach E V chip device also provides an "On-Chip Debug" function to debug the corresponding MCU device during t he de velopment proc ess. T he E V c hip a nd t he a ctual MCU de vice a re a lmost func tionally compatible except for the "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT - IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no e ffect i n t he E V c hip. Howe ver, t he t wo OCDS pi ns whi ch a re pi n-shared wi th t he ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-hip Deug Suppot Data/Addess input/output OCDSCK OCDSCK On-hip Deug Suppot Clok input VDD VDD Powe Supply GND VSS Gound

Rev. 1.60 3 Deee 1 016 Rev. 1.60 33 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two types, the first of these is an area of RAM, known as the Special Function Data Memory. He re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. Ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory , which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks for the devices. The Special Purpose Data M emory regis ters addressed from 00H ~7FH in D ata M emory are common and accessible in all banks, with the exception of the EEC register at address 40H which is only accessible in Bank 1. Switching betwee n the dif ferent Data Memory sectors is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Memory Type Device Capacity Speial Funtion Data Meoy BS8B1A-3 Bank 0~: 00H~7FH EEC egiste at 40H only aessile in Bank 1 BS8C16A-3 Bank 0~3: 00H~7FH EEC egiste at 40H only aessile in Bank 1 BS8D0A-3 Bank 0~: 00H~7FH EEC egiste at 40H only aessile in Bank 1 Geneal pupose Data Meoy BS8B1A-3 384×8 Bank 0: 80H~FFH Bank 1: 80H~FFH Bank : 80H~FFH BS8C16A-3 1×8 Bank 0: 80H~FFH Bank 1: 80H~FFH Bank : 80H~FFH Bank 3: 80H~FFH BS8D0A-3 768×8 Bank 0: 80H~FFH Bank 1: 80H~FFH Bank : 80H~FFH Bank 3: 80H~FFH Bank 4: 80H~FFH Bank : 80H~FFH Data Memory Sturcture Speial Funtion Data Meoy Geneal Pupose Data Meoy 00H 7FH 80H FFH 40H in Bank 1 Bank 0 Bank 1 EEC Bank N N= fo BS8B1A-3; N=3 fo BS8C16A-3; N= fo BS8D0A-3 Data Memory Structure

Rev. 1.60 34 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G30/G30 /G48 /G30/G31 /G48 /G30/G32 /G48 /G30/G33 /G48 /G30/G34 /G48 /G30/G35 /G48 /G30/G36 /G48 /G30/G37 /G48 /G30/G38 /G48 /G30/G39 /G48 /G30/G41 /G48 /G30/G42 /G48 /G30/G43 /G48 /G30/G44 /G48 /G30/G45 /G48 /G30/G46 /G48 /G31/G30 /G48 /G31/G31 /G48 /G31/G32 /G48 /G31/G33 /G48 /G31/G34 /G48 /G31/G35 /G48 /G31/G36 /G48 /G31/G37 /G48 /G31/G38 /G48 /G31/G39 /G48 /G31/G41 /G48 /G31/G42 /G48 /G31/G43 /G48 /G31/G44 /G48 /G31/G45 /G48 /G31/G46 /G48 /G32/G30 /G48 /G32/G31 /G48 /G32/G32 /G48 /G32/G33 /G48 /G32/G34 /G48 /G32/G35 /G48 /G32/G36 /G48 /G32/G37 /G48 /G32/G38 /G48 /G32/G39 /G48 /G32/G41 /G48 /G32/G42 /G48 /G32/G43 /G48 /G32/G44 /G48 /G32/G45 /G48 /G32/G46 /G48 /G33/G30 /G48 /G33/G31 /G48 /G33/G32 /G48 /G33/G33 /G48 /G33/G34 /G48 /G33/G35 /G48 /G33/G36 /G48 /G33/G37 /G48 /G33/G38 /G48 /G33/G39 /G48 /G33/G41 /G48 /G33/G42 /G48 /G33/G43 /G48 /G33/G44 /G48 /G33/G45 /G48 /G33/G46 /G48 /G49/G41 /G52/G30 /G4D/G50 /G30 /G49/G41 /G52/G31 /G4D/G50 /G31 /G42/G50 /G41/G43 /G43 /G50/G43 /G4C /G54/G42 /G4C/G50 /G54/G42 /G4C/G48 /G54/G42 /G48/G50 /G53/G54 /G41/G54 /G55/G53 /G53/G4D /G4F/G44 /G55/G6E /G75/G73 /G65/G64 /G49/G4E /G54/G45 /G47 /G49/G4E /G54/G43 /G30 /G49/G4E /G54/G43 /G31 /G49/G4E /G54/G43 /G32 /G49/G4E /G54/G43 /G33 /G4C/G56 /G44/G43 /G55/G6E /G75/G73 /G65/G64 /G50/G41 /G50/G41 /G43 /G50/G41/G50 /G55 /G50/G41/G57 /G55 /G53/G4C /G45/G44 /G43/G30 /G53/G4C /G45/G44 /G43/G31 /G57/G44 /G54/G43 /G54/G42 /G43 /G50/G53 /G43/G52 /G55/G6E /G75/G73 /G65/G64 /G45/G45 /G41 /G45/G45 /G44 /G50/G42 /G50/G42 /G43 /G50/G42/G50 /G55 /G49/G32 /G43/G54 /G4F/G43 /G49/G49/G43 /G43/G30 /G49/G49/G43 /G43/G31 /G49/G49 /G43/G44 /G49/G49/G43 /G41 /G55/G53 /G52 /G55/G43/G52/G31 /G55/G43/G52/G32 /G42/G52 /G47 /G54/G58 /G52/G5F /G52/G58 /G52 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G54/G4D /G50/G43 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G53/G4C /G43/G44/G43 /G30 /G53/G4C /G43/G44/G43 /G31 /G53/G4C /G43/G44/G43 /G32 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G50/G43 /G50/G43 /G43 /G50/G43 /G50/G55 /G55/G6E /G75/G73 /G65/G64 /G43/G54 /G52/G4C /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G34/G30 /G48 /G34/G31 /G48 /G34/G32 /G48 /G34/G33 /G48 /G34/G34 /G48 /G34/G35 /G48 /G34/G36 /G48 /G34/G37 /G48 /G34/G38 /G48 /G34/G39 /G48 /G34/G41 /G48 /G34/G42 /G48 /G34/G43 /G48 /G34/G44 /G48 /G34/G45 /G48 /G34/G46 /G48 /G35/G30 /G48 /G35/G31 /G48 /G35/G32 /G48 /G35/G33 /G48 /G35/G34 /G48 /G35/G35 /G48 /G35/G36 /G48 /G35/G37 /G48 /G35/G38 /G48 /G35/G39 /G48 /G35/G41 /G48 /G35/G42 /G48 /G35/G43 /G48 /G35/G44 /G48 /G35/G45 /G48 /G35/G46 /G48 /G36/G30 /G48 /G36/G31 /G48 /G36/G32 /G48 /G36/G33 /G48 /G36/G34 /G48 /G36/G35 /G48 /G36/G36 /G48 /G36/G37 /G48 /G36/G38 /G48 /G36/G39 /G48 /G36/G41 /G48 /G36/G42 /G48 /G36/G43 /G48 /G36/G44 /G48 /G36/G45 /G48 /G36/G46 /G48 /G37/G46 /G48 /G42/G61 /G6E/G6B /G20/G30 /G7E/G32 /G42/G61 /G6E/G6B /G20/G30 /G2C/G32 /G42/G61 /G6E/G6B /G20/G31 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G54/G4B /G54/G4D /G52 /G54/G4B /G43/G30 /G54/G4B /G31/G36 /G44/G4C /G54/G4B /G31/G36 /G44/G48 /G54/G4B /G43/G31 /G54/G4B /G4D/G30 /G31/G36 /G44/G4C /G54/G4B /G4D/G30 /G31/G36 /G44/G48 /G54/G4B /G4D/G30 /G52/G4F /G4C /G54/G4B /G4D/G30 /G52/G4F /G48 /G54/G4B /G4D/G30 /G43/G30 /G54/G4B /G4D/G30 /G43/G31 /G54/G4B /G4D/G31 /G31/G36 /G44/G4C /G54/G4B /G4D/G31 /G31/G36 /G44/G48 /G54/G4B /G4D/G31 /G52/G4F /G4C /G54/G4B /G4D/G31 /G52/G4F /G48 /G54/G4B /G4D/G31 /G43/G30 /G54/G4B /G4D/G31 /G43/G31 /G54/G4B /G4D/G32 /G31/G36 /G44/G4C /G54/G4B /G4D/G32 /G31/G36 /G44/G48 /G54/G4B /G4D/G32 /G52/G4F /G4C /G54/G4B /G4D/G32 /G52/G4F /G48 /G54/G4B /G4D/G32 /G43/G30 /G54/G4B /G4D/G32 /G43/G31 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G43/G54 /G4D/G30 /G43/G30 /G43/G54 /G4D/G30 /G43/G31 /G43/G54 /G4D/G30 /G44/G4C /G43/G54 /G4D/G30 /G44/G48 /G43/G54 /G4D/G30 /G41/G4C /G43/G54 /G4D/G30 /G41/G48 /G50/G54 /G4D/G30 /G43/G30 /G50/G54 /G4D/G30 /G43/G31 /G50/G54 /G4D/G30 /G44/G4C /G50/G54 /G4D/G30 /G44/G48 /G50/G54 /G4D/G30 /G41/G4C /G50/G54 /G4D/G30 /G41/G48 /G50/G54 /G4D/G30 /G52/G50 /G4C /G50/G54 /G4D/G30 /G52/G50 /G48 /G55/G6E /G75/G73 /G65/G64 /G20 /G45/G45 /G43/G20 /G42/G53 /G38/G32/G42 /G31/G32 /G41/G2D /G33/G20 /G53/G70 /G65/G63 /G69/G61 /G6C/G20 /G50/G75 /G72/G70 /G6F/G73 /G65/G20 /G44/G61 /G74/G61 /G20/G4D /G65/G6D /G6F/G72 /G79 /G20/G20/G20/G20/G20/G20/G20/G20/G20

Rev. 1.60 34 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G30/G30 /G48 /G30/G31 /G48 /G30/G32 /G48 /G30/G33 /G48 /G30/G34 /G48 /G30/G35 /G48 /G30/G36 /G48 /G30/G37 /G48 /G30/G38 /G48 /G30/G39 /G48 /G30/G41 /G48 /G30/G42 /G48 /G30/G43 /G48 /G30/G44 /G48 /G30/G45 /G48 /G30/G46 /G48 /G31/G30 /G48 /G31/G31 /G48 /G31/G32 /G48 /G31/G33 /G48 /G31/G34 /G48 /G31/G35 /G48 /G31/G36 /G48 /G31/G37 /G48 /G31/G38 /G48 /G31/G39 /G48 /G31/G41 /G48 /G31/G42 /G48 /G31/G43 /G48 /G31/G44 /G48 /G31/G45 /G48 /G31/G46 /G48 /G32/G30 /G48 /G32/G31 /G48 /G32/G32 /G48 /G32/G33 /G48 /G32/G34 /G48 /G32/G35 /G48 /G32/G36 /G48 /G32/G37 /G48 /G32/G38 /G48 /G32/G39 /G48 /G32/G41 /G48 /G32/G42 /G48 /G32/G43 /G48 /G32/G44 /G48 /G32/G45 /G48 /G32/G46 /G48 /G33/G30 /G48 /G33/G31 /G48 /G33/G32 /G48 /G33/G33 /G48 /G33/G34 /G48 /G33/G35 /G48 /G33/G36 /G48 /G33/G37 /G48 /G33/G38 /G48 /G33/G39 /G48 /G33/G41 /G48 /G33/G42 /G48 /G33/G43 /G48 /G33/G44 /G48 /G33/G45 /G48 /G33/G46 /G48 /G49/G41 /G52/G30 /G4D/G50 /G30 /G49/G41 /G52/G31 /G4D/G50 /G31 /G42/G50 /G41/G43 /G43 /G50/G43 /G4C /G54/G42 /G4C/G50 /G54/G42 /G4C/G48 /G54/G42 /G48/G50 /G53/G54 /G41/G54 /G55/G53 /G53/G4D /G4F/G44 /G55/G6E /G75/G73 /G65/G64 /G49/G4E /G54/G45 /G47 /G49/G4E /G54/G43 /G30 /G49/G4E /G54/G43 /G31 /G49/G4E /G54/G43 /G32 /G49/G4E /G54/G43 /G33 /G4C/G56 /G44/G43 /G55/G6E /G75/G73 /G65/G64 /G50/G41 /G50/G41 /G43 /G50/G41/G50 /G55 /G50/G41/G57 /G55 /G53/G4C /G45/G44 /G43/G30 /G53/G4C /G45/G44 /G43/G31 /G57/G44 /G54/G43 /G54/G42 /G43 /G50/G53 /G43/G52 /G55/G6E /G75/G73 /G65/G64 /G45/G45 /G41 /G45/G45 /G44 /G50/G42 /G50/G42 /G43 /G50/G42/G50 /G55 /G49/G32 /G43/G54 /G4F/G43 /G49/G49/G43 /G43/G30 /G49/G49/G43 /G43/G31 /G49/G49 /G43/G44 /G49/G49/G43 /G41 /G55/G53 /G52 /G55/G43/G52/G31 /G55/G43/G52/G32 /G42/G52 /G47 /G54/G58 /G52/G5F /G52/G58 /G52 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G54/G4D /G50/G43 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G53/G4C /G43/G44/G43 /G30 /G53/G4C /G43/G44/G43 /G31 /G53/G4C /G43/G44/G43 /G32 /G53/G4C /G43/G44/G43 /G33 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G50/G43 /G50/G43 /G43 /G50/G43 /G50/G55 /G55/G6E /G75/G73 /G65/G64 /G43/G54 /G52/G4C /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G34/G30 /G48 /G34/G31 /G48 /G34/G32 /G48 /G34/G33 /G48 /G34/G34 /G48 /G34/G35 /G48 /G34/G36 /G48 /G34/G37 /G48 /G34/G38 /G48 /G34/G39 /G48 /G34/G41 /G48 /G34/G42 /G48 /G34/G43 /G48 /G34/G44 /G48 /G34/G45 /G48 /G34/G46 /G48 /G35/G30 /G48 /G35/G31 /G48 /G35/G32 /G48 /G35/G33 /G48 /G35/G34 /G48 /G35/G35 /G48 /G35/G36 /G48 /G35/G37 /G48 /G35/G38 /G48 /G35/G39 /G48 /G35/G41 /G48 /G35/G42 /G48 /G35/G43 /G48 /G35/G44 /G48 /G35/G45 /G48 /G35/G46 /G48 /G36/G30 /G48 /G36/G31 /G48 /G36/G32 /G48 /G36/G33 /G48 /G36/G34 /G48 /G36/G35 /G48 /G36/G36 /G48 /G36/G37 /G48 /G36/G38 /G48 /G36/G39 /G48 /G36/G41 /G48 /G36/G42 /G48 /G36/G43 /G48 /G36/G44 /G48 /G36/G45 /G48 /G36/G46 /G48 /G37/G46 /G48 /G42/G61 /G6E/G6B /G20/G30 /G7E/G33 /G42/G61 /G6E/G6B /G20/G30 /G2C/G32 /G7E/G33 /G42/G61 /G6E/G6B /G20/G31 /G50/G44 /G50/G44 /G43 /G50/G44 /G50/G55 /G54/G4B /G54/G4D /G52 /G54/G4B /G43/G30 /G54/G4B /G31/G36 /G44/G4C /G54/G4B /G31/G36 /G44/G48 /G54/G4B /G43/G31 /G54/G4B /G4D/G30 /G31/G36 /G44/G4C /G54/G4B /G4D/G30 /G31/G36 /G44/G48 /G54/G4B /G4D/G30 /G52/G4F /G4C /G54/G4B /G4D/G30 /G52/G4F /G48 /G54/G4B /G4D/G30 /G43/G30 /G54/G4B /G4D/G30 /G43/G31 /G54/G4B /G4D/G31 /G31/G36 /G44/G4C /G54/G4B /G4D/G31 /G31/G36 /G44/G48 /G54/G4B /G4D/G31 /G52/G4F /G4C /G54/G4B /G4D/G31 /G52/G4F /G48 /G54/G4B /G4D/G31 /G43/G30 /G54/G4B /G4D/G31 /G43/G31 /G54/G4B /G4D/G32 /G31/G36 /G44/G4C /G54/G4B /G4D/G32 /G31/G36 /G44/G48 /G54/G4B /G4D/G32 /G52/G4F /G4C /G54/G4B /G4D/G32 /G52/G4F /G48 /G54/G4B /G4D/G32 /G43/G30 /G54/G4B /G4D/G32 /G43/G31 /G54/G4B /G4D/G33 /G31/G36 /G44/G4C /G54/G4B /G4D/G33 /G31/G36 /G44/G48 /G54/G4B /G4D/G33 /G52/G4F /G4C /G54/G4B /G4D/G33 /G52/G4F /G48 /G54/G4B /G4D/G33 /G43/G30 /G54/G4B /G4D/G33 /G43/G31 /G43/G54 /G4D/G30 /G43/G30 /G43/G54 /G4D/G30 /G43/G31 /G43/G54 /G4D/G30 /G44/G4C /G43/G54 /G4D/G30 /G44/G48 /G43/G54 /G4D/G30 /G41/G4C /G43/G54 /G4D/G30 /G41/G48 /G50/G54 /G4D/G30 /G43/G30 /G50/G54 /G4D/G30 /G43/G31 /G50/G54 /G4D/G30 /G44/G4C /G50/G54 /G4D/G30 /G44/G48 /G50/G54 /G4D/G30 /G41/G4C /G50/G54 /G4D/G30 /G41/G48 /G50/G54 /G4D/G30 /G52/G50 /G4C /G50/G54 /G4D/G30 /G52/G50 /G48 /G55/G6E /G75/G73 /G65/G64 /G20 /G45/G45 /G43/G20 /G42/G53 /G38/G32/G43 /G31/G36 /G41/G2D /G33/G20 /G53 /G70/G65/G63 /G69/G61 /G6C/G20 /G50/G75 /G72/G70 /G6F/G73 /G65/G20 /G44/G61 /G74/G61 /G20/G4D /G65/G6D /G6F/G72 /G79 /G20/G20/G20/G20/G20/G20/G20/G20/G20

Rev. 1.60 36 Deee 1 016 Rev. 1.60 37 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G30/G30 /G48 /G30/G31 /G48 /G30/G32 /G48 /G30/G33 /G48 /G30/G34 /G48 /G30/G35 /G48 /G30/G36 /G48 /G30/G37 /G48 /G30/G38 /G48 /G30/G39 /G48 /G30/G41 /G48 /G30/G42 /G48 /G30/G43 /G48 /G30/G44 /G48 /G30/G45 /G48 /G30/G46 /G48 /G31/G30 /G48 /G31/G31 /G48 /G31/G32 /G48 /G31/G33 /G48 /G31/G34 /G48 /G31/G35 /G48 /G31/G36 /G48 /G31/G37 /G48 /G31/G38 /G48 /G31/G39 /G48 /G31/G41 /G48 /G31/G42 /G48 /G31/G43 /G48 /G31/G44 /G48 /G31/G45 /G48 /G31/G46 /G48 /G32/G30 /G48 /G32/G31 /G48 /G32/G32 /G48 /G32/G33 /G48 /G32/G34 /G48 /G32/G35 /G48 /G32/G36 /G48 /G32/G37 /G48 /G32/G38 /G48 /G32/G39 /G48 /G32/G41 /G48 /G32/G42 /G48 /G32/G43 /G48 /G32/G44 /G48 /G32/G45 /G48 /G32/G46 /G48 /G33/G30 /G48 /G33/G31 /G48 /G33/G32 /G48 /G33/G33 /G48 /G33/G34 /G48 /G33/G35 /G48 /G33/G36 /G48 /G33/G37 /G48 /G33/G38 /G48 /G33/G39 /G48 /G33/G41 /G48 /G33/G42 /G48 /G33/G43 /G48 /G33/G44 /G48 /G33/G45 /G48 /G33/G46 /G48 /G49/G41 /G52/G30 /G4D/G50 /G30 /G49/G41 /G52/G31 /G4D/G50 /G31 /G42/G50 /G41/G43 /G43 /G50/G43 /G4C /G54/G42 /G4C/G50 /G54/G42 /G4C/G48 /G54/G42 /G48/G50 /G53/G54 /G41/G54 /G55/G53 /G53/G4D /G4F/G44 /G55/G6E /G75/G73 /G65/G64 /G49/G4E /G54/G45 /G47 /G49/G4E /G54/G43 /G30 /G49/G4E /G54/G43 /G31 /G49/G4E /G54/G43 /G32 /G49/G4E /G54/G43 /G33 /G4C/G56 /G44/G43 /G55/G6E /G75/G73 /G65/G64 /G50/G41 /G50/G41 /G43 /G50/G41/G50 /G55 /G50/G41/G57 /G55 /G53/G4C /G45/G44 /G43/G30 /G53/G4C /G45/G44 /G43/G31 /G57/G44 /G54/G43 /G54/G42 /G43 /G50/G53 /G43/G52 /G55/G6E /G75/G73 /G65/G64 /G45/G45 /G41 /G45/G45 /G44 /G50/G42 /G50/G42 /G43 /G50/G42/G50 /G55 /G49/G32 /G43/G54 /G4F/G43 /G49/G49/G43 /G43/G30 /G49/G49/G43 /G43/G31 /G49/G49 /G43/G44 /G49/G49/G43 /G41 /G55/G53 /G52 /G55/G43/G52/G31 /G55/G43/G52/G32 /G42/G52 /G47 /G54/G58 /G52/G5F /G52/G58 /G52 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G54/G4D /G50/G43 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G53/G4C /G43/G44/G43 /G30 /G53/G4C /G43/G44/G43 /G31 /G53/G4C /G43/G44/G43 /G32 /G53/G4C /G43/G44/G43 /G33 /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G50/G43 /G50/G43 /G43 /G50/G43 /G50/G55 /G55/G6E /G75/G73 /G65/G64 /G43/G54 /G52/G4C /G55/G6E /G75/G73 /G65/G64 /G55/G6E /G75/G73 /G65/G64 /G34/G30 /G48 /G34/G31 /G48 /G34/G32 /G48 /G34/G33 /G48 /G34/G34 /G48 /G34/G35 /G48 /G34/G36 /G48 /G34/G37 /G48 /G34/G38 /G48 /G34/G39 /G48 /G34/G41 /G48 /G34/G42 /G48 /G34/G43 /G48 /G34/G44 /G48 /G34/G45 /G48 /G34/G46 /G48 /G35/G30 /G48 /G35/G31 /G48 /G35/G32 /G48 /G35/G33 /G48 /G35/G34 /G48 /G35/G35 /G48 /G35/G36 /G48 /G35/G37 /G48 /G35/G38 /G48 /G35/G39 /G48 /G35/G41 /G48 /G35/G42 /G48 /G35/G43 /G48 /G35/G44 /G48 /G35/G45 /G48 /G35/G46 /G48 /G36/G30 /G48 /G36/G31 /G48 /G36/G32 /G48 /G36/G33 /G48 /G36/G34 /G48 /G36/G35 /G48 /G36/G36 /G48 /G36/G37 /G48 /G36/G38 /G48 /G36/G39 /G48 /G36/G41 /G48 /G36/G42 /G48 /G36/G43 /G48 /G36/G44 /G48 /G36/G45 /G48 /G36/G46 /G48 /G37/G30 /G48 /G37/G31 /G48 /G37/G32 /G48 /G37/G33 /G48 /G37/G34 /G48 /G37/G35 /G48 /G37/G46 /G48 /G42/G61 /G6E/G6B /G20/G30 /G7E/G35 /G42/G61 /G6E/G6B /G20/G30 /G2C/G32 /G7E/G35 /G42/G61 /G6E/G6B /G20/G31 /G50/G44 /G50/G44 /G43 /G50/G44 /G50/G55 /G54/G4B /G54/G4D /G52 /G54/G4B /G43/G30 /G54/G4B /G31/G36 /G44/G4C /G54/G4B /G31/G36 /G44/G48 /G54/G4B /G43/G31 /G54/G4B /G4D/G30 /G31/G36 /G44/G4C /G54/G4B /G4D/G30 /G31/G36 /G44/G48 /G54/G4B /G4D/G30 /G52/G4F /G4C /G54/G4B /G4D/G30 /G52/G4F /G48 /G54/G4B /G4D/G30 /G43/G30 /G54/G4B /G4D/G30 /G43/G31 /G54/G4B /G4D/G31 /G31/G36 /G44/G4C /G54/G4B /G4D/G31 /G31/G36 /G44/G48 /G54/G4B /G4D/G31 /G52/G4F /G4C /G54/G4B /G4D/G31 /G52/G4F /G48 /G54/G4B /G4D/G31 /G43/G30 /G54/G4B /G4D/G31 /G43/G31 /G54/G4B /G4D/G32 /G31/G36 /G44/G4C /G54/G4B /G4D/G32 /G31/G36 /G44/G48 /G54/G4B /G4D/G32 /G52/G4F /G4C /G54/G4B /G4D/G32 /G52/G4F /G48 /G54/G4B /G4D/G32 /G43/G30 /G54/G4B /G4D/G32 /G43/G31 /G54/G4B /G4D/G33 /G31/G36 /G44/G4C /G54/G4B /G4D/G33 /G31/G36 /G44/G48 /G54/G4B /G4D/G33 /G52/G4F /G4C /G54/G4B /G4D/G33 /G52/G4F /G48 /G54/G4B /G4D/G33 /G43/G30 /G54/G4B /G4D/G33 /G43/G31 /G43/G54 /G4D/G30 /G43/G30 /G43/G54 /G4D/G30 /G43/G31 /G43/G54 /G4D/G30 /G44/G4C /G43/G54 /G4D/G30 /G44/G48 /G43/G54 /G4D/G30 /G41/G4C /G43/G54 /G4D/G30 /G41/G48 /G50/G54 /G4D/G30 /G43/G30 /G50/G54 /G4D/G30 /G43/G31 /G50/G54 /G4D/G30 /G44/G4C /G50/G54 /G4D/G30 /G44/G48 /G50/G54 /G4D/G30 /G41/G4C /G50/G54 /G4D/G30 /G41/G48 /G50/G54 /G4D/G30 /G52/G50 /G4C /G50/G54 /G4D/G30 /G52/G50 /G48 /G54/G4B /G4D/G34 /G31/G36 /G44/G4C /G54/G4B /G4D/G34 /G31/G36 /G44/G48 /G54/G4B /G4D/G34 /G52/G4F /G4C /G54/G4B /G4D/G34 /G52/G4F /G48 /G54/G4B /G4D/G34 /G43/G30 /G54/G4B /G4D/G34 /G43/G31 /G55/G6E /G75/G73 /G65/G64 /G20 /G45/G45 /G43/G20 /G42/G53 /G38/G32/G44 /G32/G30 /G41/G2D /G33/G20 /G53 /G70/G65/G63 /G69/G61 /G6C/G20 /G50/G75 /G72/G70 /G6F/G73 /G65/G20 /G44/G61 /G74/G61 /G20/G4D /G65/G6D /G6F/G72 /G79 /G20/G20/G20/G20/G20/G20/G20/G20/G20

Rev. 1.60 36 Deee 1 016 Rev. 1.60 37 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers directly will return a result of "00H" and writing to the registers directly will result in no operation. Memory Pointers – MP0, MP1 Two Me mory Po inters, k nown a s MP0 a nd MP1 a re p rovided. T hese Me mory Po inters a re physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the releva nt Indirect Addressing Registers is carried out, the actual address that the microcontroller is di rected to is the address specified by the relat ed Memory Pointer . MP0, together with Indirect Addressing Register , IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access d ata f rom a ll banks a ccording t o the B P r egister. Di rect Ad dressing c an only be u sed with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 ´code´ org 00h start: m ov a ,04h ; setup size of block m ov block ,a m ov a ,offset adres1 ; Accumulator loaded with first RAM address m ov mp0 ,a ; setup memory pointer with first RAM address loop: c lr IAR0 ; clear the data at address defined by mp0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.

Rev. 1.60 38 Deee 1 016 Rev. 1.60 39 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bank Pointer – BP Depending upon which device is used, the Data Memory is divided into several banks. Selecting the required Data Memory area is achieved using the Bank Pointer. The Data Memory is initialised to Bank 0 after a reset, except for a WD T time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaf fected. It should be noted that the Special Function Data Memory is not af fected by the bank selection with the exception of the EEC register in Bank 1, which means that the Special Function Registers can be accessed from within any bank. The EEC register in bank 1 can only be accessed by indirectly addressing the Data Memory . Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer . Accessing data from banks other than Bank 0 must be implemented using Indirect Addressing. Device 7 6 5 4 3 2 1 0 BS8B1A-3 — — — — — — DMBP1 DMBP0 BS8C16A-3 — — — — — — DMBP1 DMBP0 BS8D0A-3 — — — — — DMBP DMBP1 DMBP0 BP Register List BP Register – BS82B12A-3 Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 DMBP1~DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Undefined BP Register – BS82C16A-3 Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 DMBP1~DMBP0: Select Data Memory Banks 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3

Rev. 1.60 38 Deee 1 016 Rev. 1.60 39 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BP Register – BS82D20A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — — DMBP DMBP1 DMBP0 R/W — — — — — R/W R/W R/W Bit 7 ~ 3 Unimplemented, read as "0" Bit 2 ~ 0 DMBP2~DMBP0: Select Data Memory Banks 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101: Bank 5 11x: Undefined Accumulator – ACC The A ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. W ithout the Accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he Da ta Me mory resulting i n highe r program ming and t iming overheads. Da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he Ac cumulator; for e xample, wh en t ransferring da ta be tween one user-defined register and another , it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory . By manipulating this register , direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to cont rol operation of the look-up table which is stored i n t he Progra m Me mory. T BLP a nd T BHP a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.

Rev. 1.60 40 Deee 1 016 Rev. 1.60 41 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (T O). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exceptio n of the T O and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the T O or PDF flag. In addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. The T O flag can be af fected only by a system power -up, a WDT time-out or by executing the "CLR WDT" or "HAL T" instruction. The PDF flag is af fected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction.
TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. T O is set by a WDT time-out. In additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

Rev. 1.60 40 Deee 1 016 Rev. 1.60 41 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver STATUS Register Bit 7 6 5 4 3 2 1 0 Nae — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5 TO: W atchdog T ime-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction.

Rev. 1.60 4 Deee 1 016 Rev. 1.60 43 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver EEPROM Data Memory The devices contain an area of internal EEPROM Data Memory . EEPROM, which stands for Electrically Erasable Programmable Read Only Memory , is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of d ata m emory, a wh ole n ew h ost o f a pplication p ossibilities a re m ade a vailable t o t he d esigner. The a vailability o f E EPROM st orage a llows i nformation su ch a s p roduct i dentification n umbers, calibration values , s pecific us er data, s ystem s etup data or other product information to be s tored directly within the product microcontroller . The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly accessible in the same w ay as the other types of memory . Read and W rite operations to the EEP ROM are carried o ut i n single b yte o perations u sing a n a ddress a nd d ata r egister i n Sector 0 a nd a si ngle control register in Sector 1. Device Capacity Address BS8B1A-3 64×8 00H~3FHBS8C16A-3 BS8D0A-3 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory . These are the address register , EEA, the data register , EED and a single control register , EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same way as any other Special Function Register . The EEC register however , being located in Bank 1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register , IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Control Registers List Name Bit 7 6 5 4 3 2 1 0 EEA — — D D4 D3 D D1 D0 EED D7 D6 D D4 D3 D D1 D0 EEC — — — — WREN WR RDEN RD EEA Register Bit 7 6 5 4 3 2 1 0 Nae — — D D4 D3 D D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 ~ 0 Data EEPROM address Data EEPROM address bit 5 ~ bit 0

Rev. 1.60 4 Deee 1 016 Rev. 1.60 43 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver EED Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM W rite Enable 0: Disable 1: Enable This is the D ata EEP ROM W rite Enable Bit w hich mus t be s et high before D ata EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM W rite Control 0: W rite cycle has finished 1: Activate a write cycle This i s t he Da ta E EPROM W rite C ontrol B it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no ef fect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero w ill inhibit D ata EEPROM read operations. Bit 0 RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the applic ation program will activ ate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no ef fect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time.

Rev. 1.60 44 Deee 1 016 Rev. 1.60 4 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Reading Data from the EEPROM To read data from the EEP ROM, the read enable bit, RDEN , in the EEC register must firs t be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register . If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle term inates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register . The data will remain in the EED register until another read or write operation i s e xecuted. T he a pplication pr ogram c an po ll t he RD bi t t o de termine whe n t he da ta i s valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in t he EE A regist er and t he dat a pla ced in t he EE D regist er. Then the writ e enabl e bit , WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the E EC r egister m ust b e i mmediately se t h igh t o i nitial a wr ite c ycle. T hese t wo i nstructions must be executed consecutively . The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on t he W rite E nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. Also at power -on the Bank Pointer , BP , will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the W rite Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register . When an EEPROM write cycle ends, the DEF request flag will be set. If the global and EEPROM write interrupts is enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is serviced, the EEPROM interrupt flag will be automatically reset.

Rev. 1.60 44 Deee 1 016 Rev. 1.60 4 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the W rite Enable bit is normally cleared to zero when not writing. Also the Memory P ointer high byte regis ter could be normally cleared to zero as this w ould inhibit access to Sector 1 where the EEPROM control register exist. Although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a si mple re ad ba ck proc ess. When wri ting da ta t he W R bi t m ust be se t hi gh i mmediately after the WREN bit has been set high, to ensure the write cycle executes correctly . The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally completed. Otherwise, the EEPROM read or write operation will fail. Programming Examples

Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer BP MOV BP, A SET IAR1.1 ; set RDEN bit, enable read operations SET IAR1.0 ; start Read Cycle - set RD bit BACK: SZ IAR1.0 ; check for read cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP MOV A, EED ; move read data to register MOV READ_DATA, A
Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, EEPROM_DATA ; user defined data MOV EED, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer BP MOV BP, A CLR EMI SET IAR1.3 ; set WREN bit, enable write operations SET IAR1.2 ; start Write Cycle - set WR bit – executed immediately ; a f t e r s e t W R E N b i t SET EMI BACK: SZ IAR1.2 ; check for write cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP

Rev. 1.60 46 Deee 1 016 Rev. 1.60 47 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Oscillator Various oscillator options of fer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview All the devices include two internal oscillators and the some devices also include an external oscillator. In addit ion to being the source of the main system clock the oscillators also provide clock sources for the Watchdog T imer , T ime Bases and TMs. External oscillator requiring some external components a s wel l a s fully i ntegrated i nternal osc illators requiring no e xternal c omponents, a re provided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. For t he BS8 2C16A-3 a nd BS82D20A-3 devices, the low speed oscillators are selected through the configuration option. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. W ith the capability of dynamically switching between fast and slow system clock, the devices have the flexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. Device Type Name Freq. Pins BS8B1A-3 BS8C16A-3 BS8D0A-3 Intenal High Speed RC HIRC 8/1/16MHz — Intenal Low Speed RC LIRC 3kHz — BS8C16A-3 BS8D0A-3 Extenal Low Speed Cystal LXT 3768Hz XT1/XT Oscillator Types System Clock Configurations There are three methods of generating the system clock, a high speed oscillator and two low speed oscillators. The high speed oscillato r is the internal 8MHz, 12MHz, 16MHz RC oscillator . The two low speed oscillators are the internal 32kHz oscillator, LIRC, and the external 32.768kHz crystal oscillator, LXT. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. For two of the three devices, the actual source clock used for the low speed oscillator is chosen via configuration option. The frequency of the slow speed or high speed system clock is also determined using t he HL CLK bi t a nd CKS2 ~ CKS0 bi ts i n t he SMOD re gister. Not e t hat t wo osc illator selections m ust be m ade na mely one hi gh spe ed a nd one l ow spe ed syst em osc illators. It i s not possible to choose a no-oscillator selection for either the high or low speed oscillator.

Rev. 1.60 46 Deee 1 016 Rev. 1.60 47 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G48/G49 /G52/G43 /G4C/G49 /G52/G43 /G48/G69 /G67/G68 /G20/G53 /G70/G65/G65/G64 /G20/G4F /G73/G63 /G69/G6C/G6C/G61 /G74/G69 /G6F/G6E /G4C/G6F /G77/G20 /G53/G70 /G65/G65/G64/G20 /G4F/G73 /G63/G69 /G6C/G6C /G61/G74 /G69/G6F /G6E/G73 /G66 /G48 /G66 /G48 /G2F/G36 /G34 /G66 /G48 /G2F/G33 /G32 /G66 /G48 /G2F/G31 /G36 /G66 /G48 /G2F/G38 /G66 /G48 /G2F/G34 /G66 /G48 /G2F/G32 /G36/G2D /G73/G74 /G61/G67/G65/G20 /G50 /G72/G65 /G73/G63/G61 /G6C/G65 /G72 /G66 /G53/G59/G53 /G48/G4C /G43/G4C /G4B/G2C /G20 /G43/G4B /G53/G32 /G7E/G43 /G4B/G53 /G30/G20 /G62/G69 /G74/G73 /G4C/G58 /G54 /G43/G6F /G6E/G66 /G69/G67 /G75/G72 /G61/G74 /G69/G6F /G6E /G4F/G70 /G74/G69 /G6F/G6E /G66 /G53/G55 /G42 Note: The LXT oscillator is only for the BS82C16A-3 and BS82D20A-3. System Clock Configurations Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a power on default frequency of 8 MHz but can be selected to be either 8MHz, 12MHz or 16MHz via a configuration option and the HIRCS1 and HIRCS0 bit s in the CTRL register . Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is a low frequency oscillator . It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V , requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.

Rev. 1.60 48 Deee 1 016 Rev. 1.60 49 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver External 32.768kHz Crystal Oscillator – LXT For the BS82C16A-3 and BS82D20A-3 devices, the External 32.768kHz Crystal System Oscillator is one of t he l ow fre quency osc illator c hoices, whi ch i s sel ected vi a c onfiguration opt ion. T his clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pi ns XT 1 a nd XT 2. T he e xternal re sistor a nd c apacitor c omponents c onnected t o t he 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to dif ferent crystal m anufacturing t olerances. Duri ng po wer-up t here i s a t ime de lay a ssociated wi th t he L XT oscillator waiting for it to start-up. When the microco ntroller enters the SLEEP or IDLE Mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. Howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. T o do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification. The external parallel feedback resistor , Rp, is required. Note that the wire connected betwee n the 32.768kHz crystal and the XT1/XT2 pins should be kept as short as possible to minimize the stray noise interface. The configuration option determines if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins or other pin-shared functions.

If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/ O pins or other pin-shared functions.
If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For osci llator st ability and t o minimize t he ef fects of noise and crosst alk, i t i s i mportant t o ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. /G54/G6F /G20/G69 /G6E/G74 /G65/G72 /G6E/G61/G6C /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G49/G6E /G74/G65 /G72/G6E /G61/G6C /G4F /G73/G63/G69 /G6C/G6C /G61/G74 /G6F/G72 /G43/G69 /G72/G63 /G75/G69 /G74 /G43/G31 /G43/G32 /G52/G70 /G4E/G6F /G74/G65 /G3A/G31 /G2E/G20 /G52/G70 /G2C/G20/G43 /G31/G20 /G61/G6E/G64 /G20/G43 /G32/G20 /G61/G72 /G65/G20 /G72/G65 /G71/G75/G69 /G72 /G65/G64/G2E /G32/G2E /G20/G41 /G6C/G74 /G68/G6F/G75/G67/G68/G20 /G6E/G6F/G74 /G20/G73 /G68/G6F/G77 /G6E/G20 /G70/G69 /G6E/G73 /G20/G68 /G61/G76 /G65/G20 /G61 /G20/G20/G20/G20 /G70/G61/G72 /G61/G73 /G69/G74 /G69/G63 /G20/G63 /G61/G70/G61/G63 /G69/G74 /G61/G6E /G63/G65 /G20/G6F /G66/G20 /G61/G72 /G6F/G75/G6E/G64/G20 /G37/G70/G46 /G2E /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G43 /G4F /G73/G63 /G69/G6C/G6C/G61 /G74/G6F /G72 /G33/G32/G2E /G37/G36 /G38 /G6B/G48 /G7A /G58/G54 /G31 /G58/G54 /G32 External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 3.768kHz 10pF 10pF Note: 1. C1 and C values ae fo guidane only. . RP=MΩ~10MΩ is eoended. 32.768kHz Crystal Recommended Capacitor Values

Rev. 1.60 48 Deee 1 016 Rev. 1.60 49 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the CTRL register. LXTLP Bit LXT Mode

0 Quik Stat

1 Low-powe

After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly . However , after the LXT oscillator has fully powered up it can be placed into t he L ow-power m ode b y se tting t he L XTLP b it h igh. T he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It shou ld be no ted t hat, no m atter wha t c ondition t he L XTLP bi t i s se t t o, t he L XT osc illator wi ll always function normally , the only dif ference is that it will take more time to start up if in the Low- power mode. Operating Modes and System Clocks Present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conflicting requirements that are especially true i n ba ttery powe red port able a pplications. T he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The main system clock, can come from either a high frequency , fH, or low frequency , fSUB, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register . The high speed system clock is sourced from the HIRC oscillator. The low speed system clock source can be sourced from inte rnal cloc k fSUB. Depending on the devices, if fSUB is selected then it is sourced by the LIRC oscillator or can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64.

Rev. 1.60 0 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G54/G69 /G6D/G65 /G20/G42 /G61/G73 /G65/G20 /G30 /G48/G49 /G52/G43 /G4C/G49 /G52/G43 /G48/G69 /G67/G68 /G20/G53 /G70/G65/G65/G64 /G20/G4F /G73/G63 /G69/G6C/G6C/G61 /G74/G69 /G6F/G6E /G4C/G6F /G77/G20 /G53/G70 /G65/G65/G64/G20 /G4F/G73 /G63/G69 /G6C/G6C /G61/G74 /G69/G6F /G6E/G73 /G66 /G48 /G66 /G48 /G2F/G36 /G34 /G66 /G48 /G2F/G33 /G32 /G66 /G48 /G2F/G31 /G36 /G66 /G48 /G2F/G38 /G66 /G48 /G2F/G34 /G66 /G48 /G2F/G32 /G36/G2D /G73/G74 /G61/G67/G65/G20 /G50/G72 /G65 /G73/G63/G61 /G6C/G65 /G72 /G66 /G53/G59/G53 /G48/G4C /G43/G4C /G4B/G2C /G20 /G43/G4B /G53/G32 /G7E/G43 /G4B/G53 /G30/G20 /G62/G69 /G74/G73 /G57/G44 /G54 /G54/G69 /G6D/G65 /G20/G42 /G61/G73 /G65/G20 /G31 /G4C/G58 /G54 /G43/G6F /G6E/G66 /G69/G67 /G75/G72 /G61/G74 /G69/G6F /G6E /G4F/G70 /G74/G69 /G6F/G6E /G66 /G53/G55 /G42 /G43/G4C /G4B/G53/G45/G4C /G30/G5B /G31/G3A /G30/G5D /G66 /G53/G59/G53 /G2F/G34 /G66 /G50/G53/G43 /G66 /G53/G59/G53 /G66 /G48 /G66 /G53/G55 /G42 /G54/G42 /G30/G5B /G32 /G3A/G30 /G5D /G43/G4C /G4B/G53/G45/G4C /G31/G5B /G31/G3A /G30/G5D /G66 /G53/G59/G53 /G2F/G34 /G66 /G50/G53/G43 /G66 /G53/G59/G53 /G66 /G48 /G66 /G53/G55 /G42 /G54/G42 /G31/G5B /G32 /G3A/G30 /G5D /G49 /G32 /G43/G20 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 System Clock Configurations Note: The LX T oscillator is only for the BS82C16A-3 and BS82D 20A-3. When the sys tem clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power . Thus there is no fH~fH/64 for peripheral circuit to use.

Rev. 1.60 0 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver System Operation Modes There a re five d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. There are two modes all owing normal operati on of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP , IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operating Mode

Description

NORMAL ode On fH~fH/64 On SLOW ode On fSUB On ILDE0 ode Off Off On IDLE1 ode Off On On SLEEP ode Off Off Off NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . This mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD regis ter. A lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. T he c lock so urce u sed wi ll b e f rom fSUB. R unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP Mode The S LEEP M ode is entered w hen an H ALT instruction is executed and w hen the ID LEN bit in the SMOD register is low . In the SLEEP mode the CPU will be stopped, and the fSUB clock will be stopped too, the W atchdog T imer function is automatically disabled by hardware for power saving. IDLE0 Mode The IDLE0 Mode is entered when a HAL T instruction is executed and when the IDLEN bit in the SMOD regi ster i s high and t he FSYSON bit i n t he CTRL register i s l ow. In t he IDLE 0 Mode t he system oscillator will be stop and will therefore be inhibited from driving the CPU. IDLE1 Mode The IDLE1 Mode is entered when a HAL T instruction is executed and when the IDLEN bit in the SMOD registe r is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator.

Rev. 1.60 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Control Register The SMOD register is used to control the internal clocks within the devices. SMOD Register Bit 7 6 5 4 3 2 1 0 Nae CKS CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7 ~ 5 CKS2 ~ CKS0: The system clock selection when HLCLK is "0" 000: fSUB (LIRC or LXT) 001: fSUB (LIRC or LXT) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0". Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscilla tor ready flag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. The flag will be low when in the SLEEP mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This i s t he hi gh spe ed syst em osc illator re ady fl ag whi ch i ndicates whe n t he hi gh speed system oscillator is stable after a wake-up has occurred. This flag is cleared to zero by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power -on. The flag will be low when in the SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used. Bit 1 IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HAL T instruction is executed. If this bit is high, when a HAL T instruction is executed the device wi ll e nter t he IDLE Mo de. I n t he I DLE1 Mo de t he C PU wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HAL T instruction is executed. Bit 0 HLCLK: System Clock Selection 0: fH/2 ~ fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power.

Rev. 1.60 Deee 1 016 Rev. 1.60 3 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CTRL Register Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 Unimplemented, read as "0". Bit 5 ~ 4 HIRCS1~HIRCS0: HIRC frequency clock select 00: 8MHz 01: 12 MHz 10: 16 MHz 11: 8 MHz It is recommended that the HIRC frequency selected by these two bits is the same with the frequency determined by the configuration option to keep the HIRC frequency accuracy specified in the A.C. characteristics. Bit 3 LXTLP: LXT low power control 0: Quick Start mode 1: Low Power mode Bit 2 LVRF: LVR function reset flag Describe elsewhere Bit 1 Undefined bit This bit can be read or written by user software program Bit 0 WRF: WDT Control register software reset flag Describe elsewhere /G4E/G4F /G52/G4D /G41/G4C /G66 /G53/G59/G53 /G3D/G66 /G48 /G7E/G66 /G48 /G2F/G36 /G34 /G66 /G48 /G20/G6F /G6E /G43/G50 /G55/G20 /G72/G75 /G6E /G66 /G53/G59/G53 /G20/G6F /G6E /G66 /G53/G55 /G42/G20 /G6F/G6E /G57/G44 /G54/G20 /G6F/G6E /G49/G44 /G4C/G45 /G31 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74/G72 /G75/G63 /G74/G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74/G65 /G64 /G43/G50 /G55/G20 /G73/G74 /G6F/G70 /G49 /G44/G4C /G45/G4E /G3D/G31 /G46/G53 /G59/G53 /G4F/G4E /G3D/G31 /G66 /G53/G59/G53 /G20/G6F /G6E /G66 /G53/G55 /G42/G20 /G6F/G6E /G57/G44 /G54/G20 /G6F/G6E /G49/G44 /G4C/G45 /G30 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74/G72 /G75/G63 /G74/G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74/G65 /G64 /G43/G50 /G55/G20 /G73/G74 /G6F/G70 /G49 /G44/G4C /G45/G4E /G3D/G31 /G46/G53 /G59/G53 /G4F/G4E /G3D/G30 /G66 /G53/G59/G53 /G20/G6F /G66/G66 /G66 /G53/G55 /G42/G20 /G6F/G6E /G57/G44 /G54/G20 /G6F/G6E /G53/G4C /G4F/G57 /G66 /G53/G59/G53 /G3D/G66 /G53/G55 /G42 /G43/G50 /G55/G20 /G72/G75 /G6E /G66 /G53/G59/G53 /G20/G6F /G6E /G66 /G53/G55 /G42/G20 /G6F/G6E /G66 /G48 /G20/G6F /G66/G66 /G57/G44 /G54/G20 /G6F/G6E /G53/G4C /G45/G45 /G50 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74/G72 /G75/G63 /G74/G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74/G65 /G64 /G66 /G53/G59/G53 /G20/G6F /G66/G66 /G43/G50 /G55/G20 /G73/G74 /G6F/G70 /G49 /G44/G4C /G45/G4E /G3D/G30 /G66 /G53/G55 /G42/G20 /G6F/G66 /G66 /G57/G44 /G54/G20 /G6F/G66 /G66

Rev. 1.60 4 Deee 1 016 Rev. 1.60 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Operating Mode Switching The d evice s c an swi tch b etween o perating m odes d ynamically a llowing t he u ser t o se lect t he b est performance/power ratio for the pres ent task in hand. In this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HAL T instruction. When a HAL T instructio n is executed, whether the devices enter the IDLE Mode or the SLEEP Mode is determined by the condit ion of the IDL EN bit in the SMOD regi ster and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power . When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running. The accompanying flowchart shows what happens when the devices move between the various operating modes. NORMAL Mode to SLOW Mode Switching When r unning i n t he NOR MAL Mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power , the system clock can switch to run in the SLOW Mode by clearing the HLCLK bit to zero and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register .This will then use the low speed system oscillator which will consume less power . Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SL OW Mo de i s so urced f rom t he LXT o r LIRC o scillator a nd t herefore r equires these oscillators to be stable before full mode switching occurs. This is monitored using the L TO bit in the SMOD register. /G53/G4C /G4F/G57 /G20/G4D /G6F/G64/G65 /G53/G4C /G45 /G45/G50/G20 /G20/G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G30/G20 /G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G31/G20 /G4D /G6F/G64/G65 /G4E/G4F /G52/G4D /G41/G4C /G20/G4D /G6F/G64 /G65 /G43/G4B /G53/G32 /G20/G7E /G20/G43 /G4B/G53/G30 /G20/G3D /G20 /G30/G30/G78 /G42/G20 /G26 /G48/G4C /G43/G4C /G4B/G20 /G3D/G20 /G30 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G30 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74 /G72/G75 /G63/G74 /G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53 /G4F/G4E /G3D/G30 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74 /G72/G75 /G63/G74 /G69/G6F /G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53/G4F /G4E/G3D /G31 /G48/G41 /G4C/G54 /G20/G69 /G6E/G73 /G74 /G72/G75 /G63/G74 /G69 /G6F/G6E/G20 /G69/G73 /G20/G65 /G78/G65 /G63/G75 /G74 /G65/G64

Rev. 1.60 4 Deee 1 016 Rev. 1.60 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator . T o switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set high or HLCLK bit is low, but CKS2~CKS0 is set to "010", "01 1", "100", "101", "1 10" or "111". A s a certain amount of time w ill be required for the high frequency clock to s tabilise, the status of the HT O bit is checked. The amount of time required for high speed system oscillator stabilization is 15~16 clock cycles. /G4E/G4F /G52/G4D /G41/G4C /G20/G4D /G6F/G64/G65 /G53/G4C /G45 /G45/G50/G20 /G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G30/G20 /G4D /G6F/G64/G65 /G49/G44 /G4C/G45 /G31/G20 /G4D /G6F/G64/G65 /G53/G4C /G4F/G57 /G20/G4D /G6F/G64 /G65 /G43/G4B /G53/G32 /G7E/G43 /G4B/G53/G30 /GB9 /G30/G30/G30/G42 /G2C/G20 /G30/G30/G31/G42 /G20/G61 /G73/G20 /G48/G4C /G43/G4C /G4B/G3D /G30 /G6F/G72 /G20/G48 /G4C/G43 /G4C/G4B /G3D/G31 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G30 /G48/G41 /G4C/G54 /G20/G69 /G6E /G73/G74 /G72/G75 /G63/G74 /G69/G6F /G6E /G20/G69 /G73/G20 /G65/G78 /G65/G63 /G75/G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53 /G4F/G4E /G3D/G30 /G48/G41 /G4C/G54 /G20/G69 /G6E /G73/G74 /G72/G75 /G63/G74 /G69/G6F /G6E /G20/G69 /G73/G20 /G65/G78 /G65/G63 /G75/G74 /G65/G64 /G49/G44 /G4C/G45 /G4E/G20 /G3D/G20 /G31/G2C /G20/G46 /G53/G59/G53/G4F /G4E/G3D /G31 /G48/G41 /G4C/G54 /G20/G69 /G6E /G73/G74 /G72/G75 /G63/G74 /G69/G6F /G6E /G20/G69 /G73/G20 /G65/G78 /G65/G63 /G75/G74 /G65/G64 Entering the SLEEP Mode There is only one way for the devic es to enter the SLEEP Mode and that is to execute the "HAL T" instruction in the application program with the IDLEN bit in SMOD register equal to "0". When this instruction is executed under the conditions described above, the following will occur:

The system clock and the fSUB clock will be stopped and the application program will stop at the "HALT" instruction.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and stop counting.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the W atchdog time-out flag, T O, will be cleared.

Rev. 1.60 6 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Entering the IDLE0 Mode There is only one way for the devices to enter the IDLE0 Mode and that is to execute the "HAL T" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur:

The system clock will be stopped and the application program will stop at the "HALT" instruc- tion, but the low frequency fSUB clock will be on.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the W atchdog time-out flag, T O, will be cleared. Entering the IDLE1 Mode There is only one way for the devices to enter the IDLE1 Mode and that is to execute the "HAL T" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur:
The system clock and the low frequency fSUB will be on and the application program will stop at the "HALT" instruction.
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the W atchdog time-out flag, T O, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. Spe cial a ttention m ust be m ade t o the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumpti on. This also applies to devices which have dif ferent package types, as there may be unbonbed pins. These must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. T hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps.

An external falling edge on Port A
A system interrupt
A WDT overflow If the device is woken up by a WDT overflow , a W atchdog T imer reset will be initiated. The PDF flag is cleared by a system power -up or executing the clear W atchdog T imer instructions and is set when e xecuting t he "HAL T" i nstruction. T he T O fla g i s se t i f a W DT t ime-out oc curs, a nd c auses a wake-up that only resets the Program Counter and Stack Pointer , the other flags remain in their original status. Each pin on Port A can be setup using the P AWU register to permit a negative transition on the pin to wake-up t he syste m. When a Port A pin wake-up occurs, the progra m wil l resume exec ution at the instruction following the "HAL T" instruction. If the system is woken up by an interrupt, then two possible situations may occur . The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HAL T" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag i s se t hi gh be fore e ntering t he SLE EP or IDL E Mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. System Oscillator Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) HIRC 1~16 HIRC yles 1~ HIRC yles LIRC 1~ LIRC yles 1~ LIRC yles LXT 104 LXT yles 1~ LXT yles Wake-Up Time Programming Considerations The high speed and low speed oscillators both use the same SST counter . For example, if the system is woken up from the SLEEP Mode the HIRC oscillator needs to start-up from an off state. If the device is woken up from the SLEEP Mode to the NO RMAL Mode, the high speed system oscillator needs an SST period. The device will execute the first instruction after HT O is high. At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator . The same situation occurs i n t he powe r-on st ate. T he L XT osc illator i s not rea dy yet whe n t he first i nstruction i s executed.

Rev. 1.60 8 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Watchdog Timer The W atchdog T imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The W atchdog T imer clock source is provided by the internal fSUB cloc k, depending on the devices, the fSUB clock is in turn supplied by the LIRC oscillator or either the LXT or LIRC oscillator selected by a configuration option. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an externa l 32.768 kHz crystal. The W atchdog T imer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register , WDTC, controls the required timeout period as well as the enable operation. The WDTC register is initiated to 01010011B at any reset except WDT time-out hardware warm reset. WDTC Register Bit 7 6 5 4 3 2 1 0 Nae WE4 WE3 WE WE1 WE0 WS WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~ 3 WE4 ~ WE0 : WDT function software control 01010B or 10101B: Enabled Other values: Reset MCU (Reset will be active after 2~3 LIRC clock for debounce time.) If the MCU reset is caused by the WE [4:0] in WDTC software reset, the WRF flag of CTRL register will be set. Bit 2~ 0 WS2 ~ WS0 : WDT T ime -out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three bits determine the division ratio of the Watchdog T imer s ource clock, which in turn determines the timeout period.

Rev. 1.60 8 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CTRL Register Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Describe elsewhere Bit 6 Unimplemented, read as "0" Bit 5~ 4 HIRCS1~HIRCS0: HIRC frequency clock select Describe elsewhere Bit 3 LXTLP: LXT low power control Describe elsewhere Bit 2 LVRF: LVR function reset flag Describe elsewhere Bit 1 Undefined bit This bit can be read or written by user software program Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set high by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The W atchdog T imer ope rates by provi ding a de vice re set whe n i ts t imer ove rflows. T his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he Watchdog T imer before it overflows to prevent the W atchdog T imer from executing a reset. This is done using the cle ar watchdog instructions. If the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear WDT instruction will not be executed in the correct manne r, in which case the W atchdog T imer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to enable the WDT function. When the WE4~WE0 bits value is equal to 01010B or 10101B, the WDT function is enabled. However , if the WE4~WE0 bits are changed to any other values except 01010B and 10101B, which is caused by the environmental noise, it will reset the microcontroller after 2~3 LIRC clock cycles. After power on these bits will have a value of 01010B. Under norm al progra m ope ration, a W atchdog T imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit T O. However , if the system is in the SLEEP or IDLE Mode, when a W atchdog T imer time-out occurs, the T O bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the W atchdog T imer. The first is a WDT software reset, which means a certain value is written into the WE4~WE0 bit filed exce pt 01010B and 10101B, the second is using the W atchdog T imer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the W atchdog T imer. That is to use the single "CLR WDT" instruction to clear the WDT . The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.

Rev. 1.60 60 Deee 1 016 Rev. 1.60 61 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver 000:8/fSUB WS[:0]= fSUB CLR Reset MCU 11 stage divide 8-to-1 MUX WDT Tie-out WS~WS0 7-stage Divide (fSUB/1~fSUB/11) 001:10/fSUB 010:1/fSUB 011:14/fSUB 100:1/fSUB 101:16/fSUB 110:17/fSUB 111:18/fSUB “HALT”Instution “CLR WDT”Instution WE4~WE0 itsWDTC Registe LIRC LXT M U X Configuation Option Note: For the BS82B12A-3 device, the fSUB is supplied only by the LIRC oscillator. Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller . In this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fir st p rogram i nstruction. Af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is w hen the W atchdog T imer overflow s and resets the microcontroller . A ll types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low V oltage Reset, L VR, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally: Power-on Reset The m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s first a pplied t o the microcontroller . As well as ensuring that the Program Memory begins execution from the first memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Powe-on Reset SST Tie-out tRSTD Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart

Rev. 1.60 60 Deee 1 016 Rev. 1.60 61 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Low Voltage Reset – LVR The micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The L VR function is always enabled with a specific L VR voltag e, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery , the L VR will automatically reset the device internally and the L VRF bit in the CTRL register will also be set high. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteri stics. If the low voltage state does not exceed this value, the L VR will ignore the low supply voltage and will not perform a reset function. The actual VLVR is fixed at a voltage value of 2.55V. Note that the L VR function will be automatically disabled when the device enters the SLEEP or IDLE mode. /G4C/G56 /G52 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 /G74 /G52/G53 /G54/G44 /G20/G2B /G20 /G74 /G53/G53/G54 Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart

CTRL Register Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 LXTLP LVRF D1 WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Describe elsewhere Bit 6 Unimplemented, read as "0". Bit 5 ~ 4 HIRCS1~HIRCS0: HIRC frequency clock select Describe elsewhere Bit 3 LXTLP: LXT low power control Describe elsewhere Bit 2 LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set high when a specific Low V oltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Bit 1 Undefined bit This bit can be read or written by user software program Bit 0 WRF: WDT Control register software reset flag Describe elsewhere Watchdog Time-out Reset during Normal Operation The W atchdog time-out Reset during normal operation is the same as a LVR reset except that the Watchdog time-out flag T O will be set to "1". /G74 /G52/G53 /G54/G44 /G20/G2B /G20 /G74 /G53/G53/G54 /G57/G44 /G54/G20 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart

Rev. 1.60 6 Deee 1 016 Rev. 1.60 63 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Watchdog Time-out Reset during SLEEP or IDLE Mode The W atchdog time-out Reset during SLEEP or IDLE Mode is a little dif ferent from other kinds of re set. Mo st of t he c onditions re main unc hanged e xcept t hat t he Pro gram Count er a nd t he St ack Pointer will be cleared to zero and the T O flag will be set high. Refer to the A.C. Characteristics for tSST details. /G74 /G53/G53/G54 /G57/G44 /G54/G20 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC. The tSST is 1~2 clock for the LIRC. The tSST is 1024 clock for the LXT. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The dif ferent types of reset described af fect the reset flags in dif ferent ways. These flags, known as P DF and T O are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he SL EEP o r I DLE Mo de f unction o r W atchdog T imer. T he r eset f lags a re shown in the table: TO PDF RESET Conditions 0 0 Powe-on eset u u LVR eset duing NORMAL o SLOW Mode opeation 1 u WDT tie-out eset duing NORMAL o SLOW Mode opeation 1 1 WDT tie-out eset duing IDLE o SLEEP Mode opeation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Poga Counte Reset to zeo Inteupts All inteupts will e disaled WDT Clea afte eset WDT egins ounting Tie Modules Tie Modules will e tuned off Input/Output Pots I/O pots will e setup as inputs Stak Pointe Stak Pointe will point to the top of the stak The dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers.

Rev. 1.60 6 Deee 1 016 Rev. 1.60 63 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Register BS82B12A-3 BS82C16A-3 BS82D20A-3 Power On Reset LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (HALT)* Poga Counte ● ● ● 0000H 0000H 0000H 0000H MP0 ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ACC ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● x xxx xxxx u uuu uuuu u uuu uuuu u uuu uuuu TBHP

---- - xxx ---- - uuu ---- - uuu ---- - uuu
---- xxxx ---- uuuu ---- uuuu ---- uuuu
---x xxxx ---u uuuu ---u uuuu ---u uuuu STATUS ● ● ● --00 xxxx --uu uuuu --1u uuuu --11 uuuu SMOD ● ● ● 000- 0011 000- 0011 000- 0011 uuu- uuuu INTC0 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PA ● ● ● 1--1 1111 1--1 1111 1--1 1111 u--u uuuu PAC ● ● ● 1--1 1111 1--1 1111 1--1 1111 u--u uuuu PAPU ● ● ● 0--0 0000 0--0 0000 0--0 0000 u--u uuuu PAWU ● ● ● 0--0 0000 0--0 0000 0--0 0000 u--u uuuu SLEDC0 ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu
● --01 0101 --01 0101 --01 0101 --uu uuuu WDTC ● ● ● 0101 0011 0101 0011 0101 0011 uuuu uuuu TBC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu EEA ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu EED ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PB ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ICTOC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IICC1 ● ● ● 1000 0001 1000 0001 1000 0001 uuuu uuuu IICD ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu IICA ● ● ● 0000 000- 0000 000- 0000 000- uuuu uuu- USR ● ● ● 0000 1011 0000 1011 0000 1011 uuuu uuuu UCR1 ● ● ● 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

Rev. 1.60 64 Deee 1 016 Rev. 1.60 6 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Register BS82B12A-3 BS82C16A-3 BS82D20A-3 Power On Reset LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (HALT)* TXR_RXR ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SLCDC0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTRL ● ● ● 0-00 0x00 0-00 0x00 0-00 0x00 u-uu uuuu TKTMR ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC0 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu TK16DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TK16DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM016DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM016DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM116DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM116DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM16DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM16DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMC0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMC1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM316DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM316DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3C0 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3C1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu CTM0C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu

Rev. 1.60 66 Deee 1 016 Rev. 1.60 67 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Input/Output Ports Holtek m icrocontrollers of fer c onsiderable fle xibility on t heir I/ O port s. W ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The devices provide bidirectional input/output lines labeled with port names P A ~ PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. A ll of thes e I/O ports can be used for input and output operations. For input operation, these ports are non-latch ing, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List Device Register Name Bit 7 6 5 4 3 2 1 0 BS8B1A-3 BS8C16A-3 BS8D0A-3 PAWU PAWU7 — — PAWU4 PAWU3 PAWU PAWU1 PAWU0 PAPU PAPU7 — — PAPU4 PAPU3 PAPU PAPU1 PAPU0 PA PA7 — — PA4 PA3 PA PA1 PA0 PAC PAC7 — — PAC4 PAC3 PAC PAC1 PAC0 PBPU PBPU7 PBPU6 PBPU PBPU4 PBPU3 PBPU PBPU1 PBPU0 PB PB7 PB6 PB PB4 PB3 PB PB1 PB0 PBC PBC7 PBC6 PBC PBC4 PBC3 PBC PBC1 PBC0 PCPU PCPU7 PCPU6 PCPU PCPU4 PCPU3 PCPU PCPU1 PCPU0 PC PC7 PC6 PC PC4 PC3 PC PC1 PC0 PCC PCC7 PCC6 PCC PCC4 PCC3 PCC PCC1 PCC0 BS8C16A-3 BS8D0A-3 PDPU — — — — PDPU3 PDPU PDPU1 PDPU0 PD — — — — PD3 PD PD1 PD0 PDC — — — — PDC3 PDC PDC1 PDC0 PAWUn: PA wake-up function control 0: Disable 1: Enable PAn/PBn/PCn/PDn: I/O Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn: I/O T ype selection 0: Output 1: Input PAPUn/PBPUn/PCPUn/PDPUn: I/O Pull-high function control 0: Disable 1: Enable

Rev. 1.60 66 Deee 1 016 Rev. 1.60 67 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . T o eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor . These pull-high re sistors a re se lected usi ng re gisters P APU~PDPU, a nd a re i mplemented usi ng we ak PMOS transistors. Port A Wake-up The HAL T instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. V arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low . This function is especially suitable for applications that can be woken up via extern al switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. I/O Port Control Registers Each I/O port has its ow n control register known as P AC~PDC, to control the input/output configuration. W ith this control register , each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register . For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. /G56 /G44/G44 /G4D /G55 /G58 /G57/G61 /G6B/G65 /G2D/G75 /G70/G20 /G53/G65 /G6C/G65 /G63/G74 /G53 /G79/G73/G74 /G65/G6D /G20/G57 /G61/G6B /G65/G2D /G75/G70 /G52 /G65/G61/G64/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G44 /G51 /G43/G4B /G53 /G44 /G51 /G43/G4B /G53 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G42/G69 /G74 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G57/G72 /G69/G74 /G65/G20 /G43 /G6F/G6E/G74 /G72/G6F /G6C/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G43/G68 /G69/G70 /G20/G52 /G65/G73 /G65/G74 /G52/G65 /G61/G64 /G20/G43 /G6F/G6E /G74/G72 /G6F/G6C /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G57/G72 /G69/G74 /G65/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G44/G61 /G74/G61 /G20/G42 /G69/G74 /G49/G2F/G4F /G20/G70 /G69/G6E /G51 /G51 /G50/G41 /G20/G6F /G6E/G6C /G79 /G57/G65 /G61/G6B /G50/G75 /G6C/G6C/G2D /G75/G70 /G50/G75 /G6C/G6C /G2D/G48 /G69/G67 /G68 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G53/G65 /G6C/G65 /G63/G74 Generic Input/Output Structure

Rev. 1.60 68 Deee 1 016 Rev. 1.60 69 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Source Current Selection The source current of each pin in these devices can be configured with dif ferent source current which is selected by the corresponding pin source current select bits. These source current bits are available when the corresponding pin is configured as a CMOS output. Otherwise, these select bits have no ef fect. Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. SLEDC0 Register Bit 7 6 5 4 3 2 1 0 Nae PBPS3 PBPS PBPS1 PBPS0 PAPS3 PAPS PAPS1 PAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 ~ 6 PBPS3~PBPS2: PB7~PB4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 5 ~ 4 PBPS1~PBPS0: PB3~PB0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 3 ~ 2 PAPS3~PAPS2: PA7 and PA4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 1 ~ 0 PAPS1~PAPS0: PA3~PA0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. SLEDC1 Register – BS82B12A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — PCPS3 PCPS PCPS1 PCPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 1 0 1 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 ~ 2 PCPS3~PCPS2: PC7~PC4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output.

Rev. 1.60 68 Deee 1 016 Rev. 1.60 69 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 1 ~ 0 PCPS1~PCPS0: PC3~PC0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. SLEDC1 Register – BS82C16A-3/BS82D20A-3 Bit 7 6 5 4 3 2 1 0 Nae — — PDPS1 PDPS0 PCPS3 PCPS PCPS1 PCPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 1 0 1 0 1 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 ~ 4 PDPS1~PDPS0: PD3~PD0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 3 ~ 2 PCPS3~PCPS2: PC7~PC4 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Bit 1 ~ 0 PCPS1~PCPS0: PC3~PC0 source current select 00 : source = Level 0 (min.) 01 : source = Level 1 10 : source = Level 2 11 : source = Level 3 (max.) These bits are available when the corresponding pin is configured as a CMOS output. Programming Considerations Within the user program, one of the first things to consider is port initi alisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. If the port control registers, P AC~PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port dat a regi sters, P A~PD, a re first progra mmed. Se lecting whi ch pi ns a re i nputs a nd whi ch are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions . N ote that w hen us ing thes e bit control instructions , a read-modify-w rite operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

Rev. 1.60 70 Deee 1 016 Rev. 1.60 71 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Timer Modules – TM One of the most fundamental functions in any microcont roller device is the ability to control and measure time. T o implement time related functions the device includes several T imer Modules, abbreviated t o t he na me T M. T he T Ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as T imer/Counter, Input Capture, Compare Match Output and Single Pulse Output as we ll a s be ing t he fun ctional uni t for t he ge neration of PW M si gnals. E ach of t he T Ms ha s t wo individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the dif ferent TM types are described here with more detailed information provided in the individual Compact and Periodic TM sections. Introduction Each device contains a 10-bit Compact TM, CTM, and a 10-bit Periodic TM, PTM. Although similar in nature, the dif ferent TM types vary in their feature complex ity. The common features to the Compact and Periodic TMs will be described in this section and the detailed operation will be described in corresponding sections. The main features and dif ferences between the two types of TMs are summarised in the accompanying table. Function CTM PTM Tie/Counte √ √ I/P Captue — √ Copae Math Output √ √ PWM Channels 1 1 Single Pulse Output — 1 PWM Alignent Edge Edge PWM Adjustent Peiod & Duty Duty o Peiod Duty o Peiod TM Function Summary CTM0 PTM0 10-it CTM 10-it PTM TM Name/Type Reference TM Operation The two different t ypes o f T Ms o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. When the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a T M i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he T M ou tput pi n. T he i nternal T M c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where "x" can stand for C or P and "n" is the serial number . The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fSUB clock source or the external TCKn pin. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting.

Rev. 1.60 70 Deee 1 016 Rev. 1.60 71 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver TM Interrupts The Compact and Periodic type TMs each has two internal interrupts, the internal comparator A or com parator P , whi ch ge nerate a TM interrupt when a com pare match condition oc curs. Whe n a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pins, with the label TCKn. The TM input pin, TCKn, is essentially a clock source for the TM and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register . This external TM input pin allows an external clock source to drive the internal TM. The TM input pin can be chosen to have either a rising or falling active edge. The TCK1 pin is also used as the external trigger input pin in single pulse output mode for the PTM0. The TMs each has two output pins. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to s witch to a high or low level or to toggle w hen a compare match situation occurs. As the TM output pins are pin-shared with other function, the TM output function must first be setup using the associated register. A single bit in the register determines if its associated pin is to be used as an external TM output pin or if it is to have another function. Device CTM0 PTM0 BS8B1A-3 BS8C16A-3 BS8D0A-3 TCK0 TP0_0 TP0_1 TCK1 TP1_0 TP1_1 TM Input/Output Pins TM Input/Output Pin Control Register Selecting t o ha ve a T M i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. /G54/G43 /G4B /G20/G49 /G6E/G70/G75 /G74 /G43/G54 /G4D/G30 /G50/G41 /G34/G2F /G54/G43 /G4B/G30 /G50/G43 /G37/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G43 /G37 /G31 /G30 /G4F/G75 /G74 /G70/G75/G74 /G50/G43 /G37/G2F /G54/G50 /G30/G5F/G31 /G54/G4D /G30/G50 /G43/G31 /G50/G43 /G35/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G43 /G35 /G31 /G30 /G50/G43 /G35/G2F /G54/G50 /G30/G5F/G30 /G54/G4D /G30/G50 /G43/G30 BS82B12A-3 CTM Function Pin Control Block Diagram

Rev. 1.60 7 Deee 1 016 Rev. 1.60 73 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G54/G43 /G4B /G20/G49 /G6E/G70/G75 /G74 /G43/G54 /G4D/G30 /G50/G41 /G34/G2F /G54/G43 /G4B/G30 /G50/G43 /G37/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G43 /G37 /G31 /G30 /G4F/G75 /G74 /G70/G75/G74 /G50/G43 /G37/G2F /G54/G50 /G30/G5F/G31 /G54/G4D /G30/G50 /G43/G31 /G50/G44 /G31/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G44 /G31 /G31 /G30 /G50/G44 /G31/G2F /G54/G50 /G30/G5F/G30 /G54/G4D /G30/G50 /G43/G30 BS82C16A-3/BS82D20A-3 CTM Function Pin Control Block Diagram /G50/G43 /G36/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G43 /G36 /G31 /G30 /G4F/G75 /G74 /G70/G75/G74 /G43 /G61/G70/G74 /G75/G72 /G65/G20 /G49 /G6E/G70/G75/G74 /G50/G41/G30 /G2F/G54 /G43/G4B /G31 /G54/G43 /G4B /G20/G49 /G6E/G70/G75/G74 /G50/G54 /G4D/G30 /G50/G43 /G36/G2F /G54/G50 /G31/G5F/G31 /G54/G4D /G31/G50 /G43/G31 /G50/G43 /G34/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G43 /G34 /G31 /G30 /G50/G43 /G34/G2F /G54/G50 /G31/G5F/G30/G20 /G54/G4D /G31/G50 /G43/G30 /G31 /G30 /G54/G4D /G31/G50 /G43/G31 /G31 /G30 /G54/G4D /G31/G50 /G43/G30 /G30 /G31 /G50/G54 /G30/G43 /G4B/G53 BS82B12A-3 PTM Function Pin Control Block Diagram

Rev. 1.60 7 Deee 1 016 Rev. 1.60 73 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G50/G43 /G36/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G43 /G36 /G31 /G30 /G4F/G75 /G74 /G70/G75/G74 /G43 /G61/G70/G74 /G75/G72 /G65/G20 /G49 /G6E/G70/G75/G74 /G50/G41/G30 /G2F/G54 /G43/G4B /G31 /G54/G43 /G4B /G20/G49 /G6E/G70/G75/G74 /G50/G54 /G4D/G30 /G50/G43 /G36/G2F /G54/G50 /G31/G5F/G31 /G54/G4D /G31/G50 /G43/G31 /G50/G44 /G30/G20 /G4F/G75 /G74 /G70/G75/G74 /G20/G46 /G75/G6E/G63 /G74/G69 /G6F/G6E /G30 /G31 /G50/G44 /G30 /G31 /G30 /G50/G44 /G30/G2F /G54/G50 /G31/G5F/G30/G20 /G54/G4D /G31/G50 /G43/G30 /G31 /G30 /G54/G4D /G31/G50 /G43/G31 /G31 /G30 /G54/G4D /G31/G50 /G43/G30 /G30 /G31 /G50/G30 /G54/G43 /G4B/G53 BS82C16A-3/BS82D20A-3 PTM Function Pin Control Block Diagram TMPC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — TM1PC1 TM1PC0 TM0PC1 TM0PC0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3 TM1PC1: TP1_1 pin Control 0: Disabled 1: Enabled Bit 2 TM1PC0: TP1_0 pin control 0: Disabled 1: Enabled Bit 1 TM0PC1: TP0_1 pin Control 0: Disabled 1: Enabled Bit 0 TM0PC0: TP0_0 pin Control 0: Disabled 1: Enabled

Rev. 1.60 74 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specific way . The important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these registers is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMnRPL, in the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. Data Bus 8-it Buffe xTMnDHxTMnDL xTMnAHxTMnAL xTMn Counte Registe (Read only) xTMn CCRA Registe (Read/Wite) PTMn CCRP Registe (Read/Wite) PTMnRPHPTMnRPL The following steps show the read and write procedures:

Writing Data to CCRA or CCRP ♦ Step 1. W rite data to Low Byte xTMnAL or PTMnRPL – note that here data is only written to the 8-bit buffer. ♦ Step 2. W rite data to High Byte xTMnAH or PTMnRPH – here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the Low Byte registers.
Reading Data from the Counter Registers and CCRA or CCRP ♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH – here d ata i s r ead d irectly f rom t he Hi gh B yte r egisters a nd si multaneously d ata i s l atched from the Low Byte register into the 8-bit buffer. ♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL – this step reads data from the 8-bit buffer.

Rev. 1.60 74 Deee 1 016 Rev. 1.60 7 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Compact Type TM – CTM0 Although the simplest form of the two T M types, the Compact T M type still contains three operating modes, wh ich a re Compare Ma tch Ou tput, T imer/Event C ounter a nd PW M Ou tput m odes. T he Compact T M c an a lso be c ontrolled wi th an e xternal i nput pi n a nd c an dri ve two external out put pins. /G43/G43/G52 /G50 /G43/G43/G52 /G41 /G43/G54 /G30 /G43/G43/G4C /G52 /G43/G6F /G6D /G70/G61/G72 /G61/G74 /G6F/G72 /G20/G50 /G20/G4D /G61/G74 /G63/G68 /G43/G6F /G6D /G70/G61/G72 /G61/G74 /G6F/G72 /G20/G41 /G20/G20 /G4D/G61 /G74/G63 /G68 /G43/G54 /G30/G43 /G4B/G32 /G7E/G43 /G54/G30 /G43/G4B /G30 /G43/G54 /G30/G4F /G4E /G43/G54 /G30/G50 /G41/G55 /G62/G37/G7E /G62/G39 /G33/G20 /G2D/G62 /G69/G74 /G20/G43 /G6F/G6D /G70/G61/G72 /G61/G74 /G6F/G72 /G20/G50 /G54/G43 /G4B/G30 /G31/G30/G20 /G2D/G62 /G69/G74 /G20/G43 /G6F/G6D /G70/G61/G72 /G61/G74 /G6F/G72 /G20/G41 /G43 /G6F/G75/G6E /G74/G65 /G72/G20 /G43/G6C /G65/G61/G72 /G31/G30/G2D /G62/G69 /G74/G20/G43 /G6F/G75/G6E /G74/G2D /G75/G70/G20 /G43 /G6F/G75/G6E /G74/G65 /G72 /G43/G54 /G4D/G50 /G30/G46 /G20/G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G43/G54 /G4D/G41 /G30/G46 /G20/G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G4F/G75 /G74/G70 /G75/G74 /G43/G6F /G6D/G70 /G6C/G65 /G6D/G65 /G6E /G74/G61 /G72/G79 /G62/G30/G7E /G62/G39/G20 /G43/G54 /G30/G4D /G31/G2C /G20/G43 /G54/G30 /G4D/G30 /G43/G54 /G30/G49 /G4F/G31 /G2C/G20 /G43/G54 /G30/G49 /G4F/G30 /G43/G54 /G30/G50 /G4F/G4C /G43/G54 /G30/G4F /G43 /G50/G6F /G6C/G61 /G72/G69 /G74/G79 /G43/G6F /G6E /G74/G72 /G6F/G6C /G4F/G75 /G74/G70 /G75/G74 /G43/G6F /G6E /G74/G72 /G6F/G6C /G54/G50 /G30/G5F /G30 /G31/G31/G31 /G30/G30/G30 /G30/G30/G31 /G30/G31/G30 /G30/G31/G31 /G31/G30/G30 /G31/G30/G31 /G31/G31/G30 /G66 /G53/G59/G53 /G2F/G34 /G66 /G53/G59/G53 /G66 /G48 /G2F/G31 /G36 /G66 /G48 /G2F/G36 /G34 /G66 /G53/G55 /G42 /G66 /G53/G55 /G42 /G30 /G31 /G54/G50 /G30/G5F /G31 Compact Type TM Block Diagram Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. T here a re a lso t wo i nternal c omparators wi th t he na mes, Com parator A a nd Com parator P. These c omparators wi ll c ompare t he v alue i n t he c ounter wi th C CRP a nd C CRA r egisters. T he CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The onl y way of changing the value of the 10-bit count er using the appl ication program , is to clear t he c ounter by c hanging t he CT0ON bi t from l ow t o hi gh. T he c ounter wi ll a lso be c leared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur , a CTM0 interrupt signal will also usually be generated. The Compact Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources i ncluding a n i nput pi n a nd c an a lso c ontrol one out put pi n. Al l ope rating set up c onditions are selected using relevant internal registers.

Rev. 1.60 76 Deee 1 016 Rev. 1.60 77 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Compact Type TM Register Description Overall ope ration of each Compact T M i s c ontrolled usi ng several re gisters. A re ad onl y re gister pair e xists t o st ore t he i nternal c ounter 10-bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Register Name Bit 7 6 5 4 3 2 1 0 CTM0C0 CT0PAU CT0CK CT0CK1 CT0CK0 CT0ON CT0RP CT0RP1 CT0RP0 CTM0C1 CT0M1 CT0M0 CT0IO1 CT0IO0 CT0OC CT0POL CT0DPX CT0CCLR CTM0DL D7 D6 D D4 D3 D D1 D0 CTM0AL D7 D6 D D4 D3 D D1 D0 Compact TM Register List CTM0C0 Register Bit 7 6 5 4 3 2 1 0 Nae CT0PAU CT0CK CT0CK1 CT0CK0 CT0ON CT0RP CT0RP1 CT0RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CT0PAU: CTM0 Counter Pause Control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal counter operation. When in a Pause condition the CTM0 will remain powered up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6~4 CT0CK2~CT0CK0: Select CTM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: TCK0 rising edge clock 111: TCK0 falling edge clock These t hree bi ts a re use d t o se lect t he c lock sourc e for t he CT M0. T he e xternal pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section.

Rev. 1.60 76 Deee 1 016 Rev. 1.60 77 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 3 CT0ON: CTM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/of f function of the CTM0. Setting the bit high enables the c ounter t o run, c learing t he bi t di sables t he CT M0. Cl earing t his bi t t o z ero wi ll stop the counter from counting and turn of f the CTM0 which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. If t he C TM 0 i s i n t he C ompare Ma tch Ou tput Mo de t hen t he C TM0 o utput p in wi ll be reset to its initial condition, as specified by the CT0OC bit, when the CT0ON bit changes from low to high. Bit 2~0 CT0RP2~CT0RP0: CTM0 CCRP 3-bit register, compared with the CTM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 CTM0 clocks 001: 128 CTM0 clocks 010: 256 CTM0 clocks 011: 384 CTM0 clocks 100: 512 CTM0 clocks 101: 640 CTM0 clocks 110: 768 CTM0 clocks 111: 896 CTM0 clocks These three bits are used to setup the value on the internal CCRP 3-bit register , which are then compared with the internal counter ’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CT0CCLR bit is set to zero. Setting the CT0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter . As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. CTM0C1 Register Bit 7 6 5 4 3 2 1 0 Nae CT0M1 CT0M0 CT0IO1 CT0IO0 CT0OC CT0POL CT0DPX CT0CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 CT0M1~CT0M0: Select CTM0 Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: T imer/Counter Mode These bits s etup the required operating mode for the CTM0. T o ens ure reliable operation the CTM0 should be switched of f before any changes are made to the CT0M1 a nd CT0M0 b its. I n t he T imer/Counter Mo de, t he CTM0 o utput p in c ontrol must be disabled. Bit 5~4 CT0IO1~CT0IO0: Select TP0 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined

Rev. 1.60 78 Deee 1 016 Rev. 1.60 79 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Timer/counter Mode Unused These two bits are used to determin e how the CTM0 output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTM0 is running. In the Compare Match Output Mode, the CT0IO1 and CT0IO0 bits determine how the CTM0 o utput p in c hanges st ate wh en a c ompare m atch o ccurs f rom t he C omparator A. The CTM0 output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTM0 output pi n sho uld be se tup usi ng t he C T0OC bi t i n t he C TM0C1 re gister. Not e t hat the output level requested by the CT0IO1 and CT0IO0 bits must be dif ferent from the initial value setup using the CT0OC bit otherwise no change will occur on the CTM0 output pin when a compare match occurs. After the CTM0 output pin changes state it can be reset to its initial level by changing the level of the CT0ON bit from low to high. In t he PW M Mode , t he CT0IO1 a nd CT0IO0 bi ts de termine how t he CT M0 output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CT0IO1 and CT0IO0 bits only after the CTM0 has been switched off. Unpredictable PWM outputs will occur if the CT0IO1 and CT0IO0 bits are changed when The CTM0 is running. Bit 3 CT0OC: TP0 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This i s t he ou tput c ontrol bi t fo r t he CT M0 ou tput pi n. It s op eration de pends up on whether CT M 0 i s be ing used i n t he Com pare Ma tch Output Mode or i n t he PWM Mode. It ha s no e ffect i f t he CT M0 i s i n t he T imer/Counter Mode. In t he Com pare Match Out put Mode i t de termines t he l ogic l evel of t he CT M0 out put pi n be fore a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 CT0POL: TP0 Output polarity Control 0: Non-invert 1: Invert This bi t c ontrols t he pol arity of t he CTM0 out put pi n. W hen t he bi t i s set hi gh t he CTM0 output pin will be inverted and not inverted when the bit is zero. It has no effect if the CTM0 is in the T imer/Counter Mode. Bit 1 CT0DPX: CTM0 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 CT0CCLR: Select CTM Counter clear condition 0: CTM0 Comparatror P match 1: CTM0 Comparatror A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he Compact CTM0 contains two comparators, Comparator A and Comparator P , either of which can be selected to clear the internal counter . W ith the CT0CCLR bi t set hi gh, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low , the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CT0CCLR bit is not used in the PWM Mode.

Rev. 1.60 78 Deee 1 016 Rev. 1.60 79 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CTM0DL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 CTM0 Counter Low Byte Register bit 7 ~ bit 0 CTM0 10-bit Counter bit 7 ~ bit 0 CTM0DH Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 C TM0 Counter High Byte Register bit 1 ~ bit 0 CTM0 10-bit Counter bit 9 ~ bit 8 CTM0AL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 CTM0 CCRA Low Byte Register bit 7 ~ bit 0 CTM0 10-bit CCRA bit 7 ~ bit 0 CTM0AH Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 CTM0 CCRA High Byte Register bit 1 ~ bit 0 CTM0 10-bit CCRA bit 9 ~ bit 8

Rev. 1.60 80 Deee 1 016 Rev. 1.60 81 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Compact Type TM Operating Modes The Compact T ype TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or T imer/Counter Mode. The operating mode is selected using the CT0M1 and CT0M0 bits in the CTM0C1 register. Compare Match Output Mode To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register , should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare match from Comparator A and a compare match from Comparator P . When the CT0CCLR bit is low , there are two ways in which the counter can be cleared. One is when a compare match from Comparator P , the other is when the CCRP bits are all zero which allows the counter to overflow . Here both CTMA0F and CTMP0F interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the CT0CCLR bit in the CTM0C1 register is high then the counter will be cleared when a compare match occurs from Com parator A. However , here onl y the CTMA0F interrupt re quest flag wil l be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CT0CCLR is high no CTMP0F interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMA0F interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTM0 output pin will change state. The CTM0 output pin condition however only changes state when a CTMA0F interrupt request flag is generated after a compare match occurs from Comparat or A. The CTMP0F interrupt request fla g, g enerated f rom a c ompare m atch o ccurs f rom C omparator P , wi ll h ave n o e ffect o n the CTM0 output pin. The way in which the CTM0 output pin changes state are determined by the condition of the CT0IO1 and CT0IO0 bits in the CTM0C1 register . The CTM0 output pin can be selected using the CT0IO1 and CT0IO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTM0 output pin, which is setup after the CT0ON bit changes from low to high, is setup using the CT0OC bit. Note that if the CT0IO1 and CT0IO0 bits are zero then no pin change will take place.

Rev. 1.60 80 Deee 1 016 Rev. 1.60 81 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CCRA CCRP 0x3FF Counte oveflow CCRA Int. Flag CTMA0F CCRP Int. Flag CTMP0F CCRP > 0 Counte leaed y CCRP value CTM0O/P Pin CT0ON Pause Counte Reset Output Pin set to Initial Level Low if CT0OC= 0 Output Toggle with CTMA0F flag Hee CT0IO[1:0] = 11 Toggle Output Selet Now CT0IO[1:0] = 10 Ative High Output Selet Output not affeted y CTMA0F flag. Reains High until eset y CT0ON it Compare Match Output Mode - CT0CCLR= 0 CT0CCLR= 0; CT0M[1:0] = 00 CT0PAU Resue Stop Tie CCRP > 0 CCRP = 0 CT0POL Output Pin Reset to initial value Output invets when CT0POL is high Output ontolled y othe pin-shaed funtion Counte Value Compare Match Output Mode - CT0CCLR=0 Note: 1. W ith CT0CCLR = 0, a Comparator P match will clear the counter 2. The CTM0 output pin controlled only by the CTMA0F flag 3. The output pin reset to initial state by a CT0ON bit rising edge

Rev. 1.60 8 Deee 1 016 Rev. 1.60 83 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CCRA CCRP 0x3FF CCRP Int. Flag CTMP0F CCRA Int. Flag CTMA0F CCRA > 0 Counte leaed y CCRA value CTM0O/P Pin CT0ON Pause Counte Reset Output Pin set to Initial Level Low if CT0OC= 0 Output Toggle with CTMA0F flag Hee CT0IO[1:0] = 11 Toggle Output Selet Now CT0IO[1:0] = 10 Ative High Output Selet Output not affeted y CTMA0F flag. Reains High until eset y CT0ON it Compare Match Output Mode - C0TCCLR = 1 CT0CCLR = 1; CT0M[1:0] = 00 CT0PAU Resue Stop Tie CCRA = 0 CT0POL Output Pin Reset to initial value Output invets when CT0POL is high Output ontolled y othe pin- shaed funtion Counte Value Output does not hange No CTMA0F flag geneated on CCRA oveflow CCRA = 0 Counte oveflow CTMP0F not geneated Compare Match Output Mode - CT0CCLR=1 Note: 1. W ith CT0CCLR = 1, a Comparator A match will clear the counter 2. The CTM0 output pin controlled only by the CTMA0F flag 3. The output pin reset to initial state by a CT0ON rising edge 4. The CTMP0F flags is not generated when CT0CCLR = 1

Rev. 1.60 8 Deee 1 016 Rev. 1.60 83 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Timer/Counter Mode To se lect t his m ode, bi ts CT0M1 and CT0M0 i n t he CTM0C1 regi ster shoul d be se t t o 1 1 respectively. The T imer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the T imer/Counter Mode the CTM0 output pin is not used. Therefore the above description and T iming Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTM0 output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register should be set to 10 respectively. The PWM function within the CTM0 is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTM0 output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely fl exible. In the P WM mode, the CT0CCLR bit has no ef fect on the P WM operation. Bot h of t he CCRA and CCRP re gisters a re use d t o ge nerate t he PW M wave form, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CT0DPX bit in the CTM0C1 register . The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The CT0OC bit In the CTM0C1 register is used to select the required polarity of the PWM waveform while the tw o CT0IO1 and CT0IO0 bits are used to enable the PWM output or to force the CTM0 output pin to a fixed high or low level. The CT0POL bit is used to reverse the polarity of the PWM output waveform. CTM, PWM Mode, Edge-aligned Mode, CT0DPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Peiod 18 6 384 1 640 768 896 104 Duty CCRA If fSYS = 16MHz, CTM0 clock source is fSYS/4, CCRP = 100b, CCRA =128, The CTM0 PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. CTM, PWM Mode, Edge-aligned Mode, CT0DPX=1 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Peiod CCRA Duty 18 6 384 1 640 768 896 104 The PWM output period is determi ned by the CCRA register value together with the CTM0 clock while the PWM duty cycle is defined by the CCRP register value.

Rev. 1.60 84 Deee 1 016 Rev. 1.60 8 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CCRP CCRA Counter Value Counter Clearedby CCRP CCRA Int. Flag CTMA0F CCRP Int. Flag CTMP0F CTM0 O/P Pin (CT0OC=1) CT0ON PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM Mode –CT0DPX = 0 Counter Stop If CT0ON bit low Counter reset when CT0ON returns high PWM resumes operationOutput controlled by Other pin-shared function Time CT0DPX=0; CT0M[1:0]=10 CT0POL Output Inverts When CT0POL = 1 CT0PAU ResumePause CTM0 O/P Pin (CT0OC=0) PWM Mode – CT0DPX = 0 Note: 1. Here CT0DPX = 0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when CT0IO[1:0] = 00 or 01 4. The CT0CCLR bit has no influence on PWM operation

Rev. 1.60 84 Deee 1 016 Rev. 1.60 8 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CCRA CCRP Counter Value Counter Cleared by CCRA CCRP Int. Flag CTMP0F CCRA Int. Flag CTMA0F CTM0 O/P Pin (CT0OC=1) CT0ON PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM Mode –CT0DPX = 1 Counter Stop If CT0ON bit low Counter reset when CT0ON returns high PWM resumes operationOutput controlled by Other pin-shared function Time CT0DPX=1; CT0M[1:0]=10 CT0POL Output Inverts When CT0POL = 1 CT0PAU ResumePause CTM0 O/P Pin (CT0OC=0) PWM Mode – CT0DPX = 1 Note: 1. Here CT0DPX = 1 - Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CT0IO[1:0] = 00 or 01 4. The CT0CCLR bit has no influence on PWM operation

Rev. 1.60 86 Deee 1 016 Rev. 1.60 87 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Periodic Type TM – PTM0 The Pe riodic T ype T M c ontains fiv e o perating m odes, wh ich a re C ompare Ma tch Ou tput, T imer/ Event Counter , Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with one external input pin and can drive two external output pins. /G43/G43/G52/G50 /G43/G43/G52/G41 /G50/G54 /G30 /G43/G43/G4C /G52 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G20/G50 /G20/G4D /G61/G74 /G63/G68 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G20/G41 /G20/G20 /G4D/G61 /G74/G63 /G68 /G50/G54 /G30/G43 /G4B/G32 /G7E/G50 /G54/G30 /G43/G4B /G30 /G50/G54 /G30/G4F /G4E /G50/G54 /G30 /G50/G41/G55 /G62/G30 /G7E/G62 /G39 /G31/G30 /G20/G2D /G62/G69 /G74/G20 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G20/G50 /G31/G30 /G20/G2D /G62/G69 /G74 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G20/G41 /G43 /G6F/G75/G6E /G74/G65 /G72/G20 /G43/G6C /G65/G61 /G72 /G31/G30 /G2D/G62 /G69/G74 /G20/G43 /G6F/G75/G6E/G74 /G2D/G75 /G70/G20 /G43/G6F /G75/G6E /G74/G65 /G72 /G50/G54 /G4D/G50 /G30/G46 /G20/G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G50/G54 /G4D/G41 /G30/G46 /G20/G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G50/G54 /G50/G20 /G50/G69 /G6E /G49 /G6E/G70/G75 /G74/G2F /G4F/G75 /G74/G70 /G75/G74 /G62/G30 /G7E/G62 /G39 /G45 /G64/G67/G65 /G44/G65 /G74/G65 /G63/G74 /G6F/G72 /G50/G54 /G30/G49 /G4F/G31 /G2C/G20/G50 /G54/G30 /G49/G4F /G30 /G50/G54 /G30/G4D /G31/G2C /G20/G50 /G54/G30 /G4D/G30 /G50/G54 /G30/G49 /G4F/G31 /G2C/G20/G50 /G54/G30 /G49/G4F /G30 /G50/G54 /G30/G50 /G4F/G4C /G50/G54 /G30/G4F /G43 /G50/G6F /G6C /G61/G72 /G69/G74 /G79 /G43 /G6F/G6E/G74 /G72/G6F /G6C /G4F/G75 /G74/G70 /G75/G74 /G43 /G6F/G6E/G74 /G72/G6F /G6C /G54/G50 /G31/G5F /G30 /G54/G43 /G4B/G31 /G31/G31 /G31 /G30/G30 /G30 /G30/G30 /G31 /G30/G31 /G30 /G30/G31 /G31 /G31/G30 /G30 /G31/G30 /G31 /G31/G31 /G30 /G66 /G53/G59/G53 /G2F/G34 /G66 /G53/G59/G53 /G66 /G48 /G2F/G31 /G36 /G66 /G48 /G2F/G36 /G34 /G66 /G53/G55 /G42 /G66 /G53/G55 /G42 /G30 /G31 /G30 /G31 /G50/G54 /G30/G43 /G4B/G53 /G54/G50 /G31/G5F/G30/G20 /G6F/G72 /G20/G54 /G50 /G31/G5F/G31 /G54/G50 /G31/G5F /G31 Periodic Type TM Block Diagram Periodic TM Operation At the core is a 10 count-up counter which is driven by a user selectable internal or external clock source. T here a re a lso t wo i nternal c omparators wi th t he na mes, Com parator A a nd Com parator P. T hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th C CRP a nd C CRA r egisters. T he CCRP comparator is 10-bit wide. The onl y way of changing the value of the 10-bit count er using the appl ication program , is to clear the counter by changing the PT0ON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur , a PTM0 interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control more than one output pin. All operating setup conditions are selected using relevant internal registers.

Rev. 1.60 86 Deee 1 016 Rev. 1.60 87 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the int ernal 10-bit CCRA val ue and CCRP val ue. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 PTM0C0 PT0PAU PT0CK PT0CK1 PT0CK0 PT0ON — — — PTM0C1 PT0M1 PT0M0 PT0IO1 PT0IO0 PT0OC PT0POL PT0CKS PT0CCLR PTM0DL D7 D6 D D4 D3 D D1 D0 PTM0AL D7 D6 D D4 D3 D D1 D0 PTM0RPL D7 D6 D D4 D3 D D1 D0 10-bit Periodic TM Register List PTM0C0 Register Bit 7 6 5 4 3 2 1 0 Nae PT0PAU PT0CK PT0CK1 PT0CK0 PT0ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PT0PAU: PTM0 Counter Pause Control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal counter operation. When in a Pause condition the PTM1 will remain powered up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6 ~ 4 PT0CK2 ~ PT0CK0: Select PTM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the PTM0. The external pin clock source can be chosen to be active on the rasing or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section.

Rev. 1.60 88 Deee 1 016 Rev. 1.60 89 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 3 PT0ON: PTM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/of f function of the PTM0. Setting the bit high enables the counter to run, clearing the bit disables the PTM0. Clearing this bit to zero will stop the counter from counting and turn of f the PTM0 which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. If the PTM0 is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PT0OC bit, when the PT0ON bit changes from low to high. Bit 2 ~ 0 Unimplemented, read as "0" PTM0C1 Register Bit 7 6 5 4 3 2 1 0 Nae PT0M1 PT0M0 PT0IO1 PT0IO0 PT0OC PT0POL PT0CKS PT0CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 6 PT0M1~PT0M0: Select PTM0 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: T imer/Counter Mode These bits setup the required operating mode for the PTM0. T o ensure reliable operation the PTM0 should be switched off before any changes are made to the bits. In the T imer/Counter Mode, the PTM0 output pin state is undefined. Bit 5 ~ 4 PT0IO1~PT0IO0: Select TP1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: T oggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0, TP1_1 or TCK1 01: Input capture at falling edge of TP1_0, TP1_1 or TCK1 10: Input capture at falling/rising edge of TP1_0, TP1_1 or TCK1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the PTM0 output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM0 is running.

Rev. 1.60 88 Deee 1 016 Rev. 1.60 89 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver In t he Co mpare Ma tch Out put Mod e, t he PT0IO1~PT0IO0 bi ts de termine ho w t he PTM0 output pin changes state when a compare match occurs from the Comparator A. The PTM0 output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the PT0IO1~PT0IO0 bits are both zero, then no change will take place on the output. The initial value of the PTM0 output pin should be setup using the PT0OC bit in the PTM0C1 r egister . No te t hat t he o utput l evel r equested b y t he PT0IO1~PT0IO0 b its must be different from the initial value setup using the PT0OC bit otherwise no change will oc cur on t he PTM1 ou tput pi n when a c ompare m atch oc curs. Aft er t he PTM0 output pin changes state it can be reset to its initial level by changing the level of the PT0ON bit from low to high. In the PWM Mode, the PT0IO1 and PT0IO0 bit s dete rmine how the PTM0 out put pin changes sta te when a cert ain compare m atch condi tion occurs. The PWM output func tion i s m odified by changing t hese t wo bi ts. It i s ne cessary t o c hange t he values of the PT0IO1 and PT0IO0 bits only after the PTM0 has been switched of f. Unpredictable PWM outputs will occur if the PT0IO1 and PT0IO0 bits are changed when the PTM0 is running. Bit 3 PT0OC: TP1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM0 output pin. Its operation depends upon whether PTM0 is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no ef fect if the PTM0 is in the T imer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM0 output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 PT0POL: TP1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTM0 output pin. When the bit is set high the PTM0 output pin will be inverted and not inverted when the bit is zero. It has no ef fect if the PTM0 is in the T imer/Counter Mode. Bit 1 PT0CKS: PTM0 capture trigger source select 0: From TP1_0, TP1_1 1: From TCK1 Bit 0 PT0CCLR: Select PTM0 Counter clear condition 0: PTM0 Comparatror P match 1: PTM0 Comparatror A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he Periodic T M c ontains t wo c omparators, Com parator A a nd Com parator P , e ither of which can be selected to clear the internal counter . W ith the PT0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low , the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PT0CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.

Rev. 1.60 90 Deee 1 016 Rev. 1.60 91 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver PTM0DL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 PTM0 Counter Low Byte Register bit 7 ~ bit 0 PTM0 10-bit Counter bit 7 ~ bit 0 PTM0DH Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 PTM0 Counter High Byte Register bit 1 ~ bit 0 PTM0 10-bit Counter bit 9 ~ bit 8 PTM0AL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 PTM0 CCRA Low Byte Register bit 7 ~ bit 0 PTM0 10-bit CCRA bit 7 ~ bit 0 PTM0AH Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 PTM0 CCRA High Byte Register bit 1 ~ bit 0 PTM0 10-bit CCRA bit 9 ~ bit 8 PTM0RPL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 PTM0 CCRP Low Byte Register bit 7 ~ bit 0 PTM0 10-bit CCRP bit 7 ~ bit 0

Rev. 1.60 90 Deee 1 016 Rev. 1.60 91 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver PTM0RPH Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 PTM0 CCRP High Byte Register bit 1 ~ bit 0 PTM0 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or T imer/Counter Mode. The operating mode is selected using the PT0M1 and PT0M0 bits in the PTM0C1 register. Compare Match Output Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register , should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare match from Comparator A and a compare match from Comparator P . When the PT0CCLR bit is low , there are two ways in which the counter can be cleared. One is when a compare match from Comparator P , the other is when the CCRP bits are all zero which allows the counter to overflow . Here both PTMA0F and PTMP0F interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PT0CCLR bit in the PTM0C1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However , here only the PTMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PT0CCLR is high no PTMP0F interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMA0F interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTM0 output pin, will change state. The PTM0 output pin condition however only changes state when a PTMA0F interrupt request flag is generated after a compare match occurs from Comparator A. The PTMP0F interrupt request flag, generated from a compare match occurs from Comparator P , will have no ef fect on the PTM0 output pin. The way in which the PTM0 output pin changes state are determined by the condition of the PT0IO1 and PT0IO0 bits in the PTM0C1 register . The PTM0 output pin can be selected using the PT0IO1 a nd PT0IO0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from Comparator A. The initial condition of the PTM0 output pin, which is setup afte r the PT0ON bit changes from low to high, is setup using the PT0OC bit. Note that if the PT0IO1 and PT0IO0 bits are zero then no pin change will take place.

Rev. 1.60 9 Deee 1 016 Rev. 1.60 93 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Counte Value 0x3FF CCRP CCRA PT0ON PT0PAU PT0POL CCRP Int. Flag PTMP0F CCRA Int. Flag PTMA0F PTM0 O/P Pin Tie CCRP=0 CCRP > 0 Counte oveflow CCRP > 0 Counte leaed y CCRP value Pause Resue Stop Counte Restat PT0CCLR = 0; PT0M [1:0] = 00 Output pin set to initial Level Low if PT0OC=0 Output Toggle with PTMA0F flag Note PT0IO [1:0] = 10 Ative High Output seletHee PT0IO [1:0] = 11 Toggle Output selet Output not affeted y PTMA0F flag. Reains High until eset y PT0ON it Output Pin Reset to Initial value Output Invets when PT0POL is highun-defined Compare Match Output Mode – PT0CCLR=0 Note: 1. W ith PT0CCLR=0 a Comparator P match will clear the counter 2. The PTM0 output pin is controlled only by the PTMA0F flag 3. The output pin is reset to itsinitial state by a PT0ON bit rising edge

Rev. 1.60 9 Deee 1 016 Rev. 1.60 93 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Counte Value 0x3FF CCRP CCRA PT0ON PT0PAU PT0POL CCRP Int. Flag PTMP0F CCRA Int. Flag PTMA0F PTM0 O/P Pin Tie CCRA=0 CCRA = 0 Counte oveflowCCRA > 0 Counte leaed y CCRA value Pause Resue Stop Counte Restat PT0CCLR = 1; PT0M [1:0] = 00 Output pin set to initial Level Low if PT0OC=0 Output Toggle with PTMA0F flag Note PT0IO [1:0] = 10 Ative High Output seletHee PT0IO [1:0] = 11 Toggle Output selet Output not affeted y PTMA0F flag. Reains High until eset y PT0ON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when PT0POL is high PTMP0F not geneated No PTMA0F flag geneated on CCRA oveflow Output does not hange Compare Match Output Mode – PT0CCLR=1 Note: 1. W ith PT0CCLR=1 a Comparator A match will clear the counter 2. The PTM output pin is controlled only by the PTMA0F flag 3. The output pin is reset to its initial state by a PT0ON bit rising edge 4. A PTMP0F flag is not generated when PT0CCLR=1

Rev. 1.60 94 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Timer/Counter Mode To se lect t his m ode, bi ts PT0M1 and PT0M0 i n t he PT M0C1 regi ster should be se t t o 1 1 respectively. The T imer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the T imer/Counter Mode the PTM0 output pin is not used. T herefore the above description a nd T iming Diagrams for the Compare Match Output Mode can be used to understand its function. PWM Output Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 10 respectively. The PWM function within the PTM0 is useful for applica tions which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM0 output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extre mely flexible. In the PWM Output Mode, the PT0CCLR bit has no ef fect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The PT0OC bit in the PTM0C1 register is used to select the required polari ty of the PWM waveform whi le the two PT0IO1 and PT0IO0 bi ts are used to enable the PWM output or to force the PTM0 output pin to a fixed high or low level. The PT0POL bit is used to reverse the polarity of the PWM output waveform. 10-bit PTM, PWM Mode, Edge-aligned Mode CCRP 1~1023 0 Peiod 1~103 104 Duty CCRA If fSYS = 16MHz, PTM0 clock source select fSYS/4, CCRP = 512 and CCRA = 128, The PTM0 PWM output frequency = (fSYS/4) /512 = fSYS/2048 =7.8125kHz, duty = 128/512 = 25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.

Rev. 1.60 94 Deee 1 016 Rev. 1.60 9 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Counte Value CCRP CCRA PT0ON PT0PAU PT0POL CCRP Int. Flag PTMP0F CCRA Int. Flag PTMA0F PTM0 O/P Pin (PT0OC=1) Tie Counte leaed y CCRP Pause Resue Counte Stop if PT0ON it low Counte Reset when PT0ON etuns high PT0M [1:0] = 10 PWM Duty Cyle set y CCRA PWM esues opeation Output ontolled y othe pin-shaed funtion Output Invets When PT0POL = 1 PWM Peiod set y CCRP PTM0 O/P Pin (PT0OC=0) PWM Output Mode Note: 1. A counter clear sets the PWM Period 2. The internal PWM function continues running even when PT0IO [1:0] = 00 or 01 3. The PT0CCLR bit has no influence on PWM operation

Rev. 1.60 96 Deee 1 016 Rev. 1.60 97 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Single Pulse Mode To select this mode, bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 10 respectively and also the PT0IO1 and PT0IO0 bits should be set to 1 1 respectively . The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM0 output pin. The trigger for the pulse output leading edge is a low to high transition of the PT0ON bit, which can be implem ented using the applicatio n program. However in the Single Pulse Mode, the PT0ON bit can also be made to automatically change from low to high using the external TCK1 pin, which will in turn initiate the Single Pulse output. When the PT0ON bit transition s to a high level, the counter will start running and the pulse leading edge will be generated. The PT0ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PT0ON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compa re match from Comparator A will also automatically clear the PT0ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM0 interrupt. The counter can only be res et back to zero w hen the PT0ON bit changes from low to high w hen the counter restarts. In the Single Pulse Mode CCRP is not used. The PT0CCLR bit is not used in this Mode. /G4C/G65/G61/G64/G69 /G6E/G67/G20 /G45/G64 /G67/G65 /G50/G54 /G30/G4F /G4E/G20 /G62/G69 /G74 /G30/G20 /GAE/G20 /G31 /G53/G2F /G57/G20 /G43/G6F /G6D/G6D /G61/G6E /G64 /G53/G45 /G54/G20 /G22/G50 /G54/G30 /G4F/G4E /G22 /G6F/G72 /G54/G43 /G4B/G31 /G20/G50 /G69/G6E /G20/G54 /G72/G61 /G6E/G73 /G69/G74 /G69/G6F /G6E /G50/G54 /G30/G4F /G4E/G20 /G62/G69 /G74 /G31/G20 /GAE/G20 /G30 /G53/G2F /G57/G20 /G43/G6F /G6D/G6D /G61/G6E /G64 /G43/G4C /G52/G20 /G22/G50 /G54/G30 /G4F/G4E /G22 /G6F/G72 /G43/G43/G52 /G41/G20 /G4D/G61 /G74/G63 /G68 /G20/G43 /G6F/G6D /G70/G61 /G72/G65 /G50/G75 /G6C/G73 /G65/G20 /G57/G69 /G64/G74 /G68 /G20/G3D /G20 /G43/G43/G52/G41 /G20/G56 /G61/G6C /G75/G65 /G54/G72 /G61 /G69/G6C/G69 /G6E/G67 /G20/G45 /G64/G67/G65 /G50/G54 /G4D/G30 /G20/G4F /G75/G74 /G70/G75/G74 /G20/G50 /G69/G6E Single Pulse Generation

Rev. 1.60 96 Deee 1 016 Rev. 1.60 97 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Counte Value CCRP CCRA PT0ON PT0PAU PT0POL CCRP Int. Flag PTMP0F CCRA Int. Flag PTMA0F PTM0 O/P Pin (PT0OC=1) Tie Counte stopped y CCRA Pause Resue Counte Stops y softwae Counte Reset when PT0ON etuns high Pulse Width set y CCRA Output Invets when PT0POL = 1 No CCRP Inteupts geneated PTM0 O/P Pin (PT0OC=0) TCK1 pin Softwae Tigge Cleaed y CCRA ath TCK1 pin Tigge Auto. set y TCK1 pin Softwae Tigge Softwae Clea Softwae TiggeSoftwae Tigge Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCK1 pin or by setting the PT0ON bit high 4. A TCK1 pin active edge will automatically set the PT0ON bit hight 5. In the Single Pulse Mode, PT0IO [1:0] must be set to "11" and can not be changed.

Rev. 1.60 98 Deee 1 016 Rev. 1.60 99 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Capture Input Mode To select this mode bits PT0M1 and PT0M0 in the PTM0C1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TP1_0, TP1_1 or TCK1 pin which is selected using the PT0CKS bit in the PTM0C1 register . The input pin active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the PT0IO1 and PT0IO0 bits in the PTM0C1 register . The counter is started when the PT0ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TP1_0, TP1_1 or TCK1 pin the present value in the c ounter wi ll be l atched i nto t he CCRA re gisters a nd a PTM0 i nterrupt ge nerated. Irre spective of what events occur on the TP1_0, TP1_1 or TCK1 pin, the counter will continue to free run until the P T 0ON bit changes from high to low . When a CCRP compare match occurs the counter w ill reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P , a PTM0 interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PT0IO1 and PT0IO0 bits can select the active trigger edge on the TP1_0, TP1_1 or TCK1 pin to be a rising edge, falling edge or both edge types. If the PT0IO1 and PT0IO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TP1_0, TP1_1 or TCK1 pin, however it must be noted that the counter will continue to run. As the TP1_0, TP1_1 or TCK1 pin is pin shared with other functions, care must be taken if the PTM0 is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be execu ted. The PT0CCLR, PT0OC and PT0POL bits are not used in this Mode.

Rev. 1.60 98 Deee 1 016 Rev. 1.60 99 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Counte Value YY CCRP PT0ON PT0PAU CCRP Int. Flag PTMP0F CCRA Int. Flag PTMA0F CCRA Value Tie Counte leaed y CCRP Pause Resue Counte Reset PT0M [1:0] = 01 PTM0 aptue pin TP1_0TP1_1 o TCK1 XX Counte Stop PT0IO [1:0] Value XX YY XX YY Ative edge Ative edge Ative edge 00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disale Captue Capture Input Mode Note: 1. PT0M [1:0] = 01 and active edge set by the PT0IO [1:0] bits 2. A PTM0 Capture input pin active edge transfers the counter value to CCRA 3. PT0CCLR bit not used 4. No output function – PT0OC and PT0POL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.

Rev. 1.60 100 Deee 1 016 Rev. 1.60 101 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin shared with the PA ~ PD logic I/O pins, with the desired function chosen via register bits. Keys are organised into several groups, with each group known as a module and having a module number , M0 to Mn. Each module is a fully independent set of four T ouch Keys and each Touch Key has its own oscillator . Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Device Keys - n Touch Key Module Touch Key Shared I/O Pin BS8B1A-3 1 M0 Key1~Key4 PB0~PB3 M1 Key~Key8 PB4~PB7 M Key9~Key1 PC0~PC3 BS8C16A-3 16 M0 Key1~Key4 PB0~PB3 M1 Key~Key8 PB4~PB7 M Key9~Key1 PC0~PC3 M3 Key13~Key16 PC4~PC7 BS8D0A-3 0 M0 Key1~Key4 PB0~PB3 M1 Key~Key8 PB4~PB7 M Key9~Key1 PD3 PD PC0 PC1 M3 Key13~Key16 PC~PC M4 Key17~Key0 PC6 PC7 PA4 PA1 Touch Key Register Definition Each touch key module, which contains four touch key functions, has its own suite registers. The following table shows the register set for each touch key module. The Mn within the register name refers to the T ouch Key module number, the BS82B12A-3 has a ra nge of M0 to M2, the BS82C16A-3 has a range of M0 to M3, the BS82D20A-3 has a range of M0 to M4. Name Usage TKTMR Touh Key 8-it tie/ounte egiste TKC0 Counte on-off and lea ontol/efeene lok ontol/Stat it TK16DL Touh key odule 16-it ounte low yte ontents TK16DH Touh key odule 16-it ounte high yte ontents TKC1 Touh key OSC fequeny selet TKMn16DL Module n 16-it ounte low yte ontents TKMn16DH Module n 16-it ounte high yte ontents TKMnROL Refeene OSC intenal apaito selet TKMnROH Refeene OSC intenal apaito selet TKMnC0 Contol Registe 0 Multiplexe Key Selet TKMnC1 Contol Registe 1 Key osillato ontol/Refeene osillato ontol/ Touh key o I/O selet Register Listing (n=0~4)

Rev. 1.60 100 Deee 1 016 Rev. 1.60 101 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Register Name Bit 7 6 5 4 3 2 1 0 TKTMR D7 D6 D D4 D3 D D1 D0 TKC0 — TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 TK16DL D7 D6 D D4 D3 D D1 D0 TK16DH D1 D14 D13 D1 D11 D10 D9 D8 TKMn16DL D7 D6 D D4 D3 D D1 D0 TKMn16DH D1 D14 D13 D1 D11 D10 D9 D8 TKMnROL D7 D6 D D4 D3 D D1 D0 TKMnC0 MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF MnSOF1 MnSOF0 TKMnC1 MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnKIO MnK1IO Touch Key Module (n=0~4) TKTMR Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch Key 8-bit timer/counter register Time slot counter overflow set-up time is (256-TKTMR[7:0])×32 TKC0 Register Bit 7 6 5 4 3 2 1 0 Nae — TKRCOV TKST TKCFOV TK16OV TSCS TK16S1 TK16S0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TKRCOV: T ime slot counter overflow flag 0: No overflow 1: Overflow If module 0 or all module time slot counter, selected by the TSCS bit, is overflow , the Touch Key Interrupt request flag, TKMF, will be set and all module key OSCs and ref OSCs auto stop. All module 16-bit C/F counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched off. Bit 5 TKST: Start T ouch Key detection control bit 0: Stopped 0->1: Started In all modules the16-bit C/F counter , 16-bit counter , 5-bit time slot counter will be automatically cleared when this bit is cleared to zero (8-bit programmable time slot counter will not be cleared, which overflow time is setup by user). When this bit changes from low to high, the 16-bit C/F counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically on and enable key OSC and ref OSC output clock input to these counters. Bit 4 TKCFOV: T ouch key module 16-bit C/F counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by application program.

Rev. 1.60 10 Deee 1 016 Rev. 1.60 103 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 3 TK16OV: T ouch key module 16-bit counter overflow flag 0: Not overflow 1: Overflow This bit must be cleared by application program. Bit 2 TSCS: T ouch Key time slot counter select 0: Each Module uses its own time slot counter. 1: All T ouch Key Module use Module 0 time slot counter. Bit 1~0 TK16S1~ TK16S0: The touch key module 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 TKC1 Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~2 Unimplemented, read as "0" Bit 1~0 TKFS1~TKFS0: Touch key OSC frequency select 00: 500kHz 01: 1000 kHz 10: 1500 kHz 11: 2000 kHz TK16DL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch key module 16-bit counter low byte contents TK16DH Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Touch key module 16-bit counter high byte contents TKMn16DL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Module n 16-bit counter low byte contents

Rev. 1.60 10 Deee 1 016 Rev. 1.60 103 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver TKMn16DH Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Module n 16-bit counter high byte contents TKMnROL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D6 D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Reference OSC inernal capacitor select OSC inernal capacitor select : (TKMnRO[9:0] × 50pF) / 1024 TKMnROH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 Reference OSC inernal capacitor select OSC inernal capacitor select: (TKMnRO[9:0] × 50pF) / 1024 TKMnC0 Register Bit 7 6 5 4 3 2 1 0 Nae MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF MnSOF1 MnSOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~6 MnMXS1~MnMXS0: Multiplexer Key Select Bit Module Number MnMXS1 MnMXS0 M0 M1 M2 M3 M4 0 0 Key 1 Key Key 9 Key 13 Key 17 0 1 Key Key 6 Key 10 Key 14 Key 18 1 0 Key 3 Key 7 Key 11 Key 1 Key 19 1 1 Key 4 Key 8 Key 1 Key 16 Key 0 Bit 5 MnDFEN: Multi-frequency control 0: Disable 1: Enable Bit 4 MnFILEN: Filter function control 0: Disable 1: Enable Bit3 MnSOFC: C to F OSC frequency hopping function control 0: The frequency hopping function is controlled by MnSOF2 ~ MnSOF0 bits 1: The frequency hopping function is controlled by hardware regardless of what is the state of MnSOF2~ MnSOF0 bits

Rev. 1.60 104 Deee 1 016 Rev. 1.60 10 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 2~0 MnSOF2 ~ MnSOF0: Slelecting key OSC and ref OSC frequency as C to F OSC is controlled by software 000: 1380kHz 001: 1500kHz 010: 1670kHz 011: 1830kHz 100: 2000kHz 101: 2230kHz 110: 2460kHz 111: 2740kHz The frequency which is mentioned here willl be changed when the exte rnal or internal capacitor is with dif ferent value. If the touch key operates at a frequency of 2MHz, users can adjust the frequency in scale when select other frequency. TKMnC1 Register Bit 7 6 5 4 3 2 1 0 Nae MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnKIO MnK1IO R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7 MnTSS: Time slot counter clock select 0: Reference oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 MnROEN: Reference OSC control 0: Disable 1: Enable Bit 4 MnKOEN: Key OSC control 0: Disable 1: Enable Bit 3~0 MnK4IO~ MnK1IO: I/O pin or touch key function select MnK4IO M0 M1 M2 M3 M4 PB3/Key 4 PB7/Key 8 PC3/Key 12 or PC1/Key 12 PC7/Key 16 or PC5/Key 16 PA1/Key 20

0 I/O

1 Touh key

PB2/Key 3 PB6/Key 7 PC2/Key 11 or PC0/Key 11 PC6/Key15 or PC4/Key 15 PA4/Key 19 PB1/Key 2 PB5/Key 6 PC1/Key 10 or PD2/Key 10 PC5/Key 14 or PC3/Key 14 PC7/Key 18 PB0/Key 1 PB4/Key 5 PC0/Key 9 or PD3/Key 9 PC4/Key 13 or PC2/Key 13 PC6/Key 17

1 Touh key input

Rev. 1.60 104 Deee 1 016 Rev. 1.60 10 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Touch Key Operation When a finge r t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. By using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch actions can be sensed by mea suring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. Each touch key module contains four touch key inputs w hich are shared logical I/O pins , and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. There are therefore four sense oscillators within each touch key module. During this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a T ouch Key interrupt signal will be generated. Using the TSCS bit in the TKC0 register can select the module 0 time slot counter as the time slot counter for a ll m odules. Al l m odules use t he sa me st arted si gnal. T he16-bit C/ F c ounter, 16- bit counter, 5-bit time slot counter in all modules will be automatically cleared when this bit is cleared to zero, but the 8-bit programmable time slot counter will not be cleared. The overflow time is setup by user. When this bit changes from low to high, the 16-bit C/F counter , 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be automatically stopped and the 16-bit C/F counte r, 16-bit counter , 5-bit time slot counter and 8-bit time slot timer counter will be automatically switched of f when the 5-bit time slot counter overflows. The clock source for the time slot c ounter and 8+5 bi t count er, i s sourc ed from t he refe rence osc illator or fSYS/4. The refe rence oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time s lot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module consists of four touch keys, Key1 ~ Key4 are contained in module 0, Key5 ~ Key8 are contained in module 1, Key9 ~ Key12 are contained in module 2, Key13 ~ Key16 are contained in the module 3 and Key17 ~ Key20 are contained in the module 4. Each touch key module has an identical structure.

Rev. 1.60 106 Deee 1 016 Rev. 1.60 107 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver KEY 1 KEY KEY 3 KEY 4 KEY OSC KEY OSC KEY OSC KEY OSC MUX. Filte Oveflow 16-it ounte OveflowfSYSfSYS/fSYS/4fSYS/8 TK16S1~TK16S0 -it tie slot ounte Oveflow8-it tie slot tie ounte Ref OSC MUX. fSYS/4 MnTSS 8-it tie slot tie ounte peload egiste Oveflow Multi- fequeny 16-it C/F ounte Note: 1. Each touch key module contains the content in the red dash line. 2. The content in the black dash line is the module number (0~n). Each module contains 4 touch keys. Touch Key Module Block Diagram

Rev. 1.60 106 Deee 1 016 Rev. 1.60 107 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver The touch key sense oscilltor and reference oscillator timing diagram is shown in the following figure: TKST MnKOEN MnROEN KEY OSC CLK Refeene OSC CLK fCFTMCK enale fCFTMCK (MnDFEN=0) fCFTMCK (MnDFEN=1) TKRCOV Set Touh Key inteupt equest flag Hadwae lea to "0" (6-TKTMR) oveflow *3 /G54/G6F /G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G4D/G30 /G4B/G34 /G49/G4F /G20/G62 /G69/G74 /G4D/G30 /G4B/G33 /G49/G4F /G20/G62 /G69/G74 /G4D/G30 /G4B/G32 /G49/G4F /G20/G62 /G69/G74 /G4D/G30 /G4B/G31 /G49/G4F /G20/G62 /G69/G74 /G45/G78 /G74/G65 /G72/G6E /G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54/G6F /G75/G63 /G68/G20 /G4B/G65 /G79 /G54/G6F /G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G45/G78 /G74/G65 /G72/G6E /G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54/G6F /G75/G63 /G68/G20 /G4B/G65 /G79 /G54/G6F /G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G45/G78 /G74/G65 /G72/G6E /G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54/G6F /G75/G63 /G68/G20 /G4B/G65 /G79 /G54/G6F /G75/G63 /G68/G20 /G43/G69 /G72/G63 /G75/G69 /G74/G73 /G4C/G6F/G67/G69 /G63 /G20/G49/G2F /G4F/G20 /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G45/G78 /G74/G65 /G72/G6E /G61/G6C /G20/G50 /G69/G6E /G49/G2F/G4F /G20/G6F /G72/G20 /G54/G6F /G75/G63 /G68/G20 /G4B/G65 /G79 Touch Key or I/O Function Select

Rev. 1.60 108 Deee 1 016 Rev. 1.60 109 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Touch Key Interrupt The touch key only has single inter rupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned he re a re t he ke ys whi ch a re e nabled. T he 16-bit C/ F c ounter, 16-bi t c ounter, 5-bi t t ime slot counter and 8-bit time slot counter in all modules will be automatically cleared. The TKCFOV flag, which is the 16-bit C/F counter overflow flag will go high when any of the Touch K ey M odule 16-bit C/F counter overfl ows. As this fl ag w ill not be automatically cleared, it has to be cleared by the application program. Module 0 only contains one 16-bit counter. The TK16OV flag, which is the 16-bit counter overflow flag, will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the appl ication program. More details regarding the touch key interrupt is located in the interrupt section of the datasheet. Programming Considerations After t he rel evant regi sters are se tup, t he t ouch key det ection process i s i nitiated t he cha nging t he TKST bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag, whi ch i s t he t ime sl ot c ounter fla g wi ll go hi gh a nd re main hi gh unt il t he c ounter ove rflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.

Rev. 1.60 108 Deee 1 016 Rev. 1.60 109 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory e tc. Or iginally d eveloped b y Ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. /G44/G65 /G76/G69 /G63/G65 /G53/G6C /G61/G76 /G65 /G44/G65 /G76/G69 /G63/G65 /G4D/G61 /G73/G74 /G65/G72 /G44/G65 /G76/G69 /G63/G65 /G53/G6C /G61/G76 /G65 /G56/G44 /G44 /G53/G44 /G41 /G53/G43 /G4C I2C Master/Slave Bus Connection /G49 /G32 /G43/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G28/G49 /G49 /G43/G44/G29 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G28 /G49/G49/G43 /G41/G29 /G53/G68 /G69/G66 /G74/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G44/G69 /G72/G65 /G63/G74 /G69/G6F /G6E/G20 /G43/G6F /G6E/G74 /G72/G6F /G6C /G4D /G55 /G58 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G4D/G61 /G74/G63 /G68 /G49/G49/G43 /G48/G41 /G41/G53/G20 /G42/G69 /G74 /G49 /G32 /G43/G20 /G49/G6E /G74/G65 /G72/G72 /G75/G70 /G74 /G44/G61 /G74/G61 /G20/G69 /G6E/G20 /G4D /G53/G42/G20 /G44/G61 /G74/G61 /G20/G4F /G75 /G74/G20/G20 /G4D/G53 /G42 /G54/G72 /G61/G6E /G73/G6D /G69/G74 /G2F/G52 /G65/G63 /G65/G69 /G76/G65 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G55/G6E /G69/G74 /G38/G2D /G62/G69 /G74/G20/G44 /G61/G74 /G61/G20 /G43/G6F /G6D/G70 /G6C/G65 /G74/G65 /G44/G65 /G74/G65 /G63/G74 /G20/G53 /G74/G61 /G72/G74 /G20/G6F /G72/G20 /G53/G74 /G6F/G70 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G41/G64 /G64/G72 /G65/G73 /G73 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G49/G49/G43 /G54 /G58/G41/G4B /G52/G65 /G61/G64 /G2F/G77 /G72/G69 /G74/G65 /G20/G53 /G6C/G61 /G76/G65 /G49/G49/G43 /G53/G52 /G57/G20 /G42/G69 /G74 /G49/G49/G43 /G48/G42 /G42/G20 /G42/G69 /G74 /G49/G49/G43 /G48/G54 /G58/G20 /G42/G69 /G74 /G49/G49/G43 /G48/G43/G46 /G20/G42 /G69/G74 /G44 /G65/G62/G6F/G75/G6E /G63/G65 /G43/G69 /G72/G63 /G75/G69 /G74/G72 /G79 /G53/G43 /G4C/G20 /G50/G69 /G6E /G53/G44 /G41/G20 /G50/G69 /G6E /G66 /G53/G59 /G53 /G49/G32 /G43/G44/G42 /G4E/G43/G31 /G26 /G49/G32 /G43/G44/G42 /G4E/G43/G30 /G49/G32 /G43/G54 /G4F/G46 /G20/G62 /G69/G74 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G43 /G6F/G6E/G74 /G72/G6F /G6C /G49/G32 /G43/G54 /G4F/G46 /G41 /G64/G64/G72 /G65/G73 /G73/G20 /G4D/G61 /G74/G63 /G68 /G49/G32 /G43/G54 /G4F/G45 /G4E /G66 /G53/G55 /G42 I2C Block Diagram I2C Interface Operation The I2C serial interface is a two line interf ace, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two device s communicate with each other on the bidirectional I2C bus, one is known as the master de vice a nd one a s t he sl ave de vice. Bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. It i s sugge sted t hat t he use r sha ll not e nter t he m icro proc essor t o HAL T status by a pplication program during processing I2C communication. If the pin is configured to SDA or SCL function of I2C interface, the pin is configured to open-collect Input/Output port and its Pull-high function can be enabled by programming the related Generic Pull-high Control Register.

Rev. 1.60 110 Deee 1 016 Rev. 1.60 111 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver /G53/G54 /G41/G52 /G54/G20 /G73/G69 /G67/G6E/G61/G6C /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G53/G65 /G6E/G64 /G20/G73 /G6C/G61 /G76/G65 /G20 /G61/G64/G64 /G72/G65 /G73/G73 /G61/G6E/G64/G20 /G52/G2F /G57/G20 /G62/G69 /G74 /G20/G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G41 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65 /G66/G72 /G6F/G6D /G20/G73 /G6C/G61 /G76/G65 /G53 /G65/G6E/G64/G20 /G64/G61/G74 /G61/G20 /G62/G79 /G74/G65 /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G41 /G63/G6B /G6E/G6F/G77 /G6C /G65/G64/G67 /G65 /G66/G72 /G6F/G6D /G20/G73 /G6C/G61 /G76/G65 /G53/G54 /G4F/G50 /G20/G73 /G69/G67 /G6E/G61 /G6C /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 The I2 CDBNC1 a nd I2 CDBNC0 B its d etermine t he de bounce t ime o f t he I2C i nterface. T his u ses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. T he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. T o achieve the required I2C data trans fer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Deoune fSYS > MHz fSYS > MHz syste lok deoune fSYS > 4MHz fSYS > 10MHz 4 syste lok deoune fSYS > 8MHz fSYS > 0MHz I2C Minimum fSYS Frequency I2C Registers There are four control registers associated with the I2C bus, IICC0, IICC1, IICA and I2CT OC and one data register , IICD. The IICD register is used to store the data being transmitted and received on the I2C bus. Before the microcontro ller writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register . After the data is received from the I2C bus, the microcontroller can read it from the IICD register . Any transmission or reception of data from the I2C bus must be made via the IICD register. Register Name Bit 7 6 5 4 3 2 1 0 IICC0 — — — — ICDBNC1 ICDBNC0 IICEN — IICC1 IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICAMWU IICRXAK IICD IICD7 IICD6 IICD IICD4 IICD3 IICD IICD1 IICD0 IICA IICA6 IICA IICA4 IICA3 IICA IICA1 IICA0 — ICTOC ICTOEN ICTOF ICTOS ICTOS4 ICTOS3 ICTOS ICTOS1 ICTOS0 I2C Registers List

Rev. 1.60 110 Deee 1 016 Rev. 1.60 111 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver IICC0 Register Bit 7 6 5 4 3 2 1 0 Nae — — — — ICDBNC1 ICDBNC0 IICEN — R/W — — — — R/W R/W R/W — Bit 7~4 Unimplemented, read as "0" Bit 3~2 I2CDBNC1~I2CDBNC0: I2C Debounce T ime Selection 00: No debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce Bit 1 IICEN: I2C Control 0: Disable 1: Enable Bit 0 Unimplemented, read as "0" The I2C function could be turned of f or turned on by controlling the bit IICEN. When the pin- shared I/O ports are chosen to be the functions other than SDA and SCL by clearing the IICEN bit to zero, the I2C function is turned of f and its operating current will be reduced to a minimum value. In contrary, the I2C function is turned on when the pin-shared I/O ports are chosen to be the SDA and SCL pins by setting the IICEN bit high. IICC1 Register Bit 7 6 5 4 3 2 1 0 Nae IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICAMWU IICRXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 IICHCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The I ICHCF fla g i s t he d ata t ransfer fla g. T his fla g wi ll b e z ero wh en d ata i s b eing transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Below is an example of the flow of a two-byte I2C data transfer. First, the I2C sla ve de vice re ceives a sta rt signal from the I2C m aster a nd t hen the IICHCF b it i s a utomatically c leared t o z ero. Se cond, the I2C sl ave d evice fi nishes receiving the 1st data byte and then the IICHCF bit is automatically set to one. Third, users read the 1st data byte from the IICD register by the application program and then the IICHCF bit is automatically cle ared to zero. Fourth, the I2C slave device finishes receiving the 2nd data byte and then the IICHCF bit is automatically set high and so on. Finally, the I2C slave device receives a stop signal from the I2C master and then the IICHCF bit is automatically set high. Bit 6 IICHAAS: I2C Bus address match flag 0: Not address match 1: Address match The IICHASS flag is the address match flag. This flag is used to determine if the slave device address is same as the maste r transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low.

Rev. 1.60 11 Deee 1 016 Rev. 1.60 113 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 5 IICHBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The IICHBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a ST ART signal is detected. The flag will be set to " 0" when the bus is free which will occur when a STOP signal is detected. Bit 4 IICHTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 IICTXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The IICTXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. T he sl ave d evice m ust a lways clear t he I ICTXAK b it t o zero b efore f urther data is received. Bit 2 IICSRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The II CSRW fl ag i s t he I2C Sl ave R ead/Write fl ag. T his fl ag de termines whe ther the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the IICHAAS flag is set high, the slave device will check the IICSR W flag to determine whether it should be in transmit mode or receive mode. If the IICSR W flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the IICSRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IICAMWU: I2C Address Match Control 0: Disable 1: Enable – must be cleared by the application program after wake-up. This Bit should be set to “1” to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU Bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this Bit must be cleared by application program after wake-up to ensure correction device operation. Bit 0 IICRXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The IICRXAK flag is the receiver acknowledge flag. When the IICRXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock , after 8 bits of data have been transm itted. When the sla ve device in the transm it mode, the sl ave device checks the IICRXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the IICRXAK flag is "1". When this occurs, the slave transmitter will relea se the SDA line to allow the master to send a STOP signal to release the I2C Bus.

Rev. 1.60 11 Deee 1 016 Rev. 1.60 113 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver I2CTOC Register Bit 7 6 5 4 3 2 1 0 Nae ICTOEN ICTOF ICTOS ICTOS4 ICTOS3 ICTOS ICTOS1 ICTOS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 I2CTOEN: I2C Time-out Countrol 0: Disable 1: Enable Bit 6 IICTOF: I2C T ime-out flag 0: No time-out occurred 1: T ime-out occurred This bit is set high when time-out occurs and can only be cleared by application program. Bit 5~0 I2CTOS5~I2CTOS0: I2C T ime-out period selection I2C time-out clock source is fSUB/32. I2C time-out period is equal to (I2CTOS[5 : 0]+1) × (32/fSUB) The IICD register is used to store the data being transmitted and received. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register . After the data is received from the I2C bus, the device can read it from the IICD register . Any transmission or reception of data from the I2C bus must be made via the IICD register. IICD Register Bit 7 6 5 4 3 2 1 0 Nae IICD7 IICD6 IICD IICD4 IICD3 IICD IICD1 IICD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown IICA Register Bit 7 6 5 4 3 2 1 0 Nae IICA6 IICA IICA4 IICA3 IICA IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR 0 0 0 0 0 0 0 — Bit 7~1 IICA6~IICA0: I2C slave address IICA6~ IICA0 is the I2C slave address bit 6 ~ bit 0. The IICA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the IICA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the IICA register, the slave device will be selected. Bit 0 Unimplemented, read as "0"

Rev. 1.60 114 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver I2C Bus Communication Communication on the I2C bus requires four separate steps, a ST ART signal, a slave device address transmission, a data transmission and finally a ST OP signal. When a ST ART signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the IICHAAS bit in the IICC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service rout ine, t he sl ave de vice m ust fi rst c heck t he c ondition of t he IICHAAS and I2CT OF bits to determine whether the interrupt source originates from an address match or from an I2C communication time-out or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the IICSR W bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this:

Step 1 Set the IICEN bit in the IICC0 register high to enable the I2C bus.
Step 2 Write the slave address of the device to the I2C bus address register IICA.
Step 3 Set the IICE interrupt enable bit of the interrupt control register to enable the I2C interrupt. /G53/G74 /G61/G72 /G74 /G20/G20 /G57/G72 /G69/G74 /G65/G20 /G53/G6C /G61/G76 /G65 /G20/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G74/G6F /G20 /G49/G49/G43 /G41 /G53/G45 /G54/G20 /G49/G49 /G43/G45 /G4E /G20/G20/G20/G49 /G32 /G43/G20 /G42/G75 /G73 /G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G3D/G3F /G20 /G45/G6E /G61/G62/G6C /G65 /G44/G69 /G73 /G61/G62/G6C /G65 /G53/G45 /G54/G20 /G49/G49 /G43/G45 /G20 /G57/G61 /G69/G74 /G20/G66/G6F /G72 /G20/G49/G6E /G74/G65 /G72/G72 /G75/G70 /G74 /G47/G6F /G74/G6F /G20/G4D /G61/G69 /G6E/G20 /G50/G72 /G6F/G67/G72 /G61/G6D /G43/G4C /G52/G20 /G49/G49 /G43/G45 /G20 /G50 /G6F/G6C /G6C/G20 /G49/G49/G43 /G46 /G20/G74/G6F /G20/G64 /G65/G63 /G69/G64 /G65/G20 /G77/G68 /G65/G6E /G20/G74/G6F /G20/G67 /G6F /G20/G74/G6F /G20/G49 /G32 /G43/G20 /G42/G75 /G73/G20 /G49/G53 /G52/G20 /G47/G6F /G74/G6F /G20/G4D /G61/G69 /G6E/G20 /G50/G72 /G6F/G67/G72 /G61/G6D I2C Bus Initialisation Flow Chart I2C Bus Start Signal The ST ART signal can only be generated by the master device connec ted to the I2C bus and not by the slave device. This ST ART signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the IICHBB bit will be set. A ST ART condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high.

Rev. 1.60 114 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Slave Address The t ransmission o f a ST ART si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he I2C b us. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the ST ART signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal wil l be generat ed. The next bit fol lowing the address, which is the 8th bit, defines the read/write status and will be saved to the IICSR W bit of the IICC1 register . The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag IICHAAS when the addresses match. As a n I2C bus i nterrupt c an c ome fro m three sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the IICHAAS and I2CT OF bits should be examined to see whether the interrupt source has come from a matching slave address or from an I2C communication time-out or from the completion of a data byte transfer . When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register , or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line. I2C Bus Read/Write Signal The IICSR W bit in the IICC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver . If the IICSR W flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitte r. If the IICSR W flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After t he m aster ha s t ransmitted a c alling a ddress, a ny sla ve de vice on t he I2C bus, whose own internal a ddress m atches t he c alling a ddress, m ust g enerate a n a cknowledge si gnal. T he a cknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a ST OP signal must be transmitted by the master to end the communication. When the IICHAAS flag is high, the addresses have matched and the slave device must check the IICSR W flag to determine if it is to be a transmitter or a receiver . If the IICSR W flag is high, the slave device should be setup to be a transmitter so the IICHTX bit in the IICC1 register should be set high. If the IICSR W flag is low , then the microcontroller slave device should be setup as a receiver and the IICHTX bit in the IICC1 register should be cleared to zero. I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. T he o rder o f se rial b it t ransmission i s t he MSB fir st a nd t he L SB l ast. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the SDA line to allow the master to send a ST OP signal to release the I2C Bus. The corresponding data will be stored in the IICD register. If setup as a transmitter , the slave device must first write the data to be transmitted into the IICD register . If setup as a receiver , the slave device must read the transmitted data from the IICD register.

Rev. 1.60 116 Deee 1 016 Rev. 1.60 117 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver When the slave receiver receives the data byte, it must generate an acknowledge bit, known as IICTXAK, o n t he 9 th c lock. T he sl ave d evice, wh ich i s se tup a s a t ransmitter wi ll c heck t he IICRXAK bit in the IICC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. /G44/G61 /G74/G61 /G31/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30 /G30 /G31 /G30 /G30/G31/G30/G31/G30 /G31 /G31 /G53/G3D /G53/G74 /G61/G72 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G53/G41/G3D /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G28/G37 /G20/G62 /G69/G74 /G73/G29 /G53/G52 /G3D/G49 /G49/G43 /G53/G52 /G57/G20 /G62/G69 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G4D/G3D /G53/G6C /G61/G76 /G65/G20 /G64/G65 /G76/G69 /G63/G65 /G20/G73 /G65/G6E/G64/G20 /G61 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65/G20 /G62/G69 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G44/G3D /G44/G61 /G74/G61 /G20/G28 /G38 /G20/G62 /G69/G74 /G73/G29 /G41/G3D /G41/G43 /G4B/G20 /G28/G49 /G49 /G43/G52/G58 /G41/G4B /G20/G62 /G69 /G74/G20/G66 /G6F/G72 /G20/G74/G72 /G61/G6E/G73 /G6D/G69 /G74/G74 /G65/G72 /G2C /G20/G49/G49 /G43/G54 /G58/G41/G4B /G20/G62 /G69/G74 /G20/G66 /G6F/G72 /G20/G72 /G65/G63 /G65/G69 /G76/G65 /G72/G20 /G31/G20 /G62/G69 /G74/G29 /G50/G3D /G53/G74 /G6F/G70 /G20/G28 /G31/G20 /G62/G69 /G74/G29 /G53/G43 /G4C /G53/G74 /G61/G72 /G74 /G53/G44 /G41 /G49/G49 /G43/G53 /G52/G57 /G41/G43 /G4B /G41/G43 /G4B/G53 /G74/G6F /G70 /G53/G43 /G4C /G53/G44 /G41 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73 /G53/G53 /G41/G53 /G52 /G4D/G44 /G41 /G44/G41 /G53/G53 /G41/G53 /G52 /G4D/G44 /G41 /G44/G41 /G50 Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register , or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line. I2C Communication Timing Diagram /G49/G49 /G43/G48/G54 /G58/G3D /G31/G20 /G3F /G49/G49 /G43/G53 /G52/G57 /G3D/G31 /G20/G3F /G59/G65 /G73 /G4E/G6F /G49/G49 /G43/G52 /G58/G41/G4B /G3D/G31 /G3F /G59/G65 /G73 /G4E/G6F /G4E/G6F /G52 /G65/G61/G64 /G20/G66/G72 /G6F/G6D /G49/G49/G43 /G44/G20 /G74/G6F /G20/G72 /G65/G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G6C/G69/G6E /G65 /G52/G45 /G54/G49 /G59/G65 /G73 /G44/G75 /G6D/G6D /G79/G20 /G72 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G49/G49 /G43/G44 /G20/G74 /G6F/G20 /G72/G65 /G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G52/G45 /G54/G49 /G52/G45 /G54/G49 /G57/G72 /G69/G74 /G65/G20 /G64/G61 /G74/G61 /G20/G74/G6F /G20/G49/G49 /G43/G44 /G72/G65 /G6C /G65/G61/G73 /G65/G20 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G53/G45 /G54/G20 /G49/G49 /G43/G48/G54 /G58 /G57/G72 /G69/G74 /G65/G20 /G64/G61 /G74/G61 /G20/G74/G6F /G20/G49/G49 /G43/G44 /G74/G6F /G20/G72 /G65/G6C /G65/G61 /G73/G65 /G20/G53 /G43/G4C /G20/G4C /G69/G6E /G65 /G52/G45 /G54/G49 /G43/G4C /G52/G20 /G49/G49 /G43/G48 /G54/G58 /G43/G4C /G52/G20 /G49/G49 /G43/G54 /G58/G41 /G4B /G53/G74 /G61/G72 /G74 /G44/G75 /G6D/G6D /G79/G20 /G72 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G49/G49/G43 /G44/G20 /G74/G6F /G20/G72 /G65/G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G43/G4C /G52/G20 /G49/G49 /G43/G48/G54 /G58 /G43/G4C /G52/G20 /G49/G49 /G43/G54 /G58/G41/G4B /G52/G45 /G54/G49 /G49/G49 /G43/G48 /G41/G41/G53/G3D /G31 /G3F /G59/G65 /G73 /G4E/G6F /G49/G32 /G43/G54 /G4F/G46 /G3D/G31 /G20/G3F /G59/G65 /G73 /G4E/G6F /G53/G45/G54 /G20/G49 /G32/G43 /G54/G4F /G45/G4E /G43/G4C /G52/G20 /G49/G32 /G43/G54 /G4F/G46 /G52/G45 /G54/G49 I2C Bus ISR Flow Chart

Rev. 1.60 116 Deee 1 016 Rev. 1.60 117 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver I2C Interface Time-out Function In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, clock, a time-out function is provided. If the clock source to the I2C is not received then after a fixed time period, the I2C circuitry and registers will be reset. /G44/G61 /G74/G61 /G31/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30 /G30 /G31 /G30 /G30/G31/G30/G31/G30 /G31 /G31 /G53/G3D /G53/G74 /G61/G72 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G53/G41/G3D /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G28/G37 /G20/G62 /G69/G74 /G73/G29 /G53/G52 /G3D/G53 /G52/G57 /G20/G62 /G69 /G74/G20/G28 /G31/G20 /G62/G69 /G74/G29 /G4D/G3D /G53/G6C /G61/G76 /G65/G20 /G64/G65 /G76/G69 /G63/G65 /G20/G73 /G65/G6E/G64/G20 /G61 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65/G20 /G62/G69 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G44/G3D /G44/G61 /G74/G61 /G20/G28 /G38/G20 /G62/G69 /G74/G73 /G29 /G41/G3D /G41/G43 /G4B /G20/G28 /G52/G58 /G41/G4B /G20/G62 /G69/G74 /G20/G66 /G6F/G72 /G20/G74 /G72/G61 /G6E/G73 /G6D/G69 /G74/G74 /G65/G72 /G2C/G20 /G54/G58 /G41/G4B /G20/G62 /G69/G74 /G20/G66 /G6F/G72 /G20/G72 /G65/G63 /G65/G69 /G76/G65 /G72/G20 /G31/G20 /G62/G69 /G74/G29 /G50/G3D /G53/G74 /G6F /G70 /G20 /G28 /G31/G20 /G62/G69 /G74 /G29 /G53/G43 /G4C /G53/G74 /G61/G72 /G74 /G53/G44 /G41 /G49/G49 /G43/G53 /G52/G57 /G41/G43 /G4B /G41/G43 /G4B /G53/G74 /G6F/G70 /G53/G43 /G4C /G53/G44 /G41 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73 I2C Time-out When an I2C time -out counte r overflow occurs, the counter will stop and the I2CT OEN bit will be cleared to zero and the I2CTOF bit will be set high to indicate that a time-out condition as occurred. The time-out c ondition wi ll a lso ge nerate a n i nterrupt whi ch use s t he I2C i nterrrupt ve ctor. W hen an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out IICD IICA IICC0 No hange IICC1 Reset to POR ondition I2C Registers After Time-out The I2CT OF fl ag can be cleared by the application program. There are 64 time-out periods w hich can be selected using bits in the I2CTOC register. The time-out time is given by the formula: This gives a range of about 1ms to 64ms.

Rev. 1.60 118 Deee 1 016 Rev. 1.60 119 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver UART Interface The devices conta in an integrated full-duplex asynchronous serial communications UAR T interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UAR T function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features:

Full-duplex, Universal Asynchronous Receiver and T ransmitter (UART) communication
8 or 9 bits character length
Even, odd or no parity options
One or two stop bits
Baud rate generator with 8-bit prescaler
Parity, framing, noise and overrun error detection
Support for interrupt on address detect (last character bit=1)
Transmitter and receiver enabled independently
2-byte Deep FIFO Receive Data Buffer
Transmit and Receive Multiple Interrupt Generation Sources: ♦ Transmitter Empty ♦ Transmitter Idle ♦ Receiver Full ♦ Receiver Overrun ♦ Address Mode Detect ♦ RX pin wake-up interrupt (RX enable, RX falling edge) UART External Pin Interfacing To communicate with an external serial interface, the internal UAR T has two external pins known as TX and RX. The TX and RX pins are the UAR T transmitter and receiver pins respectively . Along with the UAR TEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX or RX pins. When the TX or RX pin function is disabled by cle aring the UAR TEN and TXEN or RXEN bit, the TX or RX pin can be used as a general purpose I/O or other pin-shared functional pin.

Rev. 1.60 118 Deee 1 016 Rev. 1.60 119 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver UART Data Transfer Scheme The block diagram s hows the overall data trans fer s tructure arrangement for the U ART interface. The a ctual da ta t o be t ransmitted from t he MCU i s fi rst t ransferred t o t he T XR re gister by t he application program. The data will then be transferred to the T ransmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator . Only the TXR register is mapped onto the MCU Data Memory , the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UAR T is accepted on the external RX pin, from where it is shifted in, LSB fi rst, t o t he Re ceiver Shi ft R egister a t a ra te c ontrolled by t he B aud Ra te Ge nerator. W hen the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buf fered and can be manipulated by the application program. Only the RXR register i s m apped ont o t he MCU Da ta Me mory, t he Re ceiver Shift Re gister i s not m apped a nd i s therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory . This shared register known as the TXR_RXR register is used for both data transmission and data reception. Tansitte Shift Registe Reeive Shift Registe TX Pin RX Pin Baud Rate Geneato TXR Registe RXR Registe Buffe MCU Data Bus CLK CLK UART Data Transfer Scheme UART Status and Control Registers There are five control registers associated with the UAR T function. The USR, UCR1 and UCR2 registers c ontrol t he o verall f unction o f t he UAR T, wh ile t he B RG r egister c ontrols t he B aud r ate. The actua l data to be transmitted and received on the serial interface is managed through the TXR_ RXR data register. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR_RXR TXRX7 TXRX6 TXRX TXRX4 TXRX3 TXRX TXRX1 TXRX0 BRG BRG7 BRG6 BRG BRG4 BRG3 BRG BRG1 BRG0 UART Register List

Rev. 1.60 10 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver USR register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UAR T. All flags within the USR register are read only . Further explanation on each of the flags is given below. Bit 7 6 5 4 3 2 1 0 Nae PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF fla g is the noise fla g. Whe n thi s read only fla g is "0", it indi cates no noise condition. When the flag is "1", it indicates that the UAR T has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The N F flag can be cleared by a softw are sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5 FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error . When the flag is " 1", it indicates that a framing error has been detected for the current character . The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4 OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the rece iver buf fer has overflowed. When this read only flag is "0", it indicates that there is no overrun error . When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register . The flag is cleared by a software sequence, which is a read to the s tatus regis ter U SR follow ed by an acces s to the RX R data register. Bit 3 RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the init ial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition.

Rev. 1.60 10 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 2 RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty . When the flag is "1", it indicates that t he R XR r ead d ata r egister c ontains n ew d ata. W hen t he c ontents o f t he sh ift register are trans ferred to the RX R register , an interrupt is generated if RIE=1 in the UCR2 register . If one or more errors are detected in the received word, the appropriate receive-related flags NF , FERR, and/or PERR are set within the same clock cycle. The RXIF flag is clear ed when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1 TIDLE: T ransmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register . The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: T ransmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicat es that the character is not transferred to the transmitter shift register . When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register . The TXIF flag is cleared by reading the UAR T status register (USR) with TXIF set and then writing to the TXR data register . Note that when t he T XEN b it i s se t, t he T XIF fla g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full.

Rev. 1.60 1 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UAR T function, such as overall on/of f control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Nae UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 "x" unknown Bit 7 UARTEN: UART function enable control 0: Disable UART. TX and RX pins are as I/O or other pin-shared functional pins 1: Enable UART. TX and RX pins function as UART pins The UAR TEN bit is the UAR T enable bit. When this bit is equal to "0", the UAR T will be di sabled a nd t he RX pi n a s we ll a s t he T X pi n wi ll be a s Ge neral Purpose I/ O or other pin-shared functional pins. When the bit is equal to "1", the UAR T will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UAR T is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. In addition, the value of the baud rate counter will be reset. If the UAR T is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF , OERR, FERR, PERR and NF bits will be cle ared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaf fected. If the UAR T is active and the UAR TEN bit is cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. When the UAR T is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Note: 1. If BNO=1 (9-bit data transfer), parity function is enabled, the 9th bit of data is the parity bit which will not be transferred to RX8. 2. If BNO=0 (8-bit data transfer), parity function is enabled, the 8th bit of data is the parity bit which will not be transferred to RX7. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to "1", the parity function will be enabled. If the bit is equal to "0", then the parity function will be disabled. Bit 4 PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to "1", odd parity type will be selected. If the bit is equal to "0", then even parity type will be selected. Bit 3 STOPS: Number of stop bits selection 0: One stop bit format is used 1: T wo stop bits format is used This bit determines if one or two stop bits are to be used for the TX pin. When this bit is equal to "1", two stop bits are used. If this bit is equal to "0", then only one stop bit is used.

Rev. 1.60 1 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 2 TXBRK: T ransmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the T ransmit Break Character bit. When this bit is "0", there are no break characte rs and the TX pin operates normally . When the bit is "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0 TX8: T ransmit data bit 8 for 9-bit data transfer format (write only) This bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will st ore t he 9 th b it o f t he t ransmitted d ata k nown a s T X8. T he B NO b it i s u sed t o determine whether data transfers are in 8-bit or 9-bit format. UCR2 register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functio ns is to control the basic enable/disable operation of the UAR T T ransmitter and Receiver as well as enabling the various UAR T interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Nae TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN: UART T ransmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the T ransmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buf fers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to "1" and the UAR TEN bit is also equal to "1", the transmitter will be enabled and the TX pin will be controlled by the UAR T. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . If this situation occurs, the TX pin will be used as an I/O or other pin-shared functional pin. Bit 6 RXEN: UART Receiver enabled control 0: UART receiver is disabled 1: UART receiver is enabled The bi t na med RXE N i s t he Re ceiver E nable Bi t. W hen t his bi t i s e qual t o "0", t he receiver will be disabled with any pending data receptions being aborted. In addition the receive buf fers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to "1" and the UAR TEN bit is also equal to "1", the receiver will be enabled and the RX pin will be controlled by the UAR T. Cleari ng the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiv er. If this situation occurs, the RX pin will be used as an I/O or other pin-shared functional pin.

Rev. 1.60 14 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator . This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UAR T. If this bit is equal to "1", the high speed mode is selected. If the bit is equal to "0", the low speed mode is selected. Bit 4 ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bi t na med ADDE N i s t he a ddress de tect fu nction e nable c ontrol bi t. W hen t his bit i s e qual t o "1", t he a ddress de tect func tion i s e nabled. W hen i t oc curs, i f t he 8t h bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, ha s a va lue of "1 ", t hen t he re ceived word wi ll be i dentified a s a n a ddress, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit d epending o n t he v alue o f B NO. I f t he a ddress b it k nown a s t he 8 th o r 9 th b it o f t he received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3 WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or dis ables the receiver w ake-up function. If this bit is equal to " 1" and the device is in the IDLE0 or SLEEP mode, a falling edge on the RX input pin will wake-up the device. If this bit is equal to "0" and the device is in the IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the rece iver interrupt. If this bit is equal to "1" and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UAR T interrupt request flag will be set. If this bit is equal to "0", the UAR T interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1 TIIE: T ransmitter Idle interrupt enable control 0: T ransmitter idle interrupt is disabled 1: T ransmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to "1" and when t he t ransmitter i dle fla g T IDLE i s se t, due t o a t ransmitter i dle c ondition, t he UART interrupt request flag will be set. If this bit is equal to "0", the UAR T interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0 TEIE: T ransmitter Empty interrupt enable control 0: T ransmitter empty interrupt is disabled 1: T ransmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to "1" and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UAR T i nterrupt re quest fl ag wi ll be se t. If t his bi t i s e qual t o "0", t he UAR T interrupt request flag will not be influenced by the condition of the TXIF flag.

Rev. 1.60 14 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver TXR_RXR register The TXR_RXRn register is the data register which is used to store the data to be transmitted on the TXn pin or being received from the RXn pin. Bit 7 6 5 4 3 2 1 0 Nae TXRX7 TXRX6 TXRX TXRX4 TXRX3 TXRX TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0 TXRX7~TXRX0: UART T ransmit/Receive Data bit 7 ~ bit 0 Baud Rate Generator To setup the speed of the serial data communication, the UAR T function contains its own dedicated baud rate generator. T he baud ra te is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor . Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS / [64 (N+1)] fSYS / [16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register , the required baud rate can be setup. Note that because the actual baud rate is determ ined using a discrete value, N, placed in the BRG register , there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Bit 7 6 5 4 3 2 1 0 Nae BRG7 BRG6 BRG BRG4 BRG3 BRG BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0 BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup.

Rev. 1.60 16 Deee 1 016 Rev. 1.60 17 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to "0" determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = fSYS / [64 (N+1)] Re-arranging this equation gives N = [fSYS / (BR×64)] - 1 Giving a value for N = [4000000 / (4800×64)] - 1 = 12.0208 To obtain the closest value, a decim al value of 12 should be placed into the BRG register . This gives an actual or calculated baud rate value of BR = 4000000 / [64× (12 + 1)] = 4808 Therefore the error is equal to (4808 - 4800) / 4800 = 0.16% The following table shows actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS fSYS=8MHz Baud Rates for BRGH=0 Baud Rates for BRGH=1 BRG Kbaud Error (%) BRG Kbaud Error (%) 11. 0 1 8.1 3 1 8.1 0 — — — 1 0 0 Baud Rates and Error Values UART Setup and Control For data transfer , the UAR T functio n utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UAR T hardware, and can be setup to be even, odd or no parity . For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setti ng, which is the setting at power -on. The number of data bits and stop bits, along with t he pa rity, a re se tup by pr ogramming t he c orresponding B NO, PR T, PR EN, a nd ST OPS bi ts in the UCR1 register . The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received LSB first. Although the UAR T transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission.

Rev. 1.60 16 Deee 1 016 Rev. 1.60 17 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Enabling/Disabling the UART Interface The basic on/of f function of the internal UAR T function is controlled using the UAR TEN bit in the UCR1 register . If the UAR TEN, TXEN and RXEN bits are set, then these two UAR T pins will act as n ormal T X o utput p in a nd R X i nput p in r espectively. I f n o d ata i s b eing t ransmitted o n t he T X pin, then it will default to a logic high value. Clearing the UAR TEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins. When the UAR T functi on is disabled the buf fer will be reset to an empty condition, at the same time discarding any remai ning residual data. Disabling the UAR T will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF , OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaf fected. If the UAR TEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediate ly suspended and the UAR T will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register . The BNO bit controls the number of data bits which can be set to either 8 or 9, the PR T bit controls the choice of odd or even parity , the PREN bit controls the parity on/of f function and the ST OPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character . The number of stop bits, which can be either one or two, is independent of the data length and are only to be used for T ransmitter. There is only one stop bit for Receiver. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the trans mit and receive waveforms for both 8-bit and 9-bit data formats. /G53/G74 /G61/G72 /G74/G20 /G42/G69 /G74 /G42/G69 /G74/G20/G30 /G42/G69 /G74/G20 /G31 /G42/G69 /G74/G20/G32 /G42/G69 /G74/G20/G33 /G42/G69 /G74/G20 /G34 /G42/G69 /G74/G20/G35 /G42/G69 /G74/G20/G36 /G42/G69 /G74/G20 /G37 /G53/G74 /G6F/G70/G20 /G42/G69 /G74 /G4E/G65 /G78/G74 /G53/G74 /G61/G72 /G74 /G42/G69 /G74 /G50/G61 /G72/G69 /G74/G79 /G20/G42 /G69/G74 8-Bit Data Format /G53/G74 /G61/G72 /G74/G20 /G42/G69 /G74 /G42/G69 /G74/G20/G30 /G42/G69 /G74/G20/G31 /G42/G69 /G74/G20 /G32 /G42/G69 /G74/G20/G33 /G42/G69 /G74/G20/G34 /G42/G69 /G74/G20 /G35 /G42/G69 /G74/G20/G36 /G42/G69 /G74/G20/G37 /G53/G74 /G6F/G70/G20 /G42/G69 /G74 /G4E/G65 /G78/G74 /G53/G74 /G61/G72 /G74 /G42/G69 /G74 /G42/G69 /G74/G20 /G38 /G50/G61 /G72/G69 /G74/G79 /G20/G42 /G69/G74 9-Bit Data Format

Rev. 1.60 18 Deee 1 016 Rev. 1.60 19 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register . At the transmitter core lies the Transmitter Shift Register , more commonly known as the TSR, whose data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he T XR r egister. T he d ata t o b e t ransmitted i s l oaded into this TXR register by the applic ation program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register , if it is available. It should be noted that the TSR register , unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator ha s defined a shi ft c lock sourc e. However , t he t ransmission c an a lso be i nitiated by first loading data into the TXR register , after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty , in which case a transfer to the TXR register will result in an immed iate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will imm ediately cease and the transmitter will be reset. The TX output pin will then return to the I/ O or other pin-shared function. Transmitting Data When the UAR T is transmitting data, the data is shifted on the TX pin from the shift register , with the leas t s ignificant bit firs t. In the trans mit mode, the TX R regis ter forms a buf fer betw een the internal bus and the transmitter shift register . It should be noted that if 9-bit data format has been selected, then the MSB will be take n from the TX8 bit in the UCR1 register . The steps to initiate a data transfer can be summarized as follows:

Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits.
Setup the BRG register to select the desired baud rate.
Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin.
Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF is "0", data will be inhibited from being written to the TXR register . Clearing the TXIF flag is always achieved using the following software sequence:
A USR register access
A TXR register write execution The read-only TXIF flag is set by the UAR T hardware and if set indic ates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register , which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register , resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. T o clear the TIDLE bit the following software sequence is used:
A USR register access
A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence.

Rev. 1.60 18 Deee 1 016 Rev. 1.60 19 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Transmit Break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. T ransmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR register. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register . At the receive r core lies the Receive Serial Shift Register , commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate , while the main receive serial shifter operates at the baud rate . After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register , if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register , unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UAR T receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep FIFO data buf fer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:

Make the correct selection of BNO, PRT and PREN bits to define the word length and parity type.
Setup the BRG register to select the desired baud rate.
Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur:
The RXIF bit in the USR register will be set when RXR register has data available, at least one character can be read.
When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated.
If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
A USR register access
An RXR register read execution

Rev. 1.60 130 Deee 1 016 Rev. 1.60 131 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Receive Break Any break character received by the UAR T will be managed as a framing error . The receiver will count and expect a certain number of bit times as specified by the value s programmed into the BNO and one STOPS bit. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and one STOP bit. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register , interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buf fer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UAR T registers will result in the following:

The framing error flag, FERR, will be set.
The receive data register, RXR, will be cleared.
The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status flag in the USR register , otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE bit is "1", when a word is transferred from the Receive Shift Re gister, RSR, t o t he Re ceive Da ta Re gister, RXR. An ove rrun e rror c an a lso ge nerate a n interrupt if RIE is "1". Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR flag The RXR register is composed of a two byte deep FIFO data buf fer, where two bytes can be held in the FIFO register , while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register . If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen:
The OERR flag in the USR register will be set.
The RXR contents will not be lost.
The shift register will be overwritten.
An interrupt will be generated if the RIE bit is set. The O ERR flag can be cleared by an acces s to the U SR regis ter follow ed by a read to the RX R register.

Rev. 1.60 130 Deee 1 016 Rev. 1.60 131 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Noise Error – NF Flag Over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. I f n oise i s detected within a frame the following will occur:

The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
Data will be transferred from the Shift register to the RXR register.
No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note t hat t he NF fla g i s r eset b y a USR r egister r ead o peration f ollowed b y a n R XR r egister r ead operation. Framing Error – FERR Flag The read only framing error flag, FERR, in the USR register , is set if a zero is detected instead of stop bits. If two stop bits are select ed, only the first stop bit is detecte d, it must be high. If the first stop bit is low , the FERR flag will be set. The FERR flag is buf fered along with the received data and is cleared on any reset. Parity Error – PERR Flag The read only parity error flag, PERR, in the USR register , is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN bit is "1", and if the parity type, odd or e ven i s se lected. T he re ad onl y PE RR fl ag i s buf fered a long wi th t he re ceived da ta bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buf fered along with the corresponding word and should be read before reading the data word. UART Module Interrupt Structure Several i ndividual UAR T c onditions c an ge nerate a UAR T i nterrupt. W hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . These conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt cont rol is enabled and the sta ck is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be s erviced before returning to the main program. Four of thes e conditions h ave t he c orresponding USR r egister fla gs wh ich wi ll g enerate a UAR T i nterrupt i f i ts associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address det ect condit ion, whic h is al so a UAR T i nterrupt source, does not have an associa ted flag, but will generate a UAR T interrupt when an address detect condition occurs if its function is e nabled by se tting t he ADDE N bi t i n t he UCR2 re gister. An RX pi n wa ke-up, whi ch i s a lso a UART interrupt source, does not have an associated flag, but will generate a UAR T interrupt if the microcontroller i s woke n up from IDL E0 or SL EEP m ode by a fa lling e dge on t he RX pi n, i f t he WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay , commonly known as the System Start-up T ime, for the oscillator to restart and stabilize before the system resumes normal operation.

Rev. 1.60 13 Deee 1 016 Rev. 1.60 133 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Note t hat t he USR r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. The flags will be cleared automatically whe n c ertain a ctions a re t aken by t he UAR T, t he de tails of whi ch a re gi ven i n t he UART regi ster se ction. The overal l UAR T i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. Tansitte Epty Flag TXIF USR Registe Tansitte Idle Flag TIDLE Reeive Oveun Flag OERR Reeive Data Availale RXIF ADDEN RX Pin Wake-up WAKE 0 RX7 if BNO=0 RX8 if BNO=1UCR Registe OR RIE 0 TIIE 0 TEIE 0 UART Inteupt Request Flag UARTF UCR Registe UARTE INTC Registe EMI INTC0 Registe UART Interrupt Scheme Address Detect Mode Setting t he Ad dress De tect Mo de b it, ADDE N, i n t he UC R2 r egister, e nables t his sp ecial m ode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data A vailable interrupt, which is requested by the RXIF flag. If the ADDEN bit is "1", then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO bit is "1" or the 8th bit if BNO bit is "0". If this bit is high, then the received word will be defined as an address rather than data. A Data A vailable interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is "0", then a Receiver Data A vailable interrupt will be generated each time the RXIF flag i s se t, i rrespective o f t he d ata l ast b it st atus. T he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit PREN to zero. ADDEN Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function

Rev. 1.60 13 Deee 1 016 Rev. 1.60 133 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver UART Power Down and Wake-up When the the device system clock is switched of f, the UAR T will cease to function. If the device executes the "HALT" instruction and switches of f the system clock while a transmission is still in progres s, then the trans mission w ill be paus ed until the U ART clock s ource derived from the microcontroller is activated. In a similar way , if the device executes the "HALT" instruction and switches of f the system clock while receiving data, then the reception of data will likewise be paused. When the device enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and recei ve registers, as well as the BRG register will not be af fected. It is recommended to make sure first that the UA RT data transmis sion or reception has been finished before the microcontroller enters the IDLE or SLEEP mode. The UA RT function contains a receiver RX pin wake-up function, which is enabled or disabled by the W AKE bit in the UCR2 register . If this bit, along with the UAR T enable bit, UAR TEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the device enters the IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the device from the IDLE0 or SL EEP Mo de. No te t hat a s i t t akes c ertain sy stem c lock c ycles a fter a wa ke-up, b efore n ormal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UAR T wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UAR T interrupt enable bit, UARTE, must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed.

Rev. 1.60 134 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Interrupts Interrupts are an important part of any microcontroller s ystem. When an external event or an internal function such as a T ouch Action or T imer/Event Counter overflow requires microcontroller attention, their corres ponding interrupt w ill enforce a temporary s uspension of the main program allowing the microcontroller to direct attention to their respective needs. The devices contain several external interrupt and internal interrupt functions. T he external interrupt is generated by the action of the external INT pin and T ouch Keys, while the internal interrupts are generated by various internal functions such as T imer Modules, T ime Bases, I2C, LVD, EEPROM and UART. Interrupt Registers Overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the Special Purpose Data Memory , as shown in the accompanying table. The registers fall into two categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the INTEG register to setup the external interrupt trigger edge type. Each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Notes Gloal EMI — — INT Pin INTE INTF — Touh Key Module TKME TKMF — IC IICE IICF — UART UARTE UARTF — EEPROM DEE DEF — LVD LVDE LVDF — Tie Base TBnE TBnF n=0 o 1 TM CTMPnE CTMPnF n=0 PTMPnE PTMPnF n=0 CTMAnE CTMAnF n=0 PTMAnE PTMAnF n=0 Interrupt Register Bit Naming Conventions Interrupt Register Contents Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTC0 — TB0F TKMF INTF TB0E TKME INTE EMI INTC1 PTMA0F PTMP0F CTMA0F CTMP0F PTMA0E PTMP0E CTMA0E CTMP0E INTC UARTF DEF IICF TB1F UARTE DEE IICE TB1E

Rev. 1.60 134 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver INTEG Register Bit 7 6 5 4 3 2 1 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 INTS1, INTS0: Defines INT interrupt active edge 00: Disabled interrupt 01: Rising Edge interrupt 10: Falling Edge interrupt 11: Dual Edge interrupt INTC0 Register Bit 7 6 5 4 3 2 1 0 Nae — TB0F TKMF INTF TB0E TKME INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 TKMF: T ouch key module interrupt request flag 0: No request 1: Interrupt request Bit 4 INTF: INT pin interrupt request flag 0: No request 1: Interrupt request Bit 3 TB0E: T ime Base 0 interrupt control 0: Disable 1: Enable Bit 2 TKME: T ouch key module interrupt control 0: Disable 1: Enable Bit 1 INTE: INT pin interrupt control 0: Disable 1: Enable Bit 0 EMI: Global Interrupt control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Nae PTMA0F PTMP0F CTMA0F CTMP0F PTMA0E PTMP0E CTMA0E CTMP0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 PTMA0F: PTM0 CCRA comparator interrupt request flag 0: No request 1: Interrupt request Bit 6 PTMP0F: PTM0 CCRP comparator interrupt request flag 0: No request 1: Interrupt request

Rev. 1.60 136 Deee 1 016 Rev. 1.60 137 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 5 CTMA0F: CTM0 CCRA comparator interrupt request flag 0: No request 1: Interrupt request Bit 4 CTMP0F: CTM0 CCRP comparator interrupt request flag 0: No request 1: Interrupt request Bit 3 PTMA0E: PTM0 CCRA comparator interrupt control 0: Disable 1: Enable Bit 2 PTMP0E: PTM0 CCRP comparator interrupt control 0: Disable 1: Enable Bit 1 CTMA0E: CTM0 CCRA comparator interrupt control 0: Disable 1: Enable Bit 0 CTMP0E: CTM0 CCRP comparator interrupt control 0: Disable 1: Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Nae UARTF DEF IICF TB1F UARTE DEE IICE TB1E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 UARTF: UART interrupt request flag 0: No request 1: Interrupt request Bit 6 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 5 IICF: I2C interrupt request flag 0: No request 1: Interrupt request Bit 4 TB1F: T ime Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 UARTE: UART interrupt request control 0: Disable 1: Enable Bit 2 DEE: Data EEPROM control 0: Disable 1: Enable Bit 1 IICE: I2C interrupt control 0: Disable 1: Enable Bit 0 TB1E: Time Base 1 interrupt control 0: Disable 1: Enable

Rev. 1.60 136 Deee 1 016 Rev. 1.60 137 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver INTC3 Register Bit 7 6 5 4 3 2 1 0 Bit 7~5 Unimplemented, read as "0" Bit 4 LVDF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3~1 Unimplemented, read as "0" Bit 0 LVDE: LVD interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur , such as a T ouch Key Counter overflow , a TM Comparator P or Comparator A match, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . The microcontroller will then fetch its next instruction from this interrupt vector . The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams w ith their order of priority . Every interrupt s ource has its own individual vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt e nable b it, E MI b it wi ll b e c leared a utomatically. T his wi ll p revent a ny f urther i nterrupt nesting from occurring. However , if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. All o f t he i nterrupt r equest fla gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n SL EEP o r IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.

Rev. 1.60 138 Deee 1 016 Rev. 1.60 139 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver INT Pin Touh Key Module INTF TKMF INTE TKME EMI 04H EMI 4H Inteupt Nae Request Flags Enale Bits Maste Enale Veto EMI auto disaled in ISR Pioity High Low CTM0 A CTMA0F CTMA0E xxE Enale Bits xxF Request Flag auto eset in ISR Legend EMI 08H IC IICF IICE EMI 10H EMI 14H Tie Base 1 TB1F TB1E Tie Base 0 TB0F TB0E EMI 0CH EEPROM DEF DEE EMI 18H 1CH CTM0 P CTMP0F CTMP0E EMI 0H PTM0 P PTMP0F PTMP0E EMI PTM0 A PTMA0F PTMA0E EMI EMI CHUART UARTF UARTE EMI 30HLVD LVDF LVDE Interrupt Structure External Interrupt The e xternal i nterrupt is c ontrolled by si gnal t ransitions on t he pi n INT . An e xternal i nterrupt request will take place when the external interrupt request flag, INTF , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correc t i nterrupt edge t ype must be se lected usi ng t he INT EG regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register . When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function.

Rev. 1.60 138 Deee 1 016 Rev. 1.60 139 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Time Base Interrupts The function of the T ime Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its timer function. When this happens its interrupt request flags TBnF wil l be set . T o all ow the program to branch t o its inte rrupt vect or address, the global interrupt enable bit, EMI and T ime Base enable bit, TBnE, must first be set. When the interrup t is enabled, the stack is not full and the T ime Base overflows, a subroutine call to its vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the T ime Base Interrupt is to provide an interrupt signal at fixed time periods. Each Time Base clock source originates from an independent internal prescaler. Each 15-bit prescaler can source from fSYS, fSYS/4, fSUB or fH, selected by CLKSELn1~CLKSELn0 bits in the PSCR register. PSCR Register Bit 7 6 5 4 3 2 1 0 Nae — — CLKSEL11 CLKSEL10 — — CLKSEL01 CLKSEL00 R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~4 CLKSEL11 ~ CLKSEL10: T ime Base 1 prescaler clock source selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH Bit 3~2 Unimplemented, read as "0" Bit 1~0 CLKSEL01 ~ CLKSEL00: T ime Base 0 prescaler clock source selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH TBC Register Bit 7 6 5 4 3 2 1 0 Nae TB1ON TB1 TB11 TB10 TB0ON TB0 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TB1ON: T ime Base 1 enable/disable control 0: Disable 1: Enable Bit 6~4 TB12 ~ TB10: Select T ime Base 1 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC

Rev. 1.60 140 Deee 1 016 Rev. 1.60 141 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Bit 3 TB0ON: T ime Base 0 enable/disable control 0: Disable 1: Enable Bit 2~0 TB02 ~ TB00: Select T ime Base 1 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC fSYS/4 CLKSELn[1:0 ] fSUB fSYS Prescaler TBnON fPSC TBn[2:0 ] Time Base n Interrupt fH Time Base Structure (n=0 or 1) TM Interrupts The Compact and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P , which generates a TM interrupt when a compare match condition occurs. For each of t he Compac t and Pe riodic T ype TMs, t here are t wo i nterrupt request fla gs, CTMP0F/CT MA0F and PTMP0F/PTMA0F , and two enable bits, CTMP0E/CTMA0E and PTMP0E/PTMA0E. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A macth situation happens. To allow the program to branch to its respective interrup t vector address, the global interrupt enable bit, EMI, the respective TM interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM interrupt vector location, will take place. When the TM interrupt is serviced, the TM interrupt request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM W rite cycle ends. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM W rite cycle ends, a subroutine call to the respective EEPROM Interrupt vect or, will take place. When the EEPROM Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts.

Rev. 1.60 140 Deee 1 016 Rev. 1.60 141 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver LVD Interrupt An L VD Interrupt request will take place when the L VD Interrupt request flag, L VDF, is set, which occurs when the Low V oltage Detector function detects a low power supply voltage. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low V oltage Interrupt enable bit, L VDE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector , will take place. When the Low V oltage Interrupt is serviced, the L VDF flag will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. Touch Key Interrupt For a T ouch Key interrupt to occur, the global interrupt enable bit, EMI, and the T ouch Key interrupt enable TKME must be first set. An actual T ouch Key interrupt will take place when the T ouch Key request flag. TKMF , is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the T ouch Key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector , will take place. When the interrupt is serviced, the T ouch Ke y i nterrupt re quest flag, T KMF, wi ll be a utomatically re set a nd t he E MI bi t wi ll be automatically cleared to disable other interrupts. I2C Interrupt An I2C Interrupt request will take place when the I2C Interrupt request flag, IICF, is set, which occurs when an address match occurs, or an I2C communication time-out occurs, or a byte of data has been rece ived or transmitted by the I2C interface. T o allow the program to branch to its respective interrupt ve ctor a ddress, t he gl obal i nterrupt e nable bi t, E MI, a nd t he I2C Interface Int errupt enable bit, IICE, must first be set. When the interrupt is enabled, the stack is not full and any these conditions are created, a subroutine call to the respective interrupt vect or, will take place. When the I2C Interface Interrupt is serviced, the I2C interrupt request flag, IICF, will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. UART Interrupt Several i ndividual UAR T c onditions c an ge nerate a UAR T i nterrupt. W hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . These conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an RX pin wake-up. T o allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, and UAR T interrupt enable bit, UARTE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the UAR T Interrupt vector will take place. When the interrupt is serviced, the UART Interrupt flag, UARTF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. However , the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section.

Rev. 1.60 14 Deee 1 016 Rev. 1.60 143 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Interrupt Wake-up Function Each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on t he e xternal i nterrupt pi n or a l ow powe r sup ply vol tage m ay c ause t heir re spective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately . If only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n SL EEP o r I DLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.

Rev. 1.60 14 Deee 1 016 Rev. 1.60 143 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SCOM and SSEG Function for LCD The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, SSEG0~SSEG19, are pin shared w ith certain pins on the I/O ports. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using the devices by configuring the I/O pins as common pins and configuring the I/O pins as segment pins. The LCD driver function is controlled using the LCD control registers which in addition to controlling the overall on/of f function also controls the SCOM and SSEG operating current. This enables the LCD COM and SEG driver to generate the necessary VSS, (1/3)VDD, (2/3)VDD voltage and VDD levels for LCD 1/3 bias operation. The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver , however this bi t i s use d i n c onjunction wi th t he COMnE N a nd SE GnEN bi ts t o se lect whi ch I/ O Port pi ns are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. LCD Driver Structure

Rev. 1.60 144 Deee 1 016 Rev. 1.60 14 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver The acco mpanying waveform diagram shows a typical 1/3 Bias LCD waveform generated using the application program. Note that the depiction of a "1" in the diagram illustrates an illuminated LCD pixel. The COM signal polarity generated on pins SCOM0~SCOM3, whether 0 or 1, are generated using the corresponding I/O data register bits, which are bits PA0~PA2, PA4 in the PA register. Note: The logical values shown in the diagram are the PA I/O register bit values, PA0~PA2, PA4. 1/3 Bias LCD Waveform

Rev. 1.60 144 Deee 1 016 Rev. 1.60 14 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver A cyclic LCD waveform includes two frames, known as Frame 0 and Frame 1 for which the following offers a functional explanation. In Frame 0 To select Frame 0 clear the FRAME bit to 0. In frame 0, the COM signal output can have a value of VDD, or have a Vbias value of (1/3)VDD. The SEG signal can have a value of VSS, or have a Vbias value of (2/3)VDD. In Frame 1 In frame 1, the COM signal output can have a value of VSS, or have a Vbias value of (2/3)VDD. The SEG signal can have a value of VDD have a Vbias value of (1/3)VDD. The COM0~COMn waveform is controlled by the application program using the FRAME bit, and the corresponding I/O data register for the respective COM pin to determine whether the COM0~COMn output has a value of either VDD, VSS or Vbias. The SEG0~SEGm waveform is controlled in a similar way using the FRAME bit and the corres ponding I/O data regis ter for the respective SEG pin to determine whether the SEG0~SEGn output has a value of either VDD, VSS or Vbias. LCD Bias Control The LCD COM and SEG driver enable a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SLCDC0 register. SLCDC0 Register Bit 7 6 5 4 3 2 1 0 Nae FRAME ISEL1 ISEL0 LCDEN COM3EN COMEN COM1EN COM0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 FRAME: Fram 0 or Frame 1 output selection 0: Frame 0 1: Frame 1 Bit 6~5 ISEL1~ISEL0: SCOM and SSEG operating current selection (VDD=5V) 00: 8.3μA 01: 16.7μA 10: 50μA 11: 100μA Bit 4 LCDEN: SCOM and SSEG module on/off control 0: Disable 1: Enable The SCOMn and SSEGm lines can be enabled using COMnEN and SEGmEN if LCDEN=1. When LCDEN=0, then the SCOMn and SSEGm outputs will be fixed at a VSS level. Bit 3 COM3EN: SCOM3 or other function selection 0: Other function 1: SCOM3 Bit 2 COM2EN: SCOM2 or other function selection 0: Other function 1: SCOM2 Bit 1 COM1EN: SCOM1 or other function selection 0: Other function 1: SCOM1 Bit 0 COM0EN: SCOM0 or other function selection 0: Other function 1: SCOM0

Rev. 1.60 146 Deee 1 016 Rev. 1.60 147 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SLCDC1 Register Bit 7 6 5 4 3 2 1 0 Nae SEG7EN SEG6EN SEGEN SEG4EN SEG3EN SEGEN SEG1EN SEG0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 SEG7EN~SEG0EN: SSEG7 ~ SSEG0 or other function selection 0: Other function 1: SSEG7~SSEG0 SLCDC2 Register Bit 7 6 5 4 3 2 1 0 Nae SEG1EN SEG14EN SEG13EN SEG1EN SEG11EN SEG10EN SEG9EN SEG8EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 SEG15EN~SEG8EN: SSEG15 ~ SSEG8 or other function selection 0: Other function 1: SSEG15~SSEG8 SLCDC3 Register – BS82C16A-3/BS82D20A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — SEG19EN SEG18EN SEG17EN SEG16EN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 SEG19EN~SEG16EN: SSEG19 ~ SSEG16 or other function selection 0: Other function 1: SSEG19~SSEG16

Rev. 1.60 146 Deee 1 016 Rev. 1.60 147 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Low Voltage Detector – LVD Each device has a Low V oltage Detector function, also known as L VD. This enables the device to monitor the power supply voltage, VDD, and provides a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low V oltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name L VDC. Three bits in this register , VL VD2~VLVD0, are used to select one of five fixed voltages below which a low volta ge condition will be detemined. A low voltage condition is indicated when the L VDO bit is set. If the L VDO bit is low , this indicates that the VDD voltage is above the preset low voltage value. The L VDEN bit is used to control the overall on/of f function of the low voltage detector . Setting the bit high will enabl e the low voltage detector . Clearing the bit to zero will switch of f the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Nae — — LVDO LVDEN — VLVD VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 LVDO: LVD Output Flag 0: No Low V oltage Detect 1: Low V oltage Detect Bit 4 LVDEN: Low V oltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bit 2~0 VL VD2 ~ VLVD0 : Select LVD V oltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Note: The VLVR of these three devices is fixed at 2.55V , so the VLVD should be set to 2.7V~4.0V.

Rev. 1.60 148 Deee 1 016 Rev. 1.60 149 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver LVD Operation The Low V oltage Detector function operates by comparing the pow er supply voltage, VDD, with a pre-specified volta ge level stored in the L VDC register . This has a range of between 2.7V and 4.0V . When the power supply voltage, VDD, falls below this pre-determined value, the L VDO bit will be set high indicating a low power supply voltage condition. The Low V oltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is in SLEEP mode the low voltage detector will be automatically disabled even if the L VDEN bit is high. After enabling the Low V oltage Detector , a time delay tLVDS should be allowed for the circuitry to stabilise before reading the L VDO bit. Note also that as the VDD voltage may rise and fall rather slowly , at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. /G56/G44 /G44 /G56 /G4C/G56 /G44 /G4C/G56 /G44/G45 /G4E /G4C/G56 /G44/G4F /G74 /G4C/G56 /G44/G53 LVD Operation The Low V oltage Detector also has its own interrupt, providing an alte rnative means of low voltage detection, in addition to polling the L VDO bit. The interrupt will only be generated after a delay of tLVD after the L VDO bit has been set high by a low voltage condition. In this case, the L VDF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low V oltage Detector wake up function is not required then the L VDF flag should be first set high before the device enters the SLEEP or IDLE Mode.

Rev. 1.60 148 Deee 1 016 Rev. 1.60 149 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Configuration Options Configuration options refer to certa in options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT -IDE software development tools. As these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Option Low Speed Syste Osillato Seletion – fSUB: LIRC LXT HIRC fequeny seletion: 8MHz 1MHz 16MHz Note: 1. The low speed system oscillator selection is only for the BS82C16A-3 and BS82D20A-3. 2. When the HIRC has been configurated at a frequency shown in this table, the HIRCS1 and HIRCS0 bits is recommended to be setup to select the same frequency to keep the HIRC frequency accuracy spedified in the A.C. characteristics. Application Circuit VDD VSS KEY1 0.1uF I/O Pins IC Pins VDD KEY KEYn UART Pins SCOM&SSEG Pins XT1 XT OSC Ciuit See Osillato Setion

Rev. 1.60 10 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. In the case of Holtek microcontroller , a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator , most instructions would be i mplemented wi thin 0.5 μs a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP , CALL, RET , RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. E xamples of suc h i nstructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Ac cumulator. One of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. W ithin t he Hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified.

Rev. 1.60 10 Deee 1 016 Rev. 1.60 11 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within t he Hol tek m icrocontroller i nstruction se t. As wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he Ac cumulator wh ich m ay i nvolve a dditional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Dif ferent rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he Ca rry bit from where it can be examined and the necessary serial bit set high or low . Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or t o a su broutine usi ng t he CAL L i nstruction. T hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. This is done by placing a return ins truction " RET" in the s ubroutine w hich w ill cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping of f point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. De pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. These i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The abili ty to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers . This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively . The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is take n care of automatically when these bit operation instructions are used. Table Read Operations Data st orage i s norm ally i mplemented by usi ng re gisters. However , whe n worki ng wi th l arge amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory . T o overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HAL T" i nstruction f or Po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the W atchdog T imer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections.

Rev. 1.60 1 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A[] Add Data Meoy to ACC 1 Z C AC OV ADDM A[] Add ACC to Data Meoy 1Note Z C AC OV ADD Ax Add iediate data to ACC 1 Z C AC OV ADC A[] Add Data Meoy to ACC with Cay 1 Z C AC OV ADCM A[] Add ACC to Data eoy with Cay 1Note Z C AC OV SUB Ax Sutat iediate data fo the ACC 1 Z C AC OV SUB A[] Sutat Data Meoy fo ACC 1 Z C AC OV SUBM A[] Sutat Data Meoy fo ACC with esult in Data Meoy 1Note Z C AC OV SBC A[] Sutat Data Meoy fo ACC with Cay 1 Z C AC OV SBCM A[] Sutat Data Meoy fo ACC with Cay esult in Data Me o y 1Note Z C AC OV DAA [] Deial adjust ACC fo Addition with esult in Data Meoy 1Note C Logic Operation AND A[] Logial AND Data Meoy to ACC 1 Z OR A[] Logial OR Data Meoy to ACC 1 Z XOR A[] Logial XOR Data Meoy to ACC 1 Z ANDM A[] Logial AND ACC to Data Meoy 1Note Z ORM A[] Logial OR ACC to Data Meoy 1Note Z XORM A[] Logial XOR ACC to Data Meoy 1Note Z AND Ax Logial AND iediate Data to ACC 1 Z OR Ax Logial OR iediate Data to ACC 1 Z XOR Ax Logial XOR iediate Data to ACC 1 Z CPL [] Copleent Data Meoy 1Note Z CPLA [] Copleent Data Meoy with esult in ACC 1 Z Increment & Decrement INCA [] Ineent Data Meoy with esult in ACC 1 Z INC [] Ineent Data Meoy 1Note Z DECA [] Deeent Data Meoy with esult in ACC 1 Z DEC [] Deeent Data Meoy 1Note Z Rotate RRA [] Rotate Data Meoy ight with esult in ACC 1 None RR [] Rotate Data Meoy ight 1Note None RRCA [] Rotate Data Meoy ight though Cay with esult in ACC 1 C RRC [] Rotate Data Meoy ight though Cay 1Note C RLA [] Rotate Data Meoy left with esult in ACC 1 None RL [] Rotate Data Meoy left 1Note None RLCA [] Rotate Data Meoy left though Cay with esult in ACC 1 C RLC [] Rotate Data Meoy left though Cay 1Note C

Rev. 1.60 1 Deee 1 016 Rev. 1.60 13 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Mnemonic Description Cycles Flag Affected Data Move MOV A[] Move Data Meoy to ACC 1 None MOV []A Move ACC to Data Meoy 1Note None MOV Ax Move iediate data to ACC 1 None Bit Operation CLR [].i Clea it of Data Meoy 1Note None SET [].i Set it of Data Meoy 1Note None Branch JMP add Jup unonditionally None SZ [] Skip if Data Meoy is zeo 1Note None SZA [] Skip if Data Meoy is zeo with data oveent to ACC 1Note None SZ [].i Skip if it i of Data Meoy is zeo 1Note None SNZ [].i Skip if it i of Data Meoy is not zeo 1Note None SIZ [] Skip if ineent Data Meoy is zeo 1Note None SDZ [] Skip if deeent Data Meoy is zeo 1Note None SIZA [] Skip if ineent Data Meoy is zeo with esult in ACC 1Note None SDZA [] Skip if deeent Data Meoy is zeo with esult in ACC 1Note None CALL add Suoutine all None RET Retun fo suoutine None RET Ax Retun fo suoutine and load iediate data to ACC None RETI Retun fo inteupt None Table Read TABRD [] Read table (specific page) to TBLH and Data Memory Note None TABRDC [] Read tale (uent page) to TBLH and Data Meoy Note None TABRDL [] Read tale (last page) to TBLH and Data Meoy Note None Miscellaneous NOP No opeation 1 None CLR [] Clea Data Meoy 1Note None SET [] Set Data Meoy 1Note None CLR WDT Clea Wathdog Tie 1 TO PDF CLR WDT1 Pe-lea Wathdog Tie 1 TO PDF CLR WDT Pe-lea Wathdog Tie 1 TO PDF SWAP [] Swap niles of Data Meoy 1Note None SWAPA [] Swap niles of Data Meoy with esult in ACC 1 None HALT Ente powe down ode 1 TO PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the T O and PDF flags may be af fected by the execution status. The T O and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the T O and PDF flags remain unchanged.

Rev. 1.60 14 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Instruction Definition ADC A,[m] Add D ata M emory to A CC w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C ADCM A,[m] Add A CC to D ata M emory w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C ADD A,[m] Add D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C ADD A,x Add im mediate data to A CC Description The c ontents o f t he A ccumulator a nd t he s pecified im mediate data a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + x Affected fl ag(s) OV, Z , A C, C ADDM A,[m] Add A CC to D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C AND A,[m] Logical A ND D ata M emory t o A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ [ m] Affected fl ag(s) Z AND A,x Logical A ND im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b it w ise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ x Affected fl ag(s) Z ANDM A,[m] Logical A ND A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ AND″ [ m] Affected fl ag(s) Z

Rev. 1.60 14 Deee 1 016 Rev. 1.60 1 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CALL addr Subroutine c all Description Unconditionally c alls a s ubroutine a t t he s pecified a ddress. Th e P rogram C ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. T he sp ecified a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. A s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. Operation Stack ← P rogram Counter + 1 Program C ounter ← a ddr Affected fl ag(s) None CLR [m] Clear D ata M emory Description Each b it o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m] ← 00H Affected fl ag(s) None CLR [m].i Clear bi t o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m].i ← 0 Affected fl ag(s) None CLR WDT Clear W atchdog T imer Description The T O, P DF fl ags a nd t he W DT a re al l c leared. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CLR WDT1 Pre-clear W atchdog T imer Description The T O, P DF fl ags a nd t he W DT a re a ll c leared. N ote t hat t his instruction w orks in conjunction w ith C LR W DT2 a nd m ust b e e xecuted al ternately w ith C LR W DT2 to h ave effect. R epetitively e xecuting t his i nstruction w ithout al ternately e xecuting C LR W DT2 w ill have no e ffect. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CLR WDT2 Pre-clear W atchdog T imer Description The T O, P DF fl ags and t he W DT are all cleared. N ote t hat t his i nstruction w orks i n conjunction with C LR W DT1 a nd m ust b e e xecuted al ternately w ith C LR W DT1 to h ave e ffect. R epetitively e xecuting t his i nstruction w ithout al ternately e xecuting C LR W DT1 w ill h ave n o e ffect. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CPL [m] Complement D ata M emory Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Operation [m] ← [m] Affected fl ag(s) Z

Rev. 1.60 16 Deee 1 016 Rev. 1.60 17 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver CPLA [m] Complement D ata M emory w ith r esult i n A CC Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Th e c omplemented r esult i s s tored i n the A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] Affected fl ag(s) Z DAA [m] Decimal-Adjust A CC f or addition w ith r esult i n D ata M emory Description Convert t he c ontents o f t he A ccumulator v alue to a B CD ( Binary C oded D ecimal) v alue resulting f rom t he p revious a ddition o f t wo B CD v ariables. I f t he low n ibble is greater t han 9 or i f A C fl ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. O therwise t he l ow n ibble remains u nchanged. I f t he h igh n ibble i s g reater t han 9 o r i f t he C fl ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. E ssentially, t he decimal c onversion i s p erformed b y a dding 00H, 0 6H, 6 0H o r 6 6H depending o n t he A ccumulator a nd fl ag c onditions. O nly t he C fl ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal B CD s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. Operation [m] ← A CC + 00H or [m] ← A CC + 06 H o r [m] ← A CC + 60H o r [m] ← A CC + 66H Affected fl ag(s) C DEC [m] Decrement D ata M emory Description Data i n t he s pecified D ata M emory i s d ecremented b y 1 . Operation [m] ← [ m] − 1 Affected fl ag(s) Z DECA [ m] Decrement D ata M emory wi th r esult i n A CC Description Data in t he sp ecified D ata M emory is d ecremented b y 1 . T he re sult is s tored in t he Accumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] − 1 Affected fl ag(s) Z HALT Enter p ower down m ode Description This i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. Th e c ontents o f the D ata M emory a nd r egisters a re r etained. Th e W DT a nd p rescaler a re c leared. Th e p ower down fl ag P DF i s s et a nd t he W DT t ime-out fl ag T O i s c leared. Operation TO ← 0 PDF ← 1 Affected fl ag(s) TO, P DF INC [m] Increment D ata M emory Description Data in t he sp ecified D ata M emory is incremented b y 1 . Operation [m] ← [ m] + 1 Affected fl ag(s) Z INCA [m] Increment D ata M emory wi th r esult i n A CC Description Data i n t he sp ecified D ata M emory i s i ncremented b y 1 . Th e re sult i s s tored i n t he A ccumulator. The c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] + 1 Affected fl ag(s) Z

Rev. 1.60 16 Deee 1 016 Rev. 1.60 17 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver JMP addr Jump u nconditionally Description The c ontents o f t he P rogram C ounter a re re placed w ith t he sp ecified a ddress. P rogram execution t hen c ontinues f rom t his n ew a ddress. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. Operation Program Counter ← addr Affected fl ag(s) None MOV A,[m] Move D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. Operation ACC ← [ m] Affected fl ag(s) None MOV A,x Move im mediate data to A CC Description The im mediate data s pecified i s l oaded i nto t he A ccumulator. Operation ACC ← x Affected fl ag(s) None MOV [m],A Move A CC to D ata M emory Description The c ontents o f t he A ccumulator a re c opied to t he s pecified D ata M emory. Operation [m] ← A CC Affected fl ag(s) None NOP No o peration Description No o peration i s p erformed. E xecution c ontinues w ith t he n ext i nstruction. Operation No operation Affected fl ag(s) None OR A,[m] Logical O R D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise logical O R op eration. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ [ m] Affected fl ag(s) Z OR A,x Logical OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical O R operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ x Affected fl ag(s) Z ORM A,[m] Logical OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical O R operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ OR″ [ m] Affected fl ag(s) Z RET Return from s ubroutine Description The P rogram C ounter is re stored f rom t he s tack. P rogram e xecution c ontinues a t t he re stored a ddress. Operation Program Counter ← S tack Affected fl ag(s) None

Rev. 1.60 18 Deee 1 016 Rev. 1.60 19 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver RET A,x Return f rom su broutine and l oad im mediate data to A CC Description The P rogram C ounter i s r estored f rom t he s tack a nd t he A ccumulator l oaded w ith t he s pecified immediate data. P rogram e xecution c ontinues a t t he r estored a ddress. Operation Program Counter ← S tack ACC ← x Affected fl ag(s) None RETI Return from i nterrupt Description The P rogram C ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he EMI b it. E MI i s t he m aster i nterrupt g lobal e nable b it. I f a n i nterrupt w as p ending w hen t he RETI instruction is e xecuted, t he p ending In terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. Operation Program Counter ← S tack EMI ← 1 Affected fl ag(s) None RL [m] Rotate D ata M emory l eft Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← [ m].7 Affected fl ag(s) None RLA [m] Rotate D ata M emory left w ith re sult in A CC Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← [ m].7 Affected fl ag(s) None RLC [m] Rotate D ata M emory l eft t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated l eft b y 1 b it. B it 7 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← C C ← [ m].7 Affected fl ag(s) C RLCA [m] Rotate D ata M emory left t hrough C arry w ith re sult in A CC Description Data i n t he s pecified D ata M emory and t he carry fl ag are r otated l eft b y 1 b it. B it 7 r eplaces t he Carry b it a nd t he o riginal c arry fl ag i s r otated i nto t he b it 0 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← C C ← [ m].7 Affected fl ag(s) C RR [m] Rotate D ata M emory r ight Description The contents of t he s pecified D ata M emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← [ m].0 Affected fl ag(s) None

Rev. 1.60 18 Deee 1 016 Rev. 1.60 19 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver RRA [m] Rotate D ata M emory right with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . Th e r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he Data M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← [ m].0 Affected fl ag(s) None RRC [m] Rotate D ata M emory r ight t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← C C ← [ m].0 Affected fl ag(s) C RRCA [m] Rotate D ata M emory right th rough C arry with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 r eplaces the C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← C C ← [ m].0 Affected fl ag(s) C SBC A,[m] Subtract D ata M emory from A CC wi th C arry Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C SBCM A,[m] Subtract D ata M emory from A CC wi th C arry a nd r esult i n D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he D ata M emory. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C SDZ [m] Skip i f decrement D ata M emory i s 0 Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] − 1 Skip if [ m]=0 Affected fl ag(s) None

Rev. 1.60 160 Deee 1 016 Rev. 1.60 161 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SDZA [m] Skip i f decrement D ata M emory i s z ero w ith r esult i n A CC Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] − 1 Skip if A CC=0 Affected fl ag(s) None SET [m] Set D ata M emory Description Each b it o f t he s pecified D ata M emory i s s et t o 1 . Operation [m] ← F FH Affected fl ag(s) None SET [m].i Set b it o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s s et t o 1 . Operation [m].i ← 1 Affected fl ag(s) None SIZ [m] Skip i f i ncrement D ata M emory i s 0 Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] + 1 Skip if [ m]=0 Affected fl ag(s) None SIZA [m] Skip if increment D ata M emory is z ero w ith re sult in A CC Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] + 1 Skip if A CC=0 Affected fl ag(s) None SNZ [m].i Skip i f b it i of D ata M emory i s n ot 0 Description If b it i o f t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m].i ≠ 0 Affected fl ag(s) None SUB A,[m] Subtract D ata M emory from A CC Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C

Rev. 1.60 160 Deee 1 016 Rev. 1.60 161 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SUBM A,[m] Subtract D ata M emory from A CC wi th r esult i n D ata M emory Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he D ata M emory. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C SUB A,x Subtract im mediate data f rom A CC Description The im mediate data s pecified b y t he c ode i s s ubtracted f rom t he c ontents o f t he A ccumulator. The re sult is s tored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C flag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − x Affected fl ag(s) OV, Z , A C, C SWAP [m] Swap ni bbles of D ata M emory Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Operation [m].3~[m].0 ↔ [ m].7~[m].4 Affected fl ag(s) None SWAPA [m] Swap ni bbles of D ata M emory w ith r esult i n A CC Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Th e result i s s tored i n t he A ccumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.3~ACC.0 ← [ m].7~[m].4 ACC.7~ACC.4 ← [ m].3~[m].0 Affected fl ag(s) None SZ [m] Skip i f D ata M emory i s 0 Description If t he contents of t he s pecified D ata M emory i s 0, t he following i nstruction i s s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m]=0 Affected fl ag(s) None SZA [m] Skip i f D ata M emory i s 0 w ith data m ovement to A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. I f t he v alue i s z ero, the f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] Skip if [ m]=0 Affected fl ag(s) None SZ [m].i Skip i f b it i of D ata M emory i s 0 Description If b it i o f t he sp ecified D ata M emory is 0 , t he f ollowing instruction is s kipped. A s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m].i=0 Affected fl ag(s) None

Rev. 1.60 16 Deee 1 016 Rev. 1.60 163 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver TABRD [m] Read ta ble ( specific p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( specific p age) a ddressed b y t he t able p ointer p air (TBHP a nd T BLP) i s mo ved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None TABRDC [m] Read ta ble ( current p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( TBLP) is moved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None TABRDL [m] Read t able (last p age) t o T BLH a nd D ata M emory Description The l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (TBLP) i s mo ved to t he s pecified D ata M emory a nd t he h igh b yte m oved to T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None XOR A,[m] Logical X OR D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ [ m] Affected fl ag(s) Z XORM A,[m] Logical X OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ XOR″ [ m] Affected fl ag(s) Z XOR A,x Logical X OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ x Affected fl ag(s) Z

Rev. 1.60 16 Deee 1 016 Rev. 1.60 163 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver

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Rev. 1.60 164 Deee 1 016 Rev. 1.60 16 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver 20-pin SOP (300mil) Outline Dimensions /G32/G30 /G31 /G31/G31 /G31/G30 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.9 BSC — C 0.01 — 0.00 C’ — 0.04 BSC — D — — 0.104 E — 0.00 BSC — F 0.004 — 0.01 G 0.016 — 0.00 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.0 BSC — C 0.31 — 0.1 C’ — 1.8 BSC — D — — .6 E — 1.7 BSC — F 0.10 — 0.30 G 0.40 — 1.7 H 0.0 — 0.33 α 0° — 8°

Rev. 1.60 164 Deee 1 016 Rev. 1.60 16 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver 24-pin SOP(300mil) Outline Dimensions /G32/G34 /G31 /G31/G33 /G31/G32 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.9 BSC — C 0.01 — 0.00 C’ — 0.606 BSC — D — — 0.104 E — 0.00 BSC — F 0.004 — 0.01 G 0.016 — 0.00 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7. BSC — C 0.31 — 0.1 C’ — 1.4 BSC — D — — .6 E — 1.7 BSC — F 0.10 — 0.30 G 0.40 — 1.7 H 0.0 — 0.33 α 0° — 8°

Rev. 1.60 166 Deee 1 016 Rev. 1.60 167 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SAW Type 24-pin (4mm×4mm) QFN Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.08 0.030 0.031 A1 0.000 0.001 0.00 A3 — 0.008 BSC — 0.007 0.010 0.01 D 0.16 0.17 0.19 E 0.16 0.17 0.19 e — 0.00 BSC — D 0.10 0.106 0.110 E 0.10 0.106 0.110 L 0.014 0.016 0.018 K 0.008 — — Symbol Dimensions in mm Min. Nom. Max. A 0.700 0.70 0.800 A1 0.000 0.00 0.00 A3 — 0.00 BSC — 0.180 0.0 0.300 D 3.90 4.000 4.00 E 3.90 4.000 4.00 e — 0.00 BSC — D .600 .700 .800 E .600 .700 .800 L 0.30 0.400 0.40 K 0.00 — —

Rev. 1.60 166 Deee 1 016 Rev. 1.60 167 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver 28-pin SOP (300mil) Outline Dimensions /G32/G38 /G31 /G31/G35 /G31/G34 /G41 /G42 /G43 /G44 /G46 /G43/G27 /G47 /G48 /G61 /G45 Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.9 BSC — C 0.01 — 0.00 C’ — 0.70 BSC — D — — 0.104 E — 0.00 BSC — F 0.004 — 0.01 G 0.016 — 0.00 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7. BSC — C 0.31 — 0.1 C’ — 17.9 BSC — D — — .6 E — 1.7 BSC — F 0.10 — 0.30 G 0.40 — 1.7 H 0.0 — 0.33 α 0° — 8°

Rev. 1.60 168 Deee 1 016 Rev. 1.60 169 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver 28-pin SSOP (150mil) Outline Dimensions /G32/G38 /G31 /G31/G35 /G31/G34 /G41 /G42 /G43 /G44 /G46 /G43/G27 /G47 /G48 /G61 /G45 Symbol Dimensions in inch Min. Nom. Max. A — 0.36 BSC — B — 0.14 BSC — C 0.008 — 0.01 C’ — 0.390 BSC — D — — 0.069 E — 0.0 BSC — F 0.004 — 0.010 G 0.016 — 0.00 H 0.004 — 0.010 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 6.0 BSC — B — 3.9 BSC — C 0.0 — 0.30 C’ — 9.9 BSC — D — — 1.7 E — 0.63 BSC — F 0.10 — 0. G 0.41 — 1.7 H 0.10 — 0. α 0° — 8°

Rev. 1.60 168 Deee 1 016 Rev. 1.60 169 Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver SAW Type 32-pin (5mm×5mm) QFN Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.08 0.030 0.031 A1 0.000 0.001 0.00 A3 — 0.008 BSC — 0.007 0.010 0.01 D 0.193 0.197 0.01 E 0.193 0.197 0.01 e — 0.00 BSC — D 0.1 0.16 0.130 E 0.1 0.16 0.130 L 0.014 0.016 0.018 K 0.008 — — Symbol Dimensions in mm Min. Nom. Max. A 0.700 0.70 0.800 A1 0.000 0.00 0.00 A3 — 0.03 BSC — 0.180 0.0 0.300 D 4.900 .000 .100 E 4.900 .000 .100 e — 0.0 BSC — D 3.10 3.0 3.30 E 3.10 3.0 3.30 L 0.3 0.40 0.4 K 0.0 — —

Rev. 1.60 170 Deee 1 016 Rev. 1.60 PB Deee 1 016 BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver BS82B12A-3/BS82C16A-3/BS82D20A-3 Touch Flash MCU with LED/LCD Driver Copyight© 016 y HOLTEK SEMICONDUCTOR INC. The infoation appeaing in this Data Sheet is elieved to e auate at the tie of puliation. Howeve Holtek assues no esponsi ility a ising f o the use of the specifications described. The applications mentioned herein are used solely fo the pupose of illustation and Holtek akes no waanty o epesentation that suh appliations will e suita le without fu the odifi ation no e o ends the use of its poduts fo appliation that ay pesent a isk to huan life due to alfuntion o othewise. Holtek's poduts ae not authoized fo use as itial oponents in life suppot devies o systes. Holtek eseves the ight to alte its products without prior notification. For the most up-to-date information, please visit ou we site at http://www.holtek.o.tw.

Product Information

BS82B12A-3 specifications and overview.

Summary

Touch Flash MCU with LED/LCD Driver December 15, 2016

Description

Touch Flash MCU with LED/LCD Driver December 15, 2016

Source title BS82B12A-3 Datasheet(PDF) - Holtek Semiconductor Inc

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