BS616LV1012 BSI | Alldatasheet
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Revision 1.0 Apr. 20041R0201-BS616LV1012 Very Low Power/Voltage CMOS SRAM 64K X 16 bit
- Wide Vcc operation voltage : 2.4 ~ 3.6V
- Very low power consumption : Vcc = 3.0V C-grade : 22mA (@55ns) operating current I- grade : 23mA (@55ns) operating current C-grade : 17mA (@70ns) operating current I- grade : 18mA (@70ns) operating current 0.4uA (Typ.) CMOS standby current
- High speed access time : -55 55ns -70 70ns
- Automatic power down when chip is deselected
- Three state outputs and TTL compatible
- Fully static operation
- Data retention supply voltage as low as 1.5V
- Easy expansion with CE and OE options
- I/O Configuration x8/x16 selectable by LB and UB pin The BS616LV1012 is a high performance, very low power CMOS Static Random Access Memory organized as 65,536 words by 16 bits and operates from a wide range of 2.4V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.4uA at 3V/25 oC and maximum access time of 55ns at 3V/85 oC. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV1012 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1012 is available in the JEDEC standard 44-pin TSOP Type II and 48-pin BGA package. DESCRIPTION FEATURES Row Decoder Memory Array 512 x 2048 Column I/O Write Driver Sense Amp Column Decoder Data Buffer Output A3 A2 A1 Data Buffer Input Control Gnd Vcc OE WE CE DQ15 DQ0 A15 A13 128 2048 BLOCK DIAGRAM 51218 A14 A12 A0A11 Address Input Buffer A10 Address Input Buffer UB .LB PRODUCT FAMILY PIN CONFIGURATIONS Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. BS616LV1012 G H F E D C B A 12345 A9A8NC IO15 NC A12 NCA11A10 A13 WE IO7 IO14 VCC VSS IO9 IO13 A14 IO12 IO11 IO10 NC NC IO8 LB UB OE A15 IO5 NC IO4 IO3 IO1 IO6 VSS VCC IO2 CE IO0 NC CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 NC OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A10 A11 NC BS616LV1012EC BS616LV1012EI BSI POWER DISSIPATION SPEED (ns) STANDBY (ICCSB1, Max) Operating (ICC, Max) PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE 55ns:2.8~3.6V 70ns:2.5~3.6V Vcc=3.0V Vcc=3.0V 55ns Vcc=3.0V 70ns PKG TYPE BS616LV1012EC TSOP2-44 BS616LV1012AC O C to +70 O C 2.4V ~ 3.6V 55/70 1.3uA 22mA 17mA BGA-48-0608 BS616LV1012EI TSOP2-44 BS616LV1012AI -40 O C to +85 O C 2.4V ~ 3.6V 55/70 2.5uA 23mA 18mA BGA-48-0608
Revision 1.0 Apr. 20042R0201-BS616LV1012 Name Function A0-A15 Address Input These 16 address inputs select one of the 65,536 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE PIN DESCRIPTIONS BSI BS616LV1012 MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT Not selected (Power Down) H X X X X High Z High Z I CCSB, ICCSB1 Output Disabled L H H X X High Z High Z I CC L L Dout Dout I CC H L High Z Dout I CCRead L H L L H Dout High Z I CC LL D i n D i n I CC HL X D i n I CCWrite L L X LH D i n X I CC
Revision 1.0 Apr. 20043R0201-BS616LV1012 SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) M A X . UNITS VDR Vcc for Data Retention CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or V IN ≦ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or V IN ≦ 0.2V -- 0.15 0.8 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns tR Operation Recovery Time See Retention Waveform TRC (2) -- -- ns SYMBOL PARAMETER CONDITIONS MAX. UNIT CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 2.4V ~ 3.6V Industrial -40 O C to +85 O C 2.4V ~ 3.6V DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC ) ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) BSI BS616LV1012 PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc=3.0VVIL Guaranteed Input Low Voltage (2) -0.5 -- 0.8 V Vcc=3.0V 2.0VIH Guaranteed Input High Voltage (3) -- Vcc+0.3 V IIL Input Leakage Current Vcc = Max, V IN = 0V to Vcc -- -- 1 uA ILO Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA Vcc=3.0VVOL Output Low Voltage Vcc = Max, I OL = 2mA -- -- 0.4 V Vcc=3.0VVOH Output High Voltage Vcc = Min, I OH = -1mA 2.4 -- -- V Vcc=3.0V -- -- 23ICC Operating Power Supply Current CE = VIL, IDQ = 0mA, mA Vcc=3.0V -- -- 1ICCSB Standby Current-TTL CE = V IH, IDQ = 0mA mA Vcc=3.0V -- 0.4ICCSB1 Standby Current-CMOS CE ≧ Vcc -0.2V, VIN ≧ Vcc - 0.2V or V IN ≦ 0.2V 2.5 uA SYMBOL PARAMETER RATING UNITS V TERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V T BIAS Temperature Under Bias -40 to +85 O C T STG Storage Temperature -60 to +150 O C P T Power Dissipation 1.0 W I OUT DC Output Current 20 mA V cc Power Supply Voltage V-0.5 to Vcc+0.5 F = Fmax (4) 55ns 70ns 18 (5) (6) (3) 1. Vcc = 1.5V, TA = + 25OC2 . t RC = Read Cycle Time 3. IccDR_MAX. is 0.45uA at TA=70OC.
Revision 1.0 Apr. 20044R0201-BS616LV1012 LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) CE Data Retention Mode Vcc t CDR Vcc t R VIHVIH Vcc VDR 1.5V≥ CE Vcc - 0.2V≥ BSI BS616LV1012 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MAY CHANGE FROM H TO L DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load C L = 30pF+1TTL CL = 100pF+1TTL AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION CYCLE TIME : 55ns (Vcc = 2.8~3.6V) (Vcc = 2.5~3.6V) UNIT tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQV tAA Address Access Time -- -- 55 -- -- 70 ns tELQV tACS Chip Select Access Time -- -- 55 -- -- 70 ns tBA tBA Data Byte Control Access Time ( L B , U B ) - -- - 2 5 - -- - 3 5 n s tGLQV tOE Output Enable to Output Valid -- -- 25 -- -- 35 ns t E1LQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns tBE tBE Data Byte Control to Output Low Z (LB,UB) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 5 -- -- 5 -- -- ns tEHQZ tCHZ Chip Deselect to Output in High Z -- -- 20 -- -- 25 ns tBDO tBDO Data Byte Control to Output High Z ( L B , U B ) - -- - 2 0- -- - 2 5 n s tGHQZ tOHZ Output Disable to Output in High Z -- -- 20 -- -- 25 ns tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns (1) NOTE : 1. tBA is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; t BA is 55ns/70ns (@speed=55ns/70ns) without address toggle. CYCLE TIME : 70ns
Revision 1.0 Apr. 20045R0201-BS616LV1012 BSI BS616LV1012 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC t OHt AA D OUT ADDRESS t OH t OH READ CYCLE3 (1,4) t RC t OE D OUT LB,UB CE OE ADDRESS t CLZ (5) t ACS t CHZ (1,5) t OHZ (5) t OLZ t AA READ CYCLE2 (1,3,4) t CLZ t CHZ (5) D OUT LB,UB CE (5) t BA t ACS NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = V IL. 3. Address valid prior to or coincident with CE transition low. 4. OE = V IL . 5. The parameter is guaranteed but not 100% tested. t BE t BDO t BDO t BA t BE
Revision 1.0 Apr. 20046R0201-BS616LV1012 BSI BS616LV1012 t WR SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC (3) t CW (11) t BW (2) t WP t AW t OHZ (4,10) t AS (3) t DH t DW D IN D OUT WE LB,UB CE OE ADDRESS (5) AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION CYCLE TIME : 55ns (Vcc = 2.8~3.6V) (Vcc = 2.5~3.6V) UNIT tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tE1LWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns tAVWL tAS Address Setup Time 0- -- - 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tWLWH tWP Write Pulse Width 35 -- -- 45 -- -- ns tWHAX tWR Write recovery Time (CE,WE) 0 -- -- 0 -- -- ns tBW tBW Date Byte Control to End of Write ( L B , U B ) 3 5 - -- - 4 5 - -- - n s tWLQZ tWHZ Write to Output in High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 35 -- -- 40 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 20 -- -- 25 ns tWHOX tOW End of Write to Output Active 5 -- -- 5 -- -- ns 1. tBW is 35ns/45ns (@speed=55ns/70ns) with address toggle. ; t BW is 55ns/70ns (@speed=55ns/70ns) without address toggle. (1) NOTE : CYCLE TIME : 70ns
Revision 1.0 Apr. 20047R0201-BS616LV1012 BSI BS616LV1012 WRITE CYCLE2 (1,6) t WC t CW (11) (2) t WP t AW t WHZ (4,10) t AS t WR (3) t DH t DW D IN D OUT WE CE ADDRESS (5) t OW (7) (8) (8,9) t BW LB,UB NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. T WR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = V IL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write.
Revision 1.0 Apr. 20048 R0201-BS616LV1012 ORDERING INFORMATION BSI BS616LV1012 PACKAGE DIMENSIONS TSOP2-44 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described he rein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in signif icant injury or death, including life-support systems and critical medical instruments. BS616LV1012 X X Z Y Y GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free PACKAGE E: TSOP2-44 A: BGA-48-0608
Revision 1.0 Apr. 20049R0201-BS616LV1012 BSI BS616LV1012 PACKAGE DIMENSIONS (continued) 48 mini-BGA (6 x 8) VIEW A 1.4 Max. e 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D 8.0 6.0 EN 48 3.75 E1D1 5.25 NOTES: