BS616LV4017 BSI | Alldatasheet
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Revision 2.1 Jan. 20041 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A10 A11 A12 BS616LV4017EC BS616LV4017EI R0201-BS616LV4017 POWER DISSIPATIONSPEED ( ns ) STANDBY ( I CCSB1 , Max ) ( I CC , Max )PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE 55ns :3.0~5.5V Vcc=3.0V Vcc =3.0V PKG TYPE BS616LV4017DC DICE BS616LV4017EC TSOP2-44 BS616LV4017AC BGA-48-0608 O C to +70 O C 2.4V ~ 5.5V 55 /70 5uA 30uA 21mA 53mA BS616LV4017DI DICE BS616LV4017EI TSOP2-44 BS616LV4017AI BGA-48-0608 -40 O C to +85 O C 2.4V ~ 5.5V 55 /70 10uA 60uA 22mA 55mA Very Low Power/Voltage CMOS SRAM 256K X 16 bit
- Wide Vcc operation voltage : 2.4~5.5V
- Very low power consumption : Vcc = 3.0V C-grade: 26mA (@55ns) operating current I-grade: 27mA (@55ns) operating current C-grade: 21mA (@70ns) operating current I-grade: 22mA (@70ns) operating current 0.45uA (Typ.) CMOS standby current Vcc = 5.0V C-grade: 63mA (@55ns) operating current I-grade: 65mA (@55ns) operating current C-grade: 53mA (@70ns) operating current I-grade: 55mA (@70ns) operating current 2.0uA (Typ.) CMOS standby current
- High speed access time : -55 55ns -70 70ns
- Automatic power down when chip is deselected
- Three state outputs and TTL compatible
- Fully static operation The BS616LV4017 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.45uA at 3.0V/25 oC and maximum access time of 55ns at 3.0V/85 oC. Easy memory expansion is provided by an active LOW chip enable (CE) ,active LOW output enable(OE) and three-state output drivers. The BS616LV4017 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4017 is available in DICE form, JEDEC standard 44-pin TSOP Type II package and 48-ball BGA package. DESCRIPTION FEATURES Row Decoder Memory Array 2048 x 2048 Column I/O Write Driver Sense Amp Column Decoder Data Buffer Output A9 A8 A7 Data Buffer Input Control Gnd Vcc OE WE CE DQ15 DQ0 A13 A14 A15 128 2048 BLOCK DIAGRAM 204822 A17 A16 A10 A12 A6A11 Address Input Buffer Address Input Buffer UB LB PRODUCT FAMILY PIN CONFIGURATIONS Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. BS616LV4017 BSI Operating
- Data retention supply voltage as low as 1.5V
- Easy expansion with CE and OE options
- I/O Configuration x8/x16 selectable by LB and UB pin Vcc= 5.0V Vcc = 5.0V 70ns :2.7~5.5V 70ns 70ns
Revision 2.1 Jan. 20042R0201-BS616LV4017 Name Function A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM. CE Chip Enable Input CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0 - DQ15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE PIN DESCRIPTIONS BSI BS616LV4017 MODE CE WE OE LB UB D0~D7 D8~D15 Vcc CURRENT H X X X X High Z High Z I CCSB , ICCSB1Not selected (Power Down) X X X H H High Z High Z I CCSB , ICCSB1 Output Disabled L H H X X High Z High Z I CC L L Dout Dout I CC H L High Z Dout I CCRead L H L L H Dout High Z I CC LL D i n D i n I CC HL X D i n I CCWrite L L X LH D i n X I CC L XX H H High Z High Z ICC
Revision 2.1 Jan. 20043 CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 2.4V ~ 5.5V Industrial -40 O C to +85 O C 2.4V ~ 5.5V 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) SYMBOL PARAMETER RATING UNITS V TERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V T BIAS Temperature Under Bias -40 to +85 O C T STG Storage Temperature -60 to +150 O C P T Power Dissipation 1.0 W I OUT DC Output Current 20 mA BSI BS616LV4017 PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1 ) MAX. UNITS Vcc=3.0V 0.8VIL Guaranteed Input Low Voltage(2) -0.5 -- V Vcc=3.0V 2.0 VIH Guaranteed Input High Voltage(2) -- Vcc+0.3 V IIL Input Leakage Current Vcc = Max, V IN = 0V to Vcc -- -- 1 uA ILO Output Leakage Current Vcc = Max, CE = V IH , or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA Vcc=3.0V VOL Output Low Voltage -- -- V Vcc=3.0V VOH Output High Voltage -- -- V Vcc=3.0V 22ICC Operating Power Supply Current CE=VIL ,IDQ= 0mA, F=Fmax (3) -- -- mA Vcc=3.0V 0.5 ICCSB Standby Current-TTL CE = VIH, I DQ= 0mA -- -- mA Vcc=3.0V 0.45 10 ICCSB1 Standby Current-CMOS CE ≧Vcc-0.2V, VIN ≧ Vcc - 0.2V or VIN ≦0.2V -- uA SYMBOL PARAMETER CONDITIONS MAX. UNIT R0201-BS616LV4017 2.0 60Vcc=5.0V Vcc=5.0V 2.2 Vcc=5.0V Vcc=5.0V Vcc=5.0V Vcc=5.0V Vcc=5.0V 0.8 2.4 1.0 0.4 2.4 Vcc = Max, IOL = 2.0mA Vcc = Min, IOH = -1.0mA (4) 0.4 70ns 70ns (5)
Revision 2.1 Jan. 20044 BSI BS616LV4017 SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR Vcc for Data Retention CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE ≧ Vcc - 0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.3 1.3 uA tCDR Chip Deselect to Data Retention Time 0- -- - n s tR Operation Recovery Time See Retention Waveform TRC (2) -- -- ns DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.8uA at TA=70OC. R0201-BS616LV4017 LOW VCC DATA RETENTION WAVEFORM ( CE Controlled ) CE Data Retention Mode Vcc t CDR Vcc t R VIHVIH Vcc VDR 1.5V≥ CE Vcc - 0.2V≥ (3)
Revision 2.1 Jan. 20045R0201-BS616LV4017 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MAY CHANGE FROM H TO L DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H BSI BS616LV4017 Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load C L = 30pF+1TTL CL = 100pF+1TTL JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION (Vcc = 2.7~5.5V) (Vcc = 3.0~5.5V) UNIT tAVAX tRC Read Cycle Time 70 -- -- 55 -- -- ns tAVQV tAA Address Access Time -- -- 70 -- -- 55 ns tELQV tACS Chip Select Access Time -- -- 70 -- -- 55 ns tBA tBA Data Byte Control Access Time ( L B , U B ) - -- - 3 5 - -- - 3 0 n s tGLQV tOE Output Enable to Output Valid -- -- 35 -- -- 30 ns t E1LQX tCLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns tBE tBE Data Byte Control to Output Low Z (LB,UB) 5 -- -- 5 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 5- -- -5- -- - n s tEHQZ tCHZ Chip Deselect to Output in High Z -- -- 35 -- -- 30 ns tBDO tBDO Data Byte Control to Output High Z (LB,UB) -- -- 35 -- -- 30 ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 30 -- -- 25 ns tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns (1) NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; t BA is 70ns/55ns (@speed=70ns/55ns) without address toggle. CYCLE TIME : 70ns CYCLE TIME : 55ns
Revision 2.1 Jan. 20046R0201-BS616LV4017 NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = V IL. 3. Address valid prior to or coincident with CE transition low. 4. OE = V IL . 5. The parameter is guaranteed but not 100% tested. BSI BS616LV4017 t OH READ CYCLE3 (1,4) t RC t OE D OUT LB,UB CE OE ADDRESS t CLZ t ACS t CHZ (1,5) t OHZ t OLZ t AA READ CYCLE2 (1,3,4) t CLZ t CHZ D OUT LB,UB CE t BA t ACS t BE t BDO t BDO t BA t BE (5) (5) (5) (5) SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC t OHt AA D OUT ADDRESS t OH
Revision 2.1 Jan. 20047R0201-BS616LV4017 SWITCHING WAVEFORMS (WRITE CYCLE) BSI BS616LV4017 t WR WRITE CYCLE1 (1) t WC (3) t CW (10) t BW (2) t WP t AW t OHZ (4,11) t AS (3) t DH t DW D IN D OUT WE LB,UB CE OE ADDRESS (5) AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION (Vcc = 2.7~5.5V) (Vcc = 3.0~5.5V) UNIT tAVAX tWC Write Cycle Time 70 -- -- 55 -- -- ns tE1LWH tCW Chip Select to End of Write 70 -- -- 55 -- -- ns tAVWL tAS Address Setup Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 70 -- -- 55 -- -- ns tWLWH tWP Write Pulse Width 35 -- -- 30 -- -- ns tWHAX tWR Write recovery Time (CE,WE) 0 -- -- 0 -- -- ns tBW tBW Date Byte Control to End of Write (LB,UB) 30 -- -- 25 -- -- ns tWLQZ tWHZ Write to Output in High Z -- -- 30 -- -- 25 ns tDVWH tDW Data to Write Time Overlap 30 -- -- 25 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 30 -- -- 25 ns tWHOX tOW End of Write to Output Active 5 -- -- 5 -- -- ns WRITE CYCLE 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; t BW is 70ns/55ns (@speed=70ns/55ns) without address toggle. (1) NOTE : CYCLE TIME : 70ns CYCLE TIME : 55ns
Revision 2.1 Jan. 20048R0201-BS616LV4017 WRITE CYCLE2 (1,6) BSI BS616LV4017 t WC t CW (10) (2) t WP t AW t WHZ (4,11) t AS t WR (3) t DH t DW D IN D OUT WE CE ADDRESS (5) t OW (7) (8) (8,9) t BW LB,UB NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. T WR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = V IL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. TCW is measured from the later of CE going low to the end of write. 11. The parameter is guaranteed but not 100% tested.
Revision 2.1 Jan. 20049 R0201-BS616LV4017 ORDERING INFORMATION BSI BS616LV4017 PACKAGE DIMENSIONS TSOP2-44 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described he rein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in signif icant injury or death, including life-support systems and critical medical instruments. BS616LV4017 X X Z Y Y GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free PACKAGE E: TSOP2-44 A: BGA-48-0608 D: DICE
Revision 2.1 Jan. 200410 BS616LV4017BSI R0201-BS616LV4017 PACKAGE DIMENSIONS (continued) 48 mini-BGA (6 x 8mm) E0 . 1 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. N E D NOTES: 48 8.0 6.0 E1D1 3.755.25 SIDE VIEW D0 . 1 1.4 Max. e 0.25 ± 0.05 SOLDER BALL 0.35 ± 0.05 VIEW A