BS616LV1611_06 BSI | Alldatasheet
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May. 2006 1 Pb-Free and Green package materials are compliant to RoHS n FEATURES Wide VCC operation voltage : 2.4V ~ 5.5V Very low power consumption : V CC = 3.0V Operation current : 46mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25 OC V CC = 5.0V Operation current : 115mA (Max.) at 55ns 10mA (Max.) at 1MHz Standby current : 6.0uA (Typ.) at 25 OC High speed access time : -55 55ns(Max.) at V CC=3.0~5.5V -70 70ns(Max.) at V CC=2.7~5.5V Automatic power down when chip is deselected Easy expansion with CE2, CE1 and OE options I/O Configuration x8/x16 selectable by LB and UB pin. Three state outputs and TTL compatible Fully static operation, no clock, no refresh Data retention supply voltage as low as 1.5V n DESCRIPTION The BS616LV1611 is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,576 by 16 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 1.5uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE1), active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers. The BS616LV1611 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1611 is available in 48-pin TSOP Type I package and 48-ball BGA package. n POWER CONSUMPTION POWER DISSIPATION STANDBY (ICCSB1, Max) Operating (ICC, Max) VCC=5.0V VCC=3.0V PRODUCT FAMILY OPERATING TEMPERATURE VCC=5.0V VCC=3.0V 1MHz 10MHz fMax. 1MHz 10MHz fMax. PKG TYPE BS616LV1611FC BGA-48-0912 BS616LV1611TC Commercial +0OC to +70OC 50uA 8.0uA 9mA 48mA 113mA 1.5mA 19mA 45mA TSOP I-48 BS616LV1611FI BGA-48-0912 BS616LV1611TI Industrial -40OC to +85OC 100uA 16uA 10mA 50mA 115mA 2mA 20mA 46mA TSOP I-48 n PIN CONFIGURATIONS n BLOCK DIAGRAM Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. Address Input Buffer Row Decoder Memory Array 1024 x 16384 Column I/O Write Driver Sense Amp Column Decoder Address Input Buffer A16 A0 A1 A2 Data Input Buffer Control DQ0 DQ15 A13 A12 A11 A10 1024 16384 1024 10 A14 Data Output Buffer A18 CE2 CE1 WE OE UB LB VCC VSS A17 A15 A19 CE1 DQ0 DQ1 DQ2 DQ3 VCC NC VSS DQ4 DQ5 DQ6 DQ7 A19 WE A18 A17 A16 A15 A14 BS616LV1611TC BS616LV1611TI OE UB LB CE2 NC DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 A10 A11 A12 A13 G H F E D C B A 1 2 3 4 5 6 A9 A11 A10 NC A12 A14 A13 A15 WE D13 D5 A17 A16 VSS VCC D12 D11 NC OE A1 A2 CE2 UB D10 D1 CE1 48-ball BGA top view LB VSS VCC D14 D15 A18 A19
May. 2006 2 n PIN DESCRIPTIONS Name Function A0-A19 Address Input These 20 address inputs select one of the 1,048,576 x 16 bit in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0-DQ15 Data Input/Output Ports 16 bi-directional ports are used to read data from or write data into the RAM. VCC Power Supply VSS Ground n TRUTH TABLE MODE CE1 CE2 WE OE LB UB DQ0~DQ7 DQ8~DQ15 VCC CURRENT H X X X X X High Z High Z ICCSB, ICCSB1 X L X X X X High Z High Z ICCSB, ICCSB1 Chip De-selected (Power Down) X X X X H H High Z High Z ICCSB, ICCSB1 L H H H L X High Z High Z ICC Output Disabled L H H H X L High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC Read L H H L L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC Write L H L X L H DIN X ICC NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
May. 2006 3 n ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS VTERM Terminal Voltage with Respect to GND -0.5(2) to 7.0 V TBIAS Temperature Under Bias -40 to +125 OC TSTG Storage Temperature -60 to +150 OC PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. n OPERATING RANGE RANG AMBIENT TEMPERATURE VCC Commercial 0OC to + 70OC 2.4V ~ 5.5V Industrial -40OC to + 85OC 2.4V ~ 5.5V n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS CIN Input Capacitance VIN = 0V 6 pF CIO Input/Output Capacitance VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS VCC Power Supply 2.4 -- 5.5 V VIL Input Low Voltage -0.5(2) -- 0.8 V VIH Input High Voltage 2.2 -- VCC+0.3(3) V IIL Input Leakage Current VIN = 0V to VCC, CE1 = VIH or CE2 = VIL -- -- 1 uA ILO Output Leakage Current VI/O = 0V to V CC, CE1 = VIH or CE2 = VIL or OE = VIH -- -- 1 uA VOL Output Low Voltage VCC = Max, I OL = 2.0mA -- -- 0.4 V VOH Output High Voltage VCC = Min, I OH = -1.0mA 2.4 -- -- V VCC=3.0V 46 ICC (5) Operating Power Supply Current CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = FMAX (4) VCC=5.0V -- -- 115 mA VCC=3.0V 2 ICC1 Operating Power Supply Current CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = 1MHz VCC=5.0V -- -- mA VCC=3.0V 1.0 ICCSB Standby Current – TTL CE1 = VIH, or CE2 = VIL, IDQ = 0mA VCC=5.0V -- -- 2.0 mA VCC=3.0V 1.5 16 ICCSB1 (6) Standby Current – CMOS CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or V IN≦0.2V VCC=5.0V 6.0 100 uA 1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC.
May. 2006 4 n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR VCC for Data Retention CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V 1.5 -- -- V ICCDR (3) Data Retention Current CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V -- 0.8 8.0 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns tR Operation Recovery Time See Retention Waveform tRC (2) -- -- ns 1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCDR(Max.) is 6.0uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled) n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled) n AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Output Load Others CL = 30pF+1TTL 1. Including jig and scope capacitance. n KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE CE2 Data Retention Mode VCC tCDR VCC tR VIL VIL VCC VDR≧1.5V CE2≦0.2V Data Retention Mode VCC tCDR VCC tR VIH VIH CE1≧VCC - 0.2V VDR≧1.5V CE1 VCC CL (1)
1 TTL
→ ← 90% VCC GND Rise Time: 1V/ns Fall Time: 1V/ns 90% → ← 10% 10%
May. 2006 5 n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) READ CYCLE CYCLE TIME : 55ns (VCC=3.0~5.5V) CYCLE TIME : 70ns (VCC=2.7~5.5V) JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION UNITS tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tELQV1 tACS1 Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns tELQV2 tACS2 Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns tBLQV tBA Data Byte Control Access Time (LB, UB) -- -- 55 -- -- 70 ns tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns tELQX1 tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns tELQX2 tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns tBLQX tBE Data Byte Control to Output Low Z (LB, UB) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output Low Z 5 -- -- 5 -- -- ns tEHQZ1 tCHZ1 Chip Select to Output High Z (CE1) -- -- 30 -- -- 35 ns tEHQZ2 tCHZ2 Chip Select to Output High Z (CE2) -- -- 30 -- -- 35 ns tBHQZ tBDO Data Byte Control to Output High Z (LB, UB) -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC tOH tAA DOUT ADDRESS tOH
May. 2006 6 READ CYCLE 2 (1,3,4) READ CYCLE 3 (1, 4) NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. tCLZ (5) DOUT CE2 CE1 tACS2 tACS1 tCHZ (5) tOH tRC tOE tBE tBDO DOUT CE1 OE ADDRESS tCLZ1 (5) tACS1 tCHZ (1,5) tOHZ (5) tOLZ tAA LB, UB tBA tCLZ2 (5) tCHZ2 (2,5) CE2 tACS2
May. 2006 7 n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) WRITE CYCLE CYCLE TIME : 55ns (VCC=3.0~5.5V) CYCLE TIME : 70ns (VCC=2.7~5.5V) JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION UNITS tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tELWH tCW Chip Select to End of Write 55 -- -- 70 -- -- ns tBLWH tBW Data Byte Control to End of Write (LB, UB) 25 -- -- 30 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX1 tWR1 Write Recovery Time (CE1, WE) 0 -- -- 0 -- -- ns tWHAX2 tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC tWR1 (3) tCW (11) tWP (2) tAW tOHZ (4,10) tAS tWR2 (3) tDH tDW DIN DOUT WE LB, UB CE1 OE ADDRESS (5) tBW tCW (11) CE2 (5)
May. 2006 8 WRITE CYCLE 2 (1,6) NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = V IL). 7. D OUT is the same phase of write data of this write cycle. 8. D OUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write. 12. The change of Read/Write cycle must accompany with CE or address toggled. tWC tCW (11) tWP (2) tAW tWHZ (4,10) tAS tWR (3) tDH tDW DIN DOUT WE LB, UB CE1 ADDRESS (5) tOW (7) (8) (8,9) tBW (12) tCW (11) CE2
May. 2006 9 n ORDERING INFORMATION Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS E±0.1 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. N E D NOTES: 48 12.0 9.0 E1 D1 e 3.75 5.25 0.75 SIDE VIEW D 0.1 1.4 Max. e 0.25±0.05 SOLDER BALL 0.35 ±0.05 VIEW A 3.375 2.625 48 mini-BGA (9mm x 12mm) PACKAGE F: BGA-48-0912 T: TSOP I-48 BS616LV1611 X X Z Y Y GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant
May. 2006 10 n PACKAGE DIMENSIONS TSOP I-48 Pin (12mm x 20mm)
May. 2006 11 n Revision History Revision No. History Draft Date Remark 2.2 Add Icc1 characteristic parameter Jan. 13, 2006 Improve Iccsb1 spec. I-grade from 220uA to 100uA at 5.0V 20uA to 16uA at 3.0V C-grade from 110uA to 50uA at 5.0V 10uA to 8.0uA at 3.0V 2.3 Change I-grade operation temperature range May. 25, 2006 - from –25OC to –40OC