BS62LV1024 BSI | Alldatasheet

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Revision 2.2 April 20011 R0201-BS62LV1024 Very Low Power/Voltage CMOS SRAM 128K X 8 bit

  • Wide Vcc operation voltage : 2.4V ~ 5.5V
  • Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current I- grade : 25mA (Max.) operating current 0.02uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.4uA (Typ.) CMOS standby current
  • High speed access time : -70 70ns (Max.) at Vcc = 3.0V
  • Automatic power down when chip is deselected
  • Three state outputs and TTL compatible
  • Fully static operation
  • Data retention supply voltage as low as 1.5V
  • Easy expansion with CE2, CE1, and OE options „ FEATURES The BS62LV1024 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.02uA and maximum access time of 70ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1024 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4mm STSOP and 8mmx20mm TSOP. „ DESCRIPTION „ BLOCK DIAGRAM „ PRODUCT FAMILY „ PIN CONFIGURATIONS Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. BS62LV1024 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 NC A16 A14 A12 DQ0 DQ1 DQ2 GND VCC A15 CE2 WE A13 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 A11 A13 WE CE2 A15 VCC NC A16 A14 A12 BS62LV1024TC BS62LV1024STC BS62LV1024TI BS62LV1024STI BS62LV1024SC BS62LV1024SI BS62LV1024PC BS62LV1024PI BS62LV1024JC BS62LV1024JI Address Input Buffer Row Decoder Memory Array 1024 x 1024 Column I/O Sense Amp Write Driver Column Decoder Data Buffer Output Address Input Buffer A3 A2 A1 A0 A10 Data Buffer Input Control Gnd Vdd OE WE CE1 DQ5 DQ4 A14 A13 A12 DQ7 DQ6 DQ3 DQ2 DQ1 DQ0 A11 128 1024 102420 A16 A15 A4A5 CE2 BSI POWER DISSIPATIONSPEED (ns) Standby (IccSB1, M ax) Operat i ng (Icc, Max) PRODUCT FAM ILY OPERATING TEMPERATURE Vcc RANGE Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V PKG TYPE BS62LV P-321024SC SO BS62LV OP-321024TC TS BS62LV SOP-321024STC ST BS62LV IP-321024PC PD BS62LV J-321024JC SO BS62LV CE1024DC +0 O C to +70 O C 2.4V ~ 5.5V 70 3.0uA 1.0uA 35mA 20mA DI BS62LV P-321024SI SO BS62LV OP-321024TI TS BS62LV SOP-321024STI ST BS62LV IP-321024PI PD BS62LV J-321024JI SO BS62LV CE1024DI -40 O C to +85 O C 2.4V ~ 5.5V 70 5.0uA 1.5uA 40mA 25mA DI

Revision 2.2 April 20012 R0201-BS62LV1024 BSI BS62LV1024 SYMBOL PARAMETER CONDITIONS MAX. UNIT CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF „ ABSOLUTE MAXIMUM RATINGS(1) „ OPERATING RANGE „ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. This parameter is guaranteed and not tested. SYMBOL PARAMETER RATING UNITS V TERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V T BIAS Temperature Under Bias C -40 to +125 O T STG Storage Temperature C -60 to +150 O P T Power Dissipation 1.0 W I OUT DC Output Current 20 mA RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C2 . 4 V ~ 5 . 5 V Industrial -40 O C to +85 O C2 . 4 V ~ 5 . 5 V „ TRUTH TABLE „ PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT XHXXNot selected (Power Down) XXLX High Z I CCSB, ICCSB1 Output Disabled H L H H High Z I CC Read H L H L D OUT ICC Write L L H X D IN ICC

Revision 2.2 April 20013 R0201-BS62LV1024 BSI BS62LV1024 PARAMETER NAME PARAMETER TEST CONDITIONS M I N . T Y P . M A X . (1) UNITS Vcc=3.0V VIL Guaranteed Input Low Voltage(2) Vcc=5.0V -0.5 -- 0.8 V Vcc=3.0V 2.0 VIH Guaranteed Input High Voltage(2) Vcc=5.0V 2.2 -- Vcc+0.2 V IIL Input Leakage Current Vcc = Max, V IN = 0V to Vcc -- -- 1 uA IOL Output Leakage Current Vcc = Max, CE1= VIH, CE2= VIL, or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA Vcc=3.0V VOL Output Low Voltage Vcc = Max, I OL = 2mA Vcc=5.0V -- -- 0.4 V Vcc=3.0V VOH Output High Voltage Vcc = Min, I OH = -1mA Vcc=5.0V 2.4 -- -- V Vcc=3.0V -- -- 20 ICC Operating Power Supply Current CE1 = VIL, or CE2 = VIH, IDQ = 0mA, F = Fmax(3) Vcc=5.0V -- -- 35 mA Vcc=3.0V -- -- 1 ICCSB Standby Current-TTL CE1 = VIH, or CE2 = VIL, IDQ = 0mA, F = Fmax(3) Vcc=5.0V -- -- 2 mA Vcc=3.0V -- 0.02 1 ICCSB1 Standby Current-CMOS CE1ЊVcc-0.2V, CE2Љ0.2V, VINЊVcc-0.2V or VINЉ0.2V Vcc=5.0V -- 0.4 3 uA 1. Typical characteristics are at TA = 25oC. 3. Fmax = 1/tRC . 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. „ DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time „ DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) „ LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) CE1 Data Retention Mode Vcc t CDR Vcc t R VIHVIH Vcc VDR 1.5V≥ CE1 Vcc - 0.2V≥ „ LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) SYMBOL PARAMETER TEST CONDITIONS M I N . T Y P . (1) M A X . UNITS VDR Vcc for Data Retention CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, VIN Њ Vcc - 0.2V or V IN Љ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V, VIN Њ Vcc - 0.2V or V IN Љ 0.2V -- 0.02 0.3 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns tR Operation Recovery Time See Retention Waveform TRC (2) -- -- ns CE2 Data Retention Mode Vcc t CDR Vcc t R VILVIL Vcc VDR Њ 1.5V CE2 Љ 0.2V

Revision 2.2 April 20015 R0201-BS62LV1024 READ CYCLE3 (1,4) READ CYCLE2 (1,3,4) NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = V IL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = V IL . 5. Transition is measured 500mV from steady state with C L = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. BSI „ SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC t OHt AA D OUT ADDRESS t OH t CLZ (5) D OUT CE2 CE1 (5) t ACS2 t ACS1 t OH t RC t OE t CLZ2 t CHZ2 (2,5) D OUT CE2 CE1 OE ADDRESS (5) t CLZ1 (5) tACS1 t ACS2 t CHZ1 (1,5) t OHZ (5) t OLZ t AA BS62LV1024 t CHZ1, t CHZ2

Revision 2.2 April 20016 R0201-BS62LV1024 JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION BS62LV1024-70 MIN. TYP. MAX. UNIT tAVAX Write Cycle TimetWC 70 -- -- ns tE1LWH tCW Chip Select to End of Write 70 -- -- ns tAVWL tAS Address Set up Time 0- -- - n s tAVWH tAW Address Valid to End of Write 70 -- -- ns tWLWH tWP Write Pulse Width 50 -- -- ns tWHAX tWR1 Write Recovery Time (CE1 , WE) 0- -- - n s tE2LAX tWR2 Write Recovery Time (CE2) 0- -- - n s tWLOZ tWHZ Write to Output in High Z 0- - 3 0 n s tDVWH tDW Data to Write Time Overlap 30 -- -- ns tWHDX tDH Data Hold from Write Time 0- -- - n s tGHOZ tOHZ Output Disable to Output in High Z 0- - 3 0 n s tWHQX tOW End of Write to Output Active 5- -- - n s „ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=3.0V ) WRITE CYCLE „ SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) BSI BS62LV1024 t WR1 t WC (3) t CW (11) (11) t CW (2) t WP t AW t OHZ (4,10) t AS t WR2 (3) t DH t DW D IN D OUT WE CE2 CE1 OE ADDRESS (5) (5)

Revision 2.2 April 20017 R0201-BS62LV1024 NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with C L = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. WRITE CYCLE2 (1,6) BSI BS62LV1024 t WC t CW (11) (11) t CW (2) t WP t AW t WHZ (4,10) t AS t WR2 (3) t DH t DW D IN D OUT WE CE2 CE1 ADDRESS (5) (5) t DH (7) (8) (8,9)

Revision 2.2 April 20018 R0201-BS62LV1024 PACKAGE J: SOJ S: SOP P: PDIP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) D: DICE „ ORDERING INFORMATION BSI BS62LV1024 X X ˀˀ Y Y GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC SPEED 70: 70ns „ PACKAGE DIMENSIONS BS62LV1024 BASE METAL WITH PLATING c c1 SECTION A-A b SOP -32

Revision 2.2 April 20019 R0201-BS62LV1024 BSI BS62LV1024 „ PACKAGE DIMENSIONS (continued) TSOP - 32 STSOP - 32

Revision 2.2 April 200110 R0201-BS62LV1024 BSI BS62LV1024 „ PACKAGE DIMENSIONS (continued) PDIP - 32 SOJ - 32

Revision 2.2 April 200111 BSI R0201-BS62LV1024

REVISION HISTORY

Revision Description Date Note 2.2 2001 Data Sheet release Apr. 15, 2001 BS62LV1024