BS128HD8V

AM29BDS128H AMD | Alldatasheet

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Publication Number 27024 Revision B Amendment 3 Issue Date May 10, 2006 Am29BDS128H/Am29BDS640H Data Sheet RETIRED PRODUCT (AM29BDS40H ONLY) The Am29BDS640H has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for speci- fications and ordering information. The Am29BDS128H is available and is not affected by this revi- sion. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support the Am29BDS640H pa rt numbers. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

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Publication# 27024 Rev: B Amendment: 3 Issue Date: May 10, 2006 Am29BDS128H/Am29BDS640H 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) ■ Manufactured on 0.13 µm process technology ■ VersatileIO™ (V IO) Feature — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.8V compatible I/O signals ■ Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture:

128 Mb has 16/48/48/16 Mbit banks

64 Mb has 8/24/24/8 Mbit banks

■ Programable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst ■ SecSi TM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Sector Architecture — Banks A and D each contain both 4 Kword sectors and 32 Kword sectors; Banks B and C contain ninety-six 32 Kword sectors — Sixteen 4 Kword boot sectors Half of the boot sectors are at the top of the address range; half are at the bottom of address range ■ Minimum 1 million erase cycle guarantee per sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ 80-ball FBGA package (128 Mb) or 64-ball FBGA (64 Mb) package PERFORMANCE CHARCTERISTICS ■ Read access times at 75/66/54 MHz (CL=30 pF) — Burst access times of 9.3/11/13.5 ns at industrial temperature range — Synchronous latency of 49/56/69 ns — Asynchronous random access times of 45/50/55 ns ■ Power dissipation (typical values, CL = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA HARDWARE FEATURES ■ Handshaking feature — Provides host system with minimum possible latency by monitoring RDY — Reduced Wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses ■ Hardware reset input (RESET#) — Hardware method to reset the device for reading array data ■ WP# input — Write protect (WP#) function allows protection of the four highest and four lowest 4 kWord boot sectors, regardless of sector protect status ■ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL ■ CMOS compatible inputs, CMOS compatible outputs ■ Low VCC write inhibit SOFTWARE FEATURES ■ Supports Common Flash Memory Interface (CFI) ■ Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families ■ Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion ■ Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Burst Suspend/Resume — Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state The Am29BDS640H has been retired and is not recommended for desi gns. For new designs, S29WS064K supersedes Am29BDS640H. Please refer to the S29WS-K family data sheet for specifications and ordering information. The Am29BDS128H is available and is not affected by this revision.

2 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

The Am29BDS128H/Am29BDS640H is a 128 or 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash mem- ory device, organized as 8,388,608 or 4,194,304 words of 16 bits each. This device uses a single V CC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VHH on ACC may be used for faster program performance if de- sired. The device can also be programmed in standard EPROM programmers. At 75 MHz, the device provides a burst access of 9.3 ns at 30 pF with a latency of 49 ns at 30 pF . At 66 MHz, the device provides a burst access of 11 ns at 30 pF with a latency of 56 ns at 30 pF . At 54 MHz, the device provides a burst ac- cess of 13.5 ns at 30 pF with a latency of 69ns at 30 pF . The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in FBGA packages. The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simult aneously read from another bank, with zero latency. This releases the system from wait- ing for the completion of program or erase operations. The device is divided as shown in the following table: The VersatileIO™ (V IO) control allows the host system to set the voltage levels that the device generates at its data out- puts and the voltages tolerated at its data inputs to the same voltage level that is asserted on the V IO pin. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst opera- tions, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/micro- controllers for high performance read operations. The burst read mode feature gives system designers flexibil- ity in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The ac- tive clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power -supply Flash standard . Com- mands are written to the co mmand register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase su spend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also rese t the device, enabling the system mi croprocessor to re ad boot-up firm- ware from the Flash memory device. The host system can detect whether a program or erase op- eration is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (t oggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed witho ut affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhi bits write operations during power transitions. The device also offers two types of data protection at the sector level. When at V IL, WP# locks the four highest and four lowest boot sectors. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power con- sumption is greatly reduced in both modes. AMD Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Bank Quantity Size128 Mb 64 Mb A 8 8 4 Kwords 31 15 32 Kwords B 96 48 32 Kwords C 96 48 32 Kwords D 31 15 32 Kwords 8 8 4 Kwords

4 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 16. CLK Synchronous Burst Mode Read (rising active CLK) ... Figure 17. CLK Synchronous Burst Mode Read (Falling Active Clock) Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at Figure 22. Reduced Wait-state Handshake Burst Suspend/Resume at Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Figure 25. Standard Handshake Burst Suspend Prior to Initial Access Figure 26. Standard Handshake Burst Suspend at or after Initial Ac- Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Start- Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh Figure 29. Standard Handshake Burst Suspend at Address 3Eh/3Fh Figure 34. Asynchronous Program Operation Timings: AVD# Latched Figure 35. Asynchronous Program Operation Timings: WE# Latched Figure 36. Synchronous Program Operation Timings: WE# Latched Figure 37. Synchronous Program Operation Timings: CLK Latched Figure 40. Data# Polling Timings (During Embedded Algorithm) .. 76 Figure 42. Synchronous Data Polling Timings/Toggle Bit Timings 77 Figure 45. Sector/Sector Block Protect and Figure 47. Latency with Boundary Crossing

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 5 DATA SHEET PRODUCT SELECTOR GUIDE Note: Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC Characteristics section of this data sheet for full specifications. BLOCK DIAGRAM Note: Amax = A22 (128 Mb) or A21 (64 Mb) Part Number Am29BDS128H/Am29BDS640H Burst Frequency 66 MHz 54 MHz Speed Option V CC, VIO = 1.65 – 1.95 V E8, E9 D8, D9 Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Even Address 56 69 Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking 71 87.5 Max Burst Access Time, ns (TBACC) 11 13.5 Max Asynchronous Access Time, ns (TACC) 50 55 Max CE# Access Time, ns (TCE) Max OE# Access Time, ns (TOE) 11 13.5 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS VIO WE# RESET# WP# ACC CE# OE# DQ15–DQ0 Data Latch Y-Gating Cell Matrix Address Latch Amax–A0 RDY Buffer RDY Burst State Control Burst Address Counter AVD# CLK

6 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT VSS VCC VIO Bank B Address RESET# ACC WE# CE# AVD# RDY DQ15–DQ0 WP# STATE CONTROL COMMAND REGISTER Bank B X-Decoder Y-Decoder Latches and Control Logic Bank A X-Decoder Y-Decoder Latches and Control Logic DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Bank C Y-Decoder X-Decoder Latches and Control Logic Bank D Y-Decoder X-Decoder Latches and Control Logic OE# Status Control Amax–A0 Amax–A0 Bank C Address Bank D Address Bank A Address Amax–A0 Amax –A0 Amax –A0

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 7 DATA SHEET CONNECTION DIAGRAM C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC NCNC NC NC NC NC NC NC NC NC NCNC NC NC NC DQ15 VSSNCA16A15A14A12A13 C8 D8 E8 F8 G8 H8 J8 K8 NC NCNCVSSVIONCA22NC DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18ACCRDY DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 C1 D1 E1 F1 G1 H1 J1 K1 VSS NCVIOAVD#WP#CLKVCCNC 80-ball Fine-Pitch Ball Grid Array Top View, Balls Facing Down (Am29BDS128H only)

8 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 A7 B7 C7 D7 E7 F7 G7 H7 DQ15 VSSNCA16A15A14A12A13 A8 B8 C8 D8 E8 F8 G8 H8 NC NCNCVSSVIONCNCNC DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18ACCRDY DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 A1 B1 C1 D1 E1 F1 G1 H1 VSS NCVIOAVD#WP#CLKVCCNC 64-ball Fine-Pitch Ball Grid Array Top View, Balls Facing Down (Am29BDS640H only)

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 9 DATA SHEET INPUT/OUTPUT DESCRIPTIONS Amax–A0 = Address inputs Amax = A22 (128 Mb) or A21 (64 Mb) DQ15–DQ0 = Data input/output CE# = Chip Enable input. Asynchronous relative to CLK for the Burst mode. OE# = Output Enable input. Asynchronous relative to CLK for the Burst mode. WE# = Write Enable input. V CC = Device Power Supply (1.65 – 1.95 V). VIO = Input & Output Buffer Power Supply (1.65 – 1.95 V). VSS =G r o u n d NC = No Connect; not connected internally RDY = Ready output; In Synchronous Mode, indicates the status of the Burst read. Low = data invalid. High = data valid. In Asynchronous Mode, indicates the status of the internal program and erase function. Low = program/erase in progress. High Impedance = program/erase completed. CLK = CLK is not requir ed in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. AVD# = Address Valid input. Indicates to device that the valid address is present on the address inputs (Amax–A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs RESET# = Hardware reset input. Low = device resets and returns to reading array data WP# = Hardware write protect input. At V IL, disables program and erase functions in the four highest and four lowest sectors. At V IH, does not protect any sectors. ACC = At V HH, accelerates programming; automatically places device in unlock bypass mode. At V IL, locks all sectors. Should be at VIH for all other conditions. LOGIC SYMBOL 23 or 22 DQ15–DQ0 Amax–A0 CE# OE# WE# RESET# CLK RDY AVD# WP# ACC

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ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm avail- ability of specific valid combinati ons and to check on newly released combinations. Am29BDS 128 H E 8 VK I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE VK = 80-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 11.5 x 9 mm package (VBB080) VF = 80-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 11.5 x 9mm, Pb-free Package (VBB080) VM = 64-Ball Fine-Pitch Ball Grid Array (BGA) 0.80 mm pitch, 8 X 9 mm package (VBD064) VIO AND HANDSHAKING OPTIONS 8= V IO = 1.8 V, reduced wait-state handshaking enabled 9= V IO = 1.8 V, standard handshaking SPEED E = 66 MHz D = 54 MHz PROCESS TECHNOLOGY H = 0.13 µm DENSITY 128 = 128 Mbit (8 M x 16-bit) 64 = 64 Mbit (4 M x 16-bit) DEVICE FAMILY Am29BDS CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase Valid Combinations Burst Frequency (MHz) DensityOrder Number Package Marking Am29BDS128HE8 VKI BS128HE8V

128 Mbit

64 Mbit

each of these operations in further detail. Table 1. Device Bus Operations Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. addresses and stable CE# to valid data at the outputs. the falling edge of OE# to valid data at the output. operation and linear burst operation of a preset length.

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page 33 for further details. with Boundary Crossing,” on page 80. values by a multiple of 64) will not occur. Table 1, “Device Bus Operations,” on page 11. indicates the length of the latency by pulsing low. Table 2. Burst Address Groups back to the first address in the selected address group. inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. new synchronous access (latching of a new address). data and the current state are retained.

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 13 DATA SHEET Address 3Fh (or Offset from 3Fh by a Multiple of 64),” on page 62, Figure 25, “Standard Handshake Burst Suspend Prior to Initial Access,” on page 63, Figure 26, “Standard Handshake Burst Suspend at or after Initial Access,” on page 63, Figure 27, “Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier),” on page 64, Figure 28, “Standard Hand- shake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access),” on page 64, and Figure 29, “Stan- dard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK),” on page 65. Burst plus Burst Suspend should not last longer than t RCC without re-latching an address or crossing an address boundary. To resume the burst access, OE# must be re-asserted. The next active CLK edge will resume the burst sequence where it had been sus- pended. See Figure 30, “Read Cycle for Continuous Suspend,” on page 65. The RDY pin is only controlled by CE#. RDY will remain active and is not placed into a high-impedance state when OE# is de-asserted. Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Reduced Wait-state Handshaking Option The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to deter- mine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See “Autoselect Command Sequence” for details. For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Configuration Register Command Sequence” section on page 33 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 49, “Back-to-Back R ead/Write Cycle Timings,” on page 83 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asyn- chronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored in the Asynchronous programming mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Syn- chronous write operations. CLK and WE# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes pro- gramming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to V IL, and OE# to V IH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchro- nous write operation, the system must drive CE# and WE# to V IL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Configuration Register (see Table 18, “Configuration Register,” on page 36). The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 12, “Am29BDS128H Sector Address Table,” on page 27 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 4 Kword boot sectors in addition to 32 Kword sectors. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.

14 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

ICC2 in the “DC Characteristics” section on page 54 represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write oper- ations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this input, the device auto- matically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to V HH. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at V IL, ACC locks all sectors. ACC should be at VIH for all other conditions. Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output from the internal regis- ter (which is separate from the memory array) on DQ15–DQ0. This mode is primarily intended for pro- gramming equipment to automatically match a device to be programmed with its corresponding program- ming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID on address pin A9. Address pins must be as shown in Table 3, “Autoselect Codes (High Voltage Method),” on page 15. In addition, when verify- ing sector protection, the sector address must appear on the appropriate highest order address bits (see Table 4, “Am29BDS128H Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 16 ). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The com- mand sequence is illustrated in Table 20, “Memory Array Command Definitions,” on page 46. Note that if a Bank Address (BA) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 20, “Memory Array Command Definitions,” on page 46. This method does not require V ID. Autoselect mode may only be en- tered and used when in the asynchronous read mode. Refer to the “Autoselect Command Sequence” section on page 36 for more information.

Table 3. Autoselect Codes (High Voltage Method) SA = Sector Address, X = Don’t care.

1. The autoselect codes may also be accessed in-system via command sequences.
2. PPB Protection Status is shown on the data bus

16 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 4. Am29BDS128H Boot Sector/Sector Block

Table 5. Am29BDS640H Boot Sector/Sector Block the old 12 V controlled protection method. operations in the outermost sectors.

18 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Locking Bit. This will permanently set the part to op- erate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit . This will permanently set the part to operate only using pass- word sector protection. It is important to remember that setting either the Per- sistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See “Autoselect Command Se- quence” section on page 36 for details. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three dif- ferent sector protection states: ■ Persistently Locked —A sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command ■ Unlocked—The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of “bits” are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is as- signed to a maximum four sectors ( “Am29BDS128H Boot Sector/Sector Block Addresses for Protec- tion/Unprotection” section on page 16 ). All 4 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Program Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, un like programming where in- dividual PPBs are programmable. It is the responsibil- ity of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per de- vice. The PPB Lock is cleared after power-up or hard- ware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared. The DYBs and PPB Lock are defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protec- tion. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle.

changes to the PPBs during system operation. tection during system initialization. vice operates normally again. Table 6. Sector Protection Schemes PPB, and PPB lock relating to the status of the sector. whether or not the sector is protected or unprotected. DYB/PPB/PPB lock verify command to the device. place the device in password protection mode. ing a unique 64-bit Password to the device. identical to the Persistent Sector Protection method.

000 Unprotected—PPB and DYB are

001 Unprotected—PPB not

20 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

grammed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the pass- word. It is recommended that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each pass- word should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to re- verse this function. 2. It also disables all further commands to the pass- word region. All program, and read operations are ignored. Both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Lock- ing Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Pass- word Program and Verify commands (see “Password Program Command” section on page 40 and “Pass- word Verify Command” section on page 40 ). The password function works in conjunction with the Pass- word Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Lock- ing Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset the ONL Y means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Suc- cessful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1”. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit can be set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up re- set. The Password Unlock command is ignored in Per- sistent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be imple- mented using programming equipment. The procedure requires high voltage (V ID ) to be placed on the RESET# pin. Refer to Figure 2, “In-System Sector Pro- tection/ Sector Unprotection Algorithms,” on page 22 for details on this procedure. Note that for sector unpro- tect, all unprotected sectors must be first protected prior to the first sector write cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are set, the high voltage sector protect/unprotect capa- bility is disabled. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V CC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the opera- tion is completed. I CC3 in the “DC Characteristics” section on page 54 represents the standby current specification.

tion is required to provide new data. sequence, to ensure data integrity. RH after RESET# returns to VIH. ings,” on page 68 for the timing diagram. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP# = V IL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

22 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 2. In-System Sector Protection/

tory-locked and customer-locked status of the part. ing commands to the normal address space. Table 7. SecSi gion without raising any device pin to a high voltage. High Voltage Sector Protection section. erase operations in any sector or sector group. ■ When ACC is at VIL, all sectors are locked. tions, or from system noise.

24 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

ermost” 4 Kword boot sectors. WE# do not initiate a write cycle. automatically reset to the read mode on power-up. ward-compatible for the specified flash device families. for long-term compatibility. CFI data, the system must write the reset command. device to the autoselect mode. http://www.amd.com/flash/cfi. Table 8. CFI Query Identification String

Table 9. System Interface String Table 10. Device Geometry Definition

26 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 11. Primary Vendor-Specific Extended Query Bank A – Bank D Region Information. X = Number of sectors in bank.

Table 12. Am29BDS128H Sector Address Table

28 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 12. Am29BDS128H Sector Address Table (Continued)

30 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 13. Am29BDS640H Sector Address Table

32 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Program or Embedded Erase algorithm. Command” section on page 36 for more information. with Latched Addresses,” on page 67 show the timings. must be set before the device will enter burst mode. Figure 3. Synchronous/Asynchronous State asynchronous mode, “0” for synchronous mode. after AVD# is driven active before data will be available. related to the clock frequency.

34 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 14. Programmable Wait State Settings

1. Upon power-up or hardware reset, the default setting is
2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2. (wait states) for various conditions. Table 15. Wait States for Reduced Wait-state

1. If the latched address is 3Eh or 3Fh (or an address offset

cycles to the values listed.

1. In the 8-, 16-, and 32-word burst modes, the address

addresses offset from 3Fh by a multiple of 64).

1. Typical initial access cycles may vary depending on

110 R e s e r v e d

111 R e s e r v e d

flash device depending on the clock frequency. Table 16. Wait States for Standard Handshaking which are multiples of 3Fh). Sequence” section on page 36 for more information. device and then advances to the next 8 word boundary. Table 17. Read Mode Settings ting; “1” for rising active, “0” for falling active. OH whenever there is valid data on the outputs. chronous mode, RDY is an open-drain output.

36 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 18. Configuration Register Note:Device will be in the default state upon power-up or hardware reset. don’t cares for this command. until the operation is complete. before programming begins (prior to the third cycle). until the operation is complete. sequence cycles in an autoselect command sequence. and determine whether or not a sector is protected. page 46 shows the address and data requirements. ming or erasing in the other bank. mands to other banks will retu rn data from the array.

bank was previously in Erase Suspend). section on page 48 for information on these status bits. mode, to ensure data integrity. when the bank is in the unlock bypass mode. Table 19. Autoselect Data

38 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

ACC input to accelerate the operation. on page 72 for timing diagrams. Figure 4. Program Operation information on these status bits. data, to ensure data integrity. details on the unlock bypass command sequences. istics section for parameters and timing diagrams. timings during these operations. Note: See Table 20 for program command sequence.

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 39 DATA SHEET number of sectors may be from one sector to all sec- tors. The time between these additional cycles must be less than t SEA , otherwise erasure may begin. Any sector erase address and command following the exceeded time-out, t SEA, may or may not be accepted. It is recommended that processor interrupts be dis- abled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 51.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” section on page 48 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. The Unlock Bypass Reset Command is required to return to reading array data when the bank is in the unlock bypass mode. Figure 5, “Erase Operation,” on page 40 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the Figure , “AC Characteristics,” on page 69 for parameters and timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum t SEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of t ESL to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Figure , “Write Operation Status,” on page 48 for information on these status bits. After an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the “Write Operation Status” section on page 48 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Autoselect Mode” section on page 14 and “Autoselect Command Sequence” section on page 36 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command

40 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

written after the chip has resumed erasing. Figure 5. Erase Operation ways drive all Fs onto the DQ data bus. ation when the Password Verify command is executed. word Mode Locking Bit from ever being programmed.

1. See Table 20 for erase command sequence.
2. See the section on DQ3 for information on the sector

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 41 DATA SHEET tection Mode Locking Bit is programmed. If not, the system must repeat this program sequence from the fourth cycle of “PL/68h”. Exiting the Persistent Protec- tion Mode Locking Bit Program command is accom- plished by writing the SecSi Sector Exit command or Reset command. SecSi Sector Protection Bit Program Command To protect the SecSi Sector, write the SecSi Sector Protect command sequence while in the SecSi Sector mode. After issuing “OPBP/48h” at the fourth bus cy- cle, the device requires a time out period of approxi- mately 150 µs to protect the SecSi Sector. Then, by writing “OPBP/48” at the fifth bus cycle, the device out- puts verify data at DQ0. If DQ0 = 1, then the SecSi Sector is protected. If not, then the system must re- peat this program sequence from the fourth cycle of “OPBP/48h”. PPB Lock Bit Set Command The PPB Lock Bit Set comman d is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully exe- cuted. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the Password Unlock command is executed. Upon set- ting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the SecSi Sector Exit command, only while in the Persistent Sector Pro- tection Mode. DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (Amax–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the de- vice to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 4 times. A1 and A0 are used for matching. Writing the Password Unlock com- mand is not address order specific. The lower address A1–A0= 00, the next Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to A1–A0= 11. Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicating that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password Un- lock command is issued again, only this time with the next part of the password. Four Password Unlock com- mands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RDY signal goes LOW and reading the device re- sults in the DQ6 pin toggling on successive read oper- ations until complete. It is the responsibility of the microprocessor to keep track of the number of Pass- word Unlock commands, the order, and when to read the PPB Lock bit to confirm successful password un- lock. In order to relock the device into the Password Mode, the PPB Lock Bit Set command can be re-is- sued. Exiting the Password Unlock Command is ac- complished by writing SecSi Sector Exit command.

42 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 6. PPB Program Algorithm

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 43 DATA SHEET PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro- grammed (but is bulk er ased with the other PPBs). The specific sector address (Amax–A12) are written at the same time as the program command 60h. If the PPB Lock Bit is set and the correspondingly PPB is set for the sector, the PPB Program command will not execute and the command will time out without pro- gramming the PPB. After issuing “SBA+WP/68h” at the fourth bus cycle, the device requires a time out pe- riod of approximately 150 µs to program the PPB. Writing “SBA+WP/48” at the fifth bus cycle produces verify data at DQ0. If DQ0 = 1, the PPB is pro- grammed. If not, the system must repeat this program sequence from the fourth cycle of “SBA+WP/68h”. The PPB Program command does not follow the Embedded Program algorithm. Writing the SecSi Sector Exit command or Read/Reset command return the device back to normal operation. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- ing a specific PPB. Unlike the PPB program, no spe- cific sector address is required. However, when the PPB erase command is writt en (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set, the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After issuing “WP/60h” at the fourth bus cycle, the device re- quires a time out period of approximately 1.5 ms to erase the PPB. Writing “SBA+WP/40h” at the fifth bus cycle produces verify data at DQ0. If DQ0 = 0, the PPB is erased. If not, the system must repeat this pro- gram sequence from the fourth cycle of “WP/60h”. It is the responsibility of the system to preprogram all PPBs prior to issuing the All PPB Erase command. If the system attempts to erase a cleared PPB, over-era- sure may occur, making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the SecSi Sector Exit command or Read/Re- set command return the device to normal operation.

44 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 7. PPB Erase Algorithm

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 45 DATA SHEET DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sec- tor is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. Writing Read/Reset command returns the device to normal operations. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. Writing Read/Reset command and SecSi Sec- tor Exit command return the device to normal opera- tion. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sec- tor can be verified by writing a PPB Lock Bit status ver- ify command to the device. Read/Reset and SecSi Sector Exit return the device to normal operation. DYB Status Command The programming of the DYB for a given sector can be verified by writing a DYB Status command to the de- vice. Writing SecSi Sector Exit command returns the device to normal operation.

46 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Table 20. Memory Array Command Definitions

• For actual hexadecimal data values, refer to the note number indicated.

RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector. which command is being written. either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except
5. Unless otherwise noted, address bits Amax–A12 are don’t cares.
6. Writing incorrect address and data values or writing them in the
7. No unlock or command cycles required when bank is reading array
8. The Reset command is required to return to reading array data (or to
9. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The data is 0000h for an unlocked sector and 0001h for a locked
2. DQ15–DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not
3. The Unlock Bypass command sequence is required prior to this
4. The Unlock Bypass Reset command is required to return to reading

array data when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or enter

and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. See “Set Configuration Register Command Sequence” for details.

This command is unavailable in Unlock Bypass mode.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

1. The Unlock Bypass Reset command is required to exit this mode

Entry and exit (Reset), Program, Erase, Sector Erase and CFI.

Table 21. Sector Protection Command Definitions SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector. which command is being written. either A6 = 1 for unlocked or A6 = 0 for locked. that represent the 64-bit password. each 16-bit portion of the 64-bit entity. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1. SBA = Sector address block to be protected.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except

for RD, PD, WD, PWD, and PD3–PD0.

1. Unless otherwise noted, address bits Amax–A12 are don’t cares.
2. Writing incorrect address and data values or writing them in the
3. No unlock or command cycles required when bank is reading array
4. Not supported in Synchronous Read Mode, command mode verify

are always asynchronous read operations.

1. The fourth cycle programs the addressed locking bit. The fifth and

command must be issued and verified again.

1. The fourth cycle erases all PPBs. The fifth and sixth cycles are used
2. The entire four bus-cycle sequence must be entered for each portion
3. Before issuing the erase command, all PPBs should be programmed

in order to prevent over-erasure of PPBs.

1. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not

48 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

erase operation is complete or in progress. edge of the final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 8. Data# Polling Algorithm

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 49 DATA SHEET RDY: Ready The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which indicates whether an Embedded Algorithm is in progress or com- pleted. The RDY status is valid after the rising edge of the final WE# pulse in the command sequence. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is in high imped- ance (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 23, “Write Operation Status,” on page 52 shows the outputs for RDY . DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately t ASP, all sectors protected toggle time, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately t PSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 9, “Toggle Bit Algorithm,” on page 50, “DQ6: Toggle Bit I” on page 49 , Figure 41, “Toggle Bit Timings (During Embedded Algorithm),” on page 76 (toggle bit timing diagram), and Table 22, “DQ6 and DQ2 Indica- tions,” on page 51. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state.

50 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 9. Toggle Bit Algorithm page 51 to compare outputs for DQ2 and DQ6. Table 22, “DQ6 and DQ2 Indications,” on page 51.

Table 22. DQ6 and DQ2 Indications DQ7–DQ0 on the following read cycle. Bit Algorithm,” on page 50). the erase-suspend-program mode). applies after each additional sector erase command. SEA, the system need not monitor DQ3. programming, at any address, toggles, does not toggle. selected for erasure, toggles, also toggles. selected for erasure, toggles, does not toggle. selected for erasure, does not toggle, toggles. from any sector not selected for erasure. erase suspend at any address, toggles, is not applicable.

52 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

device will accept additi onal sector erase commands. last command might not have been accepted. Table 23. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

1. The system may read either asynchronously or synchronously (burst) while in erase suspend.
2. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This

is available in the Asynchronous mode only.

54 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Note: 1. Maximum I CC specifications are tested with VCC = VCCmax. 2. V IO= VCC 3. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 6. Total current during accelerated programming is the sum of V ACC and VCC currents. Parameter Description Test Conditions Note: 1 & 2 Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCCmax ±1 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCCmax ±1 µA ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8

54 MHz 9 17 mA

CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 54 MHz 8 15.5 mA CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous

54 MHz 7 14 mA

IIO1 VIO Non-active Output OE# = V IH 14 0 µ A ICC1 VCC Active Asynchronous Read Current (Note 3) CE# = VIL, OE# = VIH, WE# = VIH

10 MHz 20 30 mA

5 MHz 10 15 mA

1 M H z 3 . 55m A ICC2 VCC Active Write Current (Note 4) CE# = V IL, OE# = VIH, ACC = VIH 15 40 mA ICC3 VCC Standby Current (Note 5) CE# = RESET# = V CC ± 0.2 V 0.2 40 µA ICC4 VCC Reset Current RESET# = V IL, CLK = VIL 14 0 µ A ICC5 VCC Active Current (Read While Write) CE# = VIL, OE# = VIH 25 60 mA ICC6 VCC Sleep Current CE# = V IL, OE# = VIH 14 0 µ A IACC Accelerated Program Current (Note 6) CE# = VIL, OE# = VIH, VACC = 12.0 ± 0.5 V VACC 71 5 m A VCC 51 0 m A VIL Input Low Voltage V IO = 1.8 V –0.4 0.4 V VIH Input High Voltage V IO = 1.8 V V IO – 0.4 V IO + 0.4 V VOL Output Low Voltage I OL = 100 µA, VIO = VCC = VCC min 0.1 V VOH Output High Voltage I OH = –100 µA, VIO = VCC = VCC min VIO – 0.1 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 1.8 V 11.5 12.5 V VHH Voltage for Accelerated Program 11.5 12.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V

56 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 14. V CC Power-up Diagram

1. V CC ≥ VIO–100 mV and VCC ramp rate exceeds 1 V/100 µs.
2. If the V CC ramp rate is less than 1 V /100 µs, a hardware reset will be required.

Figure 15. CLK Characterization

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 57 DATA SHEET AC CHARACTERISTICS Synchronous/Burst Read Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. Parameter Description 66 MHz 54 MHz UnitJEDEC Standard tIACC Latency (Even address in Reduced wait-state Handshaking mode) Max 56 69 ns tIACC Latency (Standard Handshaking or Odd address in Reduced wait-state Handshaking mode Max 71 87.5 ns tBACC Burst Access Time Valid Clock to Output Delay Max 11 13.5 ns tACS Address Setup Time to CLK (Note ) Min 4 5 ns tACH Address Hold Time from CLK (Note ) Min 6 7 ns tBDH Data Hold Time from Next Clock Cycle Min 3 4 ns tCR Chip Enable to RDY Valid Max 11 13.5 ns tOE Output Enable to Output Valid Max 11 13.5 ns tCEZ Chip Enable to High Z Max 8 10 ns tOEZ Output Enable to High Z Max 8 10 ns tCES CE# Setup Time to CLK Min 4 5 ns tRDYS RDY Setup Time to CLK Min 4 5 ns tRACC Ready Access Time from CLK Max 11 13.5 ns tAAS Address Setup Time to AVD# (Note ) Min 4 5 ns tAAH Address Hold Time to AVD# (Note ) Min 6 7 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 4 5 ns tAVD AVD# Pulse Min 10 12 ns tACC Access Time Max 50 55 ns tCKA CLK to access resume Max 11 13.5 ns tCKZ CLK to High Z Max 8 10 ns tOES Output Enable Setup Time Min 4 5 ns tRCC Read cycle for continuous suspend Max 1 ms

58 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY .
3. The device is in synchronous mode.

Figure 16. CLK Synchronous Burst Mode Read (rising active CLK)

1. Figure shows total number of wait states set to four cycles . The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active falling edge.

1. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY .
2. The device is in synchronous mode.

7 cycles for initial access shown. 4 cycles for initial access shown.

60 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

has been written with A18=0; device will output RDY one cycle before valid data. Figure 20. Linear Burst with RDY Set One Cycle Before Data 6 wait cycles for initial access shown.

62 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 23. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Eh (or Offset from 3Eh) Figure 24. Reduced Wait-state Handshake Burst Suspend/Resume at Address 3Fh (or Offset from 3Fh by

64 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

has been written with A18=0; device will output RDY with valid data. Figure 27. Standard Handshake Burst Suspend at Address 3Fh (Starting Address 3Dh or Earlier) has been written with A18=0; device will output RDY with valid data. 1) Address is 3Eh or offset by a multiple of 64 (40h). 2) Address is 3Fh or offset by a multiple of 64 (40h). Figure 28. Standard Handshake Burst Suspend at Address 3Eh/3Fh (Without a Valid Initial Access)

66 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Notes: 1. Asynchronous Access Time is from the last of ei ther stable addresses or the falling edge of AVD#. 2. Not 100% tested. Parameter Description 75 MHz 66 MHz 54 MHz UnitJEDEC Standard tCE Access Time from CE# Low Max 45 50 55 ns tACC Asynchronous Access Time (Note 1) Max 45 50 55 ns tAVDP AVD# Low Time Min 10 12 ns tAAVDS Address Setup Time to Rising Edge of AVD Min 4 5 ns tAAVDH Address Hold Time from Rising Edge of AVD Min 5.5 6 7 ns tOE Output Enable to Output Valid Max 8.5 11 13.5 ns tOEH Output Enable Hold Time Read Min 0 ns Toggle and Data# Polling Min 8 10 ns tOEZ Output Enable to High Z (Note 2) Max 8 10 ns tCAS CE# Setup Time to AVD# Min 0 ns

68 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Hardware Reset (RESET#) Note: Not 100% tested. Parameter

Description

RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 μs RESET# tRP tReady Reset Timings NOT during Embedded Algorithms tReadyw CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP Figure 33. Reset Timings

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 69 DATA SHEET AC CHARACTERISTICS Erase/Program Operations Notes: 1. Not 100% tested. 2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of CLK. 4. See the “Erase and Programming Performance” section for more information. 5. Does not include the preprogramming time. Parameter Description 75 MHz 66 MHz 54 MHz UnitJEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 45 50 55 ns tAVWL tAS Address Setup Time (Notes 2, Synchronous Min ns Asynchronous 0 tWLAX tAH Address Hold Time (Notes 2, Synchronous Min 5.5 6 7 ns Asynchronous 15 20 20 tAVDP AVD# Low Time Min 10 12 ns tDVWH tDS Data Setup Time Min 20 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 20 30 ns tWHWL tWPH Write Pulse Width High Min 15 20 20 ns tSR/W Latency Between Read and Write Operations Min 0 ns tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tELWL tCS CE# Setup Time to WE# Min 0 ns tAVSW AVD# Setup Time to WE# Min 4 5 ns tAVHW AVD# Hold Time to WE# Min 4 5 ns tACS Address Setup Time to CLK (Notes 2, 3) Min 4 5 ns tACH Address Hold Time to CLK (Notes 2, 3) Min 5.5 6 7 ns tAVHC AVD# Hold Time to CLK Min 4 5 ns tCSW Clock Setup Time to WE# Min 5 ns tSEA Sector Erase Accept Timeout Max 50 µs tESL Erase Suspend Latency Max 35 µs tASP Toggle Time During Sector Protection Typ 100 µs tPSP Toggle Time During Programming within a Protected Sector Typ 1 µs

70 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 35. Asynchronous Program Operation Timings: WE# Latched Addresses

72 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the firs t of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from lo w to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode. Figure 36. Synchronous Program Operation Timings: WE# Latched Addresses

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the firs t of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from lo w to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode. Figure 37. Synchronous Program Operation Timings: CLK Latched Addresses

74 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 38. Chip/Sector Erase Command Sequence

1. SA is the sector address for Sector Erase.
2. Address bits Amax–A12 are don’t cares during unlock cycles in the command sequence.

Note: Use setup and hold times from conventional program operation. Figure 39. Accelerated Programming Timing

76 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

and Data# Polling will output true data.

1. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 40. Data# Polling Timings (During Embedded Algorithm)

1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

the toggle bits will stop toggling.

1. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 41. Toggle Bit Timings (During Embedded Algorithm)

78 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Figure 44. Temporary Sector Unprotect Timing Diagram

80 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing

a bank in the process of performing an erase or program.

1. If the starting ad dress latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at

Figure 46. Latency with Boundary Crossing 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a

bank in the process of performing an erase or program. 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

82 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 48. Example of Wait States Insertion

the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 49. Back-to-Back Read/Write Cycle Timings

84 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20, “Memory Array Command Definitions,” on page 46 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1 million cycles. BGA BALL CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 32 Kword 0.4 5 s Excludes 00h programming prior to erasure (Note 4) 4 Kword 0.2 5 Chip Erase Time

128 Mb 103 s

64 Mb 54 s

Word Programming Time 9 210 µs Excludes system level overhead (Note 5)Accelerated Word Programming Time 4 120 µs Chip Programming Time (Note 3) 128 Mb 75.5 226.5 s

64 Mb 38 114 s

Excludes system level overhead (Note 5)Accelerated Chip Programming Time

128 Mb 33 99 s

64 Mb 17 30 s

Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 85 DATA SHEET PHYSICAL DIMENSIONS VBB080—80-ball Fine-Pitch Ball Grid Array (BGA) 11.5 x 9 mm Package Note: BSC is an ANSI standard for Basic Space Centering 3233 \\ 16-038.9h NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. PACKAGE VBB 080 JEDEC N/A 11.50 mm x 9.00 mm NOM PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.00 OVERALL THICKNESS A1 0.20 --- --- BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 11.50 BSC. BODY SIZE E 9.00 BSC. BODY SIZE D1 8.80 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 12 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 80 TOTAL BALL COUNT φb 0.30 0.35 0.40 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT (A3-A6, B3-B6, L3-L6, -M3-M6) DEPOPULATED SOLDER BALLS BOTTOM VIEWTOP VIEW SIDE VIEW A1 CORNER A2A INDEX MARK CORNER 10 PIN A1 ML J K e C0.05 (2X) (2X) C0.05 E D BACEDFHG e SE BCA C Mφ 0.15 φ 0.08 M 0.10 C C0.08 NXφb SD A B C SEATING PLANE

86 Am29BDS128H/Am29BDS640H 27024B3 May 10, 2006

VBD064—64-ball Fine-Pitch Ball Grid Array (BGA) 9 x 8 mm Package Note: BSC is an ANSI standard for Basic Space Centering 3246 \\ 16-038.9 PACKAGE VBD 064 JEDEC N/A 8.95 mm x 7.95 mm NOM PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.00 OVERALL THICKNESS A1 0.20 --- 0.30 BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 8.95 BSC. BODY SIZE E 7.95 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 64 TOTAL BALL COUNT φb 0.30 0.35 0.40 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT NONE DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIAMETER IN A PLANE PARALLEL TO DATUM C. A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. SIDE VIEW A2A SEATING PLANE C CC 0.10 0.08A1 TOP VIEW C (2X) 0.05 (2X) C0.05 A B INDEX MARK CORNER PIN A1 E D BOTTOM VIEW A1 CORNER SD SE e AB NXφb Mφ 0.15 φ 0.08 M C C GH B A D CEF

May 10, 2006 27024B3 Am29BDS128H/Am29BDS640H 87 DATA SHEET REVISION SUMMARY Revision A (November 5, 2002) Initial release. Revision B (February 2, 2004) Global Incorporated Am29BDS640H specifications from pub- lication 27241. Removed 1.5 V V IO option. Changed 80 MHz speed grade to 75 MHz. In-System Sector Protection/Sector Unprotection Algorithms Changed “Wait 15 ms” to “Wait 1.5 ms.” Password Protection Mode Locking Bit; Persistent Sector Protection Mode Locking Bit Program Command; SecSi Sector Protection Bit Program Command; PPB Program Command; All PPB Erase Command Updated description for these sections. Command Definitions Changed WP to (01000010). Set Configuration Reg- ister command is not available in Unlock Bypass Mode Removed Password Protection Locking Bit Read command and Persistent Protection Locking Bit Read command. Updated PPB Program, Erase, Status com- mands to require Sector Block Address (SBA). DC Characteristics Updated I IO1, ICC1, ICC3, ICC4, ICC6 Test Conditions Updated Input Rise and Fall Times. VCC Power Up Added Ramp Rate information. CLK Characterization Added section. Revision B+1 (August 10, 2004) Global Incorporated Am29BDS640H specifications from pub- lication 27241. Updated speed options offered. Revision B2 (September 30, 2005) Added package type VF (Pb-free Package (VBB080)) Revision B3 (May 10, 2006) Added migration and obsolescence information for Am29BDS640H. Removed Preliminary designation from document. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2002–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.