B9948L

B9948L CYPRESS | Alldatasheet

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Technical content

2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer B9948L Cypress Semiconductor Corporation • 3901 North First Street  San Jose  CA 95134  408-943-2600 Document #: 38-07080 Rev. *C Revised December 21, 2002 Product Features

• 160-MHz clock support  2.5V or 3.3V output capability  200-ps maximum output-to-output skew  LVPECL or LVCMOS/LVTTL clock input  LVCMOS/LVTTL compatible inputs  12 clock outputs: drive up to 24 clock lines  Synchronous Output Enable  Output Three-state control  Pin compatible with MPC948L  Industrial temp. range: –40°C to +85°C  32-pin TQFP package

Description

The B9948L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/ LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The twelve outputs are 2.5V or 3.3V LVCMOS or LVTTL com- patible and can drive two series-terminated 50Ω transmission lines. With this capability the B9948L has an effective fanout of 1:24. The outputs can also be three-stated via the three- state input TS#. Low output-to-output skews make the B9948L an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9948L also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration PECL_CLK PECL_CLK# 0 1TCLK TCLK_SEL SYNC_OE TS# VDD VDDC

12 Q0-Q11

TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS

1. PD = Internal Pull-Down, PU = Internal Pull-Up.

puts are enabled as shown in Figure 1. 3 PECL_CLK I, PU PECL Input Clock. 4 PECL_CLK# I, PD PECL Input Clock. 2 TCLK I, PU External Reference/Test Clock Input. Q(11:0) VDDC O Clock Outputs. VDDC 2.5V or 3.3V Power Supply for Output Clock Buffers. Figure 1. SYNC_OE Timing Diagram

Document #: 38-07080 Rev. *C Page 3 of 6 Maximum Ratings [2] This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any volt- age higher than the maximum rated voltages to this circuit. For proper operation, V in and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic volt- age level (either VSS or VDD ). Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up resistors that effect input current, PECL_CLK# has a pull-down resistor. 4. The V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50Ω (or 50Ω to VDD /2) transmission lines. DC Parameters: VDDC = 2.5V±5% or 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage PECL_CLK, Single ended 1.49 1.825 V All other inputs V SS 0.8 VIH Input High Voltage PECL_CLK, Single ended 2.135 2.42 V All other inputs 2.0 V DD IIL Input Low Current (@VIL = VSS )N o t e 3 –100 µA IIH Input High Current (@VIL =VDD ) 100 µA VPP Peak-to-Peak Input Voltage PECL_CLK Note 4 300 1000 mV VCMR Common Mode Range PECL_CLK V DD – 2.0 V DD – 0.6 V VOL Output Low Voltage I OL = 20 mA[5] 0.4 V VOH Output High Voltage I OH = –20 mA, VDDC = 3.3V[5] 2.5 V IOH = –20 mA, VDDC = 2.5V[5] 2.0 IDD Quiescent Supply Current All V DDC and VDD 12 m A C in Input Capacitance 4p F

Document #: 38-07080 Rev. *C Page 4 of 6 Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. Outputs loaded with 30 pF each 10. Part-to-Part Skew at a given temperature and voltage. 11. Set-up and Hold times are relative to the falling edge of the input clock Note: 12. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. AC Parameters[6]: VDDC = 2.5V±5% or 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit Fmax Maximum Input Frequency [7] 160 MHz Tpd PECL_CLK to Q Delay [7] 4.0 - 9.0 ns TCLK to Q Delay[7] 4.4 - 8.9 FoutDC Output Duty Cycle [7,8] Measured at VDDC/2 TCYCLE/2 – 1000 TCYCLE/2 + 1000 ps tpZL, tpZH Output enable time (all outputs) 2 10 ns tpLZ, tpHZ Output disable time (all outputs) 2 10 ns Tskew Output-to-Output Skew [7,9] 200 ps Tskew (pp) Part to Part Skew[10] PECL_CLK to Q 1.5 ns TCLK to Q 2.0 Ts Set-up Time [7,11] SYNC_OE to PECL_CLK 1.0 ns SYNC_OE to TCLK 0.0 Th Hold Time [7,11] PECL_CLK to SYNC_OE 0.0 ns TCLK to SYNC_OE 1.0 Tr/Tf Output Clocks Rise/Fall Time [9] 10% to 90% 0.3 1.6 ns

Ordering Information

Part Number[12] Package Type Production Flow B9948LAA 32-Pin TQFP Industrial, –40°C to +85°C Marking: Example: Cypress B9948LAA Date Code, Lot # B9948LAA Package A = TQFP Revision Device Number

Document #: 38-07080 Rev. *C Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Drawing and Dimensions D D 1 be 12° L 32-Pin TQFP Outline Dimensions Inches Ml A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 - 0.041 0.95 - 1.05 D- 0 . 3 5 4 - - 9 . 0 0 - b 0.012 - 0.018 0.30 - 0.45 e 0.031 BSC 0.80 BSC L 0.018 - 0.030 0.45 - 0.75

Document #: 38-07080 Rev. *C Page 6 of 6 Document Title: B9948L 2.5V/3.3V, 160 MHz, 1:12 Clock Distribution Buffer Document Number: 38-07080 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 107116 06/06/01 IKA Convert from IMI to Cypress *A 108061 07/03/01 NDP Changed Commercial to Industrial (See page 6) *B 109806 02/01/02 DSG Convert from Word to Frame *C 122765 12/21/02 RBI Add power up requirements to maximum ratings information.