AV3232E

AVXX32E-B APLUS | Alldatasheet

Document overview

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Technical content

APLUS MAKE YOUR PRODUCTION A-PLUS AVXX32E-B SERIES DATA SHEET APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115)台北市南港區成功路㆒段32 號 3 樓之 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw Sales E-mail: sales@aplusinc.com.tw Technology E-mail: service@aplusinc.com.tw

21, 32, 43, 65 and 87 Seconds Complicate Pure Speech

Features

y Operating voltage: 2.4V~5.0V y One single-key can implement play-all, play-next and random function. Maximum play count is 32. y 4-column inputs and 3-row outputs can implement 4x4-matrix function. y Each input can implement looping function. y Single-key and 4-column inputs can be last-key priority for stand-alone input or first-key priority. y Each input trigger can select trigger mode: (For OKY, TG0, TG1, TG2, TG3) Edge/Level, Hold/Unhold, Retrigger/Irretrigger. y Each input trigger can select its own debounce time: Fast debounce: < 200us; Slow debounce: ~16ms (S.R.=6.0kHz) y Support bouncing trigger solution for retrigger application. (Second trigger force to retrigger and slow debounce.) y Maximum table entries are 460*8. y Word count is only limited by ROM capacity. y 4 output ports for Status or Led application: Ϋʳ OP_A Status: Busy_high ,DC_low, Stop_high,DC_high LED: +Fast,+Slow, Dyn(7/10), Off Ϋʳ OP_B Status: Busy_high, DC_low, Stop_high, DC_high LED: -Fast, -Slow, Dyn(9/10), On Ϋʳ OP_C Status: Busy_high, DC_low, Busy_low, DC_high LED: +Fast, +Slow, On, Off Ϋʳ OP_D Status0: Busy_high, DC_low Status1: Busy_low, DC_high y Each output can specify its initial state (High or Low) y Outputs can be set as constant current regardless of the supply voltage varied. y Two PWM playing ports. Drive speaker or buzzer directly (For tone only). y One DAC playing port, together with external bipolar to drive speaker. Ramp up/down is automatic. y For DAC, AVXX32E-B series supports 8 levels of current control to offer flexible choises of corresponding BJT. y Four-level volume control is provided for DAC or PWM output. y Eight-pitch control is provided. y Voice length: 21, 32, 43, 65 and 87 seconds. (ROM capacity : 131072*5, 196608*5, 262144*5, 393216*5 and 524288*5 bits) y Voice algorithm: 5-bits LOG_PCM y External resister or built-in resister for system frequency by bonding option on the same pad. y Sixteen default sampling frequencies are supported. The default frequencies can be changed by an external applying resistor. y Support single key play on/off. (For OKY, TG0, TG1) y Programmable pull-high, pull-low or floating input. (For OKY, TG0, TG1) General Description The AVXX32E-B is a series of single-chip synthesizing CMOS VLSI which synthesizes voice by LOG_PCM algorithm. Table programming and shared multiple I/O pins make the applications flexible. Powerful functions and pure speech architecture make the AVXX32E-B series able to best fit most speech applications and a best cost/performance ratio as a result. The programming of the AVXX32E-B series is first to define words. Each word contains voice data (or mute length), output method, pitch (if pitch control enabled), and volume (if volume control enabled). Assemble the words into sentences first, and then the programmer can assign the sentences to the keys corresponding to the user inputs. The I/O pins of the AVXX32E-B series are multiplexed. This means the users have flexible I/O options for their applications in a minimum number of pin counts, that is, lower cost. The users can use maximum 4*4 matrix plus one single-key inputs, but less outputs; or 4 maximum outputs, but less inputs. The AVXX32E-B series support DAC or PWM audio output, the users can select both if necessary. The frequency stability in the AVXX32E-B series is outstanding. The frequency variation by voltage change is relatively small compared to the competitor. Furthermore, volume option offers users flexible selection for their applications. In addition, the AVXX32E-B series support current control for DAC output. Thus users can choose suitable current output for their BJT component. The programming and the approval can be done in the EV chip of the AVXX32E-B series. It makes the programming and verification easy. Please contact APLUS sales for the EV chip if required. 10-1 Ver.1.0

Pin Name I/O Pad Assign Description VDD Power Positive power supply TEST In Test enable pad, high-active, pull-low OSC In With resister connected to VDD for system clock generating or connected to VSS using internal resister In OKY Trigger input, active-high OKY_RW3 Out ROW3 Row output for matrix function. TG0,TG1 In Column input or stand-alone input; active-high In TG2 Column input or stand-alone input; active-high TG2_OPD Out OP_D Status output In TG3 Column input or stand-alone input; active-high TG3_OPC Out OP_C Status output Out ROW1 Row output for matrix function RW1_OPB Out OP_B Status output Out ROW2 Row output for matrix function RW2_OPA Out OP_A Status output Out PWM1 Voltage output to drive speaker or buzzer PWM1 Out OP_A OP_C Status output Out PWM2 Voltage output to drive speaker or buzzer PWM2 Out OP_B OP_D Status output Out DAC Current output for speaker application DAC Out OP_A OP_B OP_C OP_D Status output VSS Power Negative power supply Absolute Maximum Rating Symbol Rating Unit VDD~VSS -0.5 ~ +0.5 V VIN (for input) V SS-0.3 < VIN < VDD+0.3 V VOUT (for all outputs) V SS < VOUT < VDD V T (operating) -10 ~ +60 к T (storage) -55 ~ +125 к 1 0 - 2 V e r .1 . 0

Symbol Parameter Min Typ. Max Unit Condition VDD Operating Voltage 2.4 3.0 5.0 V Isb Standby ΫΫ 1 ӴA VDD=3.0V, I/O open Iop Supply Current Operating ΫΫ 400 ӴA VDD=3.0V, No loading Iih ΫΫ -20 ӴA VDD=3.0V, VIP=0V Iil Input Current ΫΫ 20 ӴA VDD=3.0V, VIP=3.0V Iol Ϋ 10 Ϋ mA V DD=3.0V, VOP=0.8V Ioh Output Current Ϋ -5 Ϋ mA V DD=3.0V, VOP=2.5V d F/F Frequency Stability ΫΫ r5 % (fOSC (4.5V)-fOSC(4.0))/ fOSC (4.5V) d F/F Frequency Variation by difference lot ΫΫ r10 % VDD=4.5V fOSC =384kHz Function Diagram Edge/Level mode (If sentence = word1+word2) y Edge mode Trigger length > Voice length $XGLR ZRUG ZRUG GHERXQFHWLPH Trigger length < Voice length ZRUG ZRUG GHERXQFHWLPH y Level mode Trigger length > Voice length (if sentence=word1+word2) $XGLR ZRUG ZRUG GHERXQFHWLPH ZRUG ZRUG 1 0 - 3 V e r .1 . 0

Trigger length < Voice length (if sentence = word1+word2) $XGLR ZRUG ZRUG GHERXQFHWLPH Hold/Unhold mode (If sentence = word1+word2) y Hold mode $XGLR ZRUG GHERXQFHWLPH ZRUG y Unhold mode $XGLR ZRUG ZRUG GHERXQFHWLPH Retrigger/Irretrigger mode (If sentence = word1+word2) y Retrigger mode (Edge Unhold mode) $XGLR ZRUG GHERXQFHWLPH ZRUGZRUG ZRUG y Irretrigger mode (Edge, Unhold mode) $XGLR ZRUG GHERXQFHWLPH ZRUG 10-4 Ver. 1.0

y If TG1, TG2 are retrigger mode $XGLR 7* V 7* V 7* V 7* V Looping function If sentence is set to looping mode (sentence1_sentence2) y Unhold mode VHQWHQFH VHQWHQFH $XGLR VHQWHQFH VHQWHQFH y Hold mode VHQWHQFH VHQWHQFH $XGLR VHQWHQFH Force to retrigger and slow debounce option (Trigger mode set to Fast debounce and Irretrigger mode) VW7* )56% : : : : : : : : 7KLVZRUGPXVWEHODUJHUWKDQJOLWFKSHULRG $PXWHZRUGFDQEHXVHGEHUKDSV 6ORZGHERXQFH 5HWULJJHUPRGH 6ORZGHERXQFH 5HWULJJHUPRGH )DVWGHERXQFH ,UUHWULJJHUPRGH )DVWGHERXQFH ,UUHWULJJHUPRGH $XGLR QG7* )56% $XGLR 'RQ WFDUH Busy=0, FRSB set to high; Busy=1, depending on FRSB setting. If FRSB=0, force to slow debounce and retrigger mode; If FRSB=1, no change (fast debounce and irretrigger mode). 1 0 - 5 V e r .1 . 0

Stand-alone trigger inputs are enabled at the same time COL3 Audio This voice is enabled by COL3 OKY COL0 COL1 COL2 Trigger input priority is COL3 > COL2 > COL1 > COL0 > OKY Application circuit y External resister, Driver speaker by PWM, driver LED VDD OSC OKY OP_A PWM1 PWM2 Rosc VSS ROSC=200k: for frequency option 8 y Internal resister, driver speaker by PWM, driver LED If OSC bonds to VSS, this chip uses internal resister automatically. VDD OSC OKY VSS OP_A PWM1 PWM2 1 0 - 6 V e r .1 . 0

Set the pull resisters of OKY, TG0 or TG1 to pull-high will cause the triggers to play immediately after power on. VDD OSC OP_A PWM1 PWM2 VSS y Matrix input 9''26& 2.< 23B& 3:0 3:0 966 23B% 23B$ &2/ &2/ &2/ &2/ 52: 52: 52: 526& 7*7*7* 7*7*7* y Driver speaker by DAC and driver Motor application 10-7 Ver.1.0 VDD OSC OKY OP_C DAC Cx VSS OP_B OP_A ROSC + - Motor Rx

y Stand-alone trigger input VDDOSC OKY OP_C PWM1 PWM2 VSS OP_B OP_A COL0 COL1 COL2 COL3 ROSC Output Definition Option 0 1 2 3 Status BH DL SH DH Standby state L L L H LED +Fast +Slow Dy07 OFF OPA Standby state HHHH Status BH DL SH DH Standby state L L L H LED -Fast -Slow Dy09 ON OPB Standby state H H H H Status BH DL BL DH Standby state L L H H LED +Fast +Slow ON OFF OPC Standby state H H H H Status1 BH DL Standby state L L Satatus2 BH DL OPD Standby state H H 1 0 - 8 V e r .1 . 0

Y X VSS PWM2 PWM1 VDD DAC OSC OKY_RW3 RW2_OPA RW1_OPB TG3_OPC TG2_OPD TEST TG1 TG0 Note: The IC substrate should be connect to VSS (1) AV2132E PIN Name X(mm) Y(mm) OKY_RW3 250.75 94.00 RW2_OPA 451.50 94.25 RW1_OPB 660.25 94.25 TG3_OPC 861.00 94.25 TG2_OPD 1069.75 94.25 TEST 1270.25 94.25 OSC 94.00 271.25 TG1 1313.25 297.00 DAC 94.00 472.25 TG0 1313.25 501.00 VSS 410.75 1419.50 PWM2 631.00 1440.00 PWM1 1049.50 1440.00 VDD 1331.00 1440.00 DIE SIZE = 1510 * 1655 Pm^2 (X*Y) (2) AV3232E PIN Name X(mm) Y(mm) OKY_RW3 250.75 94.00 RW2_OPA 451.50 94.25 RW1_OPB 660.25 94.25 TG3_OPC 861.00 94.25 TG2_OPD 1069.75 94.25 TEST 1270.25 94.25 OSC 94.00 271.25 TG1 1313.25 297.00 DAC 94.00 472.25 TG0 1313.25 501.00 VSS 410.75 1649.50 PWM2 631.00 1670.00 PWM1 1049.50 1670.00 VDD 1331.00 1670.00 DIE SIZE = 1510 * 1885 Pm^2 (X*Y) 1 0 - 9 V e r .1 . 0

10-10 Ver. 1.0 (3) AV4332E PIN Name X(mm) Y(mm) OKY_RW3 250.75 94.00 RW2_OPA 451.50 94.25 RW1_OPB 660.25 94.25 TG3_OPC 861.00 94.25 TG2_OPD 1069.75 94.25 TEST 1270.25 94.25 OSC 94.00 271.25 TG1 1313.25 297.00 DAC 94.00 472.25 TG0 1313.25 501.00 VSS 410.75 1870.50 PWM2 631.00 1890.25 PWM1 1049.50 1890.25 VDD 1331.00 1890.25 DIE SIZE = 1510 * 2115 Pm^2 (X*Y) (4) AV6532E PIN Name X(mm) Y(mm) OKY_RW3 259.25 94.00 RW2_OPA 460.00 94.25 RW1_OPB 668.75 94.25 TG3_OPC 869.50 94.25 TG2_OPD 1078.25 94.25 TEST 1278.75 94.25 OSC 102.50 271.25 TG1 1321.75 297.00 DAC 102.50 472.25 TG0 1321.75 501.00 VSS 419.25 2322.50 PWM2 639.50 2342.25 PWM1 1058.00 2342.25 VDD 1271.25 2364.25 DIE SIZE = 1427.25 * 2457.50 Pm^2 (X*Y) (5) AV8732E PIN Name X(mm) Y(mm) OKY_RW3 266.00 94.00 RW2_OPA 466.75 94.25 RW1_OPB 675.50 94.25 TG3_OPC 876.25 94.25 TG2_OPD 1085.00 94.25 TEST 1285.50 94.25 OSC 109.25 271.25 TG1 1328.50 297.00 DAC 109.25 472.25 TG0 1328.50 501.00 VSS 426.00 2801.25 PWM2 646.25 2821.00 PWM1 1064.75 2821.00 VDD 1271.25 2815.00 DIE SIZE = 1427.25 * 2908.25 Pm^2 (X*Y)