AVXX32E-A APLUS | Alldatasheet
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Technical content
APLUS MAKE YOUR PRODUCTION A-PLUS AVXX32E -A SERIES DATA SHEET APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115)台北市南港區成功路㆒段32 號 3 樓之 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw Sales E-mail: sales@aplusinc.com.tw Technology E-mail: service@aplusinc.com.tw
3, 7, 14 Seconds Complicate Pure Speech
Features
y Operating voltage: 2.4V~5.0V y One single-key can implement play-all, play-next and random function. y Maximum play count is 16. y Each input can implement looping function. y Single-key input can be last-key priority for stand-alone input or first-key priority. y Each input trigger can select trigger mode: (For OKY, TG0, TG1, TG3) Edge/Level, Hold/Unhold, Retrigger/Irretrigger. y Each input trigger can select its own debounce time: Fast debounce: < 200us; Slow debounce: ~16ms (S.R.=6.0kHz) y Support bouncing trigger solution for retrigger application. (Second trigger force to retrigger and slow debounce.) y Maximum table entries are 204*4. y Word count is only limited by ROM capacity. y 3 output ports for Status or LED application: Ϋʳ OP_A Status: Busy_high, DC_low, Stop_high,DC_high LED: +Fast,+Slow, Dyn(7/10), Off Ϋʳ OP_B Status: Busy_high, DC_low, Stop_high, DC_high LED: -Fast, -Slow, Dyn(9/10), On Ϋʳ OP_C Status: Busy_high, DC_low, Busy_low, DC_high LED: +Fast, +Slow, On, Off y Each output can specify its initial state (High or Low) y Outputs can be set as constant current regardless of the supply voltage varied. y Two PWM playing ports. Drive speaker or buzzer directly. y Body define: 3, 7, 14 seconds. (Total ROM size : 18k,42k,84k) y voice length(3s body:16384*5,7s body:40960*5,14s body:83968*5) y Voice algorithm: 5-bits LOG_PCM y External resister for system frequency y Sixteen default sampling frequencies are supported. The default frequencies can be changed by applying an external resistor. y Support single key play on/off. (For OKY, TG0, TG1) y Programmable only pull-low input. (For OKY,TG3) y Programmable pull-high, pull-low or floating input. (For TG0,TG1) y TG3_OPC pin can option as input or output by mask option General Description The AVXX32E -A are series of single-chip synthesizing CMOS VLSI IC which synthesizes voice by LOG_PCM algorithm. Table programming and shared multiple I/O pins make the applications flexible. Powerful functions and pure speech architecture make the AVXX32E -A series are able to best fit most speech applications and a best cost/performance ratio as a result. The programming of the AVXX32E -A series is first to define words. Each word contains voice data (or mute length), output method, assemble the words into sentences first, and then the programmer can assign the sentences to the keys corresponding to the user inputs. The TG3_OPC pin of the AVXX32E -A series is multiplexed. This means it can option as input pin or output pin. Body Option Table Body ROM Table KEY OUT AV0332E 84K D0 – 3FF OKY, TG0 – TG1 & TG3 OPA, OPB, OPC AV0732E 42K D0 – 2FF OKY, TG0 – TG1 & TG3 OPA, OPB, OPC AV1432E 18K D0 – 1FF OKY, TG0, TG3 OPA, OPC Preliminary 9 - 1 V e r .0 . 1
VDD Power Positive power supply TEST In Test enable pad, high-active, pull-low OSC In With resister connected to VDD for system clock generating OKY In Trigger input, active-high, with internal pull_low resistor. Can define as sequential key or random key. TG0, TG1 In Trigger input, active-high with internal pull_low resistor. In Trigger input, active-high TG3_OPC Out Status output OPB Out Status output OPA Out Status output PWM1, PWM2 Out Voltage output to drive speaker or buzzer VSS Power Negative power supply Absolute Maximum Rating Symbol Rating Unit VDD~VSS -0.5 ~ +0.5 V VIN (for input) V SS-0.3 < VIN < VDD+0.3 V VOUT (for all outputs) V SS < VOUT < VDD V T (operating) -10 ~ +60 к T (storage) -55 ~ +125 к DC Characteristics Symbol Parameter Min Typ. Max Unit Condition VDD Operating Voltage 2.4 3.0 5.0 V Isb Standby ΫΫ 1 ӴA VDD=3.0V, I/O open Iop Supply Current Operating ΫΫ 400 ӴA V DD=3.0V, No loading IOL OPA, OPB source Current Ϋ –20 Ϋ mA V DD=3.0V, VIP=2.7V Ioh OPA, OPB sink Current Ϋ 20 Ϋ mA V DD=3.0V, VOP=0.3V d F/F Frequency Variation by diff. lot ΫΫ r10 % VDD=4.5V fOSC =384kHz Function Diagram 1. OPA/B/C (1:0) are the output options. Output Option 0(00) 1(01) 2(10) 3(11) Status BH DL SH DHOPA LED +Fast +Slow Dy07 OFF Status BH DL SH DHOPB LED -Fast -Slow Dy09 ON Status BH DL BL DHOPC LED +Fast +Slow ON OFF Status output mode: SH: Single pulse output, hi-level output Preliminary 9 - 2 V e r .0 . 1 BH: Busy output, hi-level output
BL: Busy output, lo-level output DH: Always Hi-level output DL: Always Lo-level output LED output mode: +Fast, -Fast: High frequency alternate output +Slow, -Slow: Low frequency alternate output Dy09: Volume level (9/10)output control. If code > 9/10(FFh), then output “Lo”. Otherwise output “Hi” Dy07: Volume level (7/10)output control. If code > 7/10(FFh), then output “Lo”. Otherwise output “Hi” ON : Always Lo-level output OFF: Always Hi-level output Note: The Status and LED mode is optioned by mask option. Edge/Level mode (If sentence = word1+word2) y Edge mode Trigger length > Voice length TG Audio word1 word2 debounce time Trigger length < Voice length TG word1 word2 debounce time y Level mode Trigger length > Voice length (if sentence=word1+word2) TG Audio word1 word2 debounce time word3 word4 Trigger length < Voice length (if sentence = word1+word2) TG Audio word1 word2 debounce time Preliminary 9 - 3 V e r .0 . 1
Hold/Unhold mode (If sentence = word1+word2) y Hold mode TG Audio word1 debounce time word2 y Unhold mode TG Audio word1 word2 debounce time Retrigger/Irretrigger mode (If sentence = word1+word2) y Retrigger mode (Edge Unhold mode) TG Audio word1 debounce time word2 word3 word4 y Irretrigger mode (Edge, Unhold mode) TG Audio word1 debounce time word2 Last key priority y If TG1, TG3 are retrigger mode ˧˚˄ ˧˚ˆ Looping function If sentence is set to looping mode (sentence1_sentence2) Preliminary 9 - 4 V e r .0 . 1
Preliminary 9 - 5 V e r .0 . 1 y Unhold mode TG sentence1 sentence2Audio sentence2 sentence2 y Hold mode TG sentence1 sentence2Audio sentence2 Force to retrigger and slow debounce option (Trigger mode set to Fast debounce and Irretrigger mode) 1st TG FRSB W11 W12 W13 W14 W21 W22 W23 W24 This word must be larger than glitch period. (A mute word can be used berhaps.) Slow debounce, Retrigger mode Slow debounce, Retrigger mode Fast debounce, Irretrigger mode Fast debounce, Irretrigger mode Audio 2nd TG FRSB Audio Don't care Busy=0, FRSB set to high; Busy=1, depending on FRSB setting. If FRSB=0, force to slow debounce and retrigger mode; If FRSB=1, no change (fast debounce and irretrigger mode). Stand-alone trigger inputs are enabled at the same time Audio This voice is enabled by TG3 OKY TG0 TG1 TG3
Preliminary 9 - 6 V e r .0 . 1 Trigger input priority is TG3 > TG1 > TG0 > OKY Application circuit y External resister, Driver speaker by PWM, driver LED 9'' 26& 2.< 23B$ 3:0 3:0 5RVF 966 ROSC=200k: for frequency option 8 y Direct Keys 9''26& 2.< 3:0 3:0 966 23B$ 23B& 526& 23B%
Preliminary 9 - 7 V e r .0 . 1 y Pad Diagram & Pad Location (1) AV0332E Note: The IC substrate should be connect to VSS Pad No. Pad Name X(um) Y(um) Pad No. Pad Name X(um) Y(um) 1 PAD_OSC 108.75 214.05 6 PAD_TG0 1281.1 94.05 2 PAD_OKY 356.2 94.05 7 VDD 1302.8 595.6 3 PAD_OPA 586.1 94.05 8 PAD_PWM2 1101.9 595.6 4 PAD_TG3OPC 777.4 94.05 9 PAD_PWM1 681.1 595.6 5 PAD_TEST 1007.3 94.05 10 VSS 480.2 595.6 Chip size : 1387.9 x 696.6 ( Pm)2
Preliminary 9 - 8 V e r .0 . 1 (2) AV0732E Note: The IC substrate should be connect to VSS Pad No. Pad Name X(um) Y(um) Pad No. Pad Name X(um) Y(um) 1 PAD_OSC 108.75 214.05 7 PAD_TG1 1279.15 94.05 2 PAD_OKY 108.75 94.05 8 PAD_TG0 1279.15 214.05 3 PAD_OPA 291.65 94.05 9 VDD 1302.8 722.3 4 PAD_OPB 573.45 94.05 10 PAD_PWM2 1101.9 722.3 5 PAD_TG3OPC 764.75 94.05 11 PAD_PWM1 681.1 722.3 6 PAD_TEST 994.65 94.05 12 VSS 480.2 722.3 Chip size : 1387.9 x 823.3 ( Pm)2
Preliminary 9-9 Ver.0.1 (3)AV1432E Note: The IC substrate should be connect to VSS Pad No. Pad Name X(um) Y(um) Pad No. Pad Name X(um) Y(um) 1 PAD_OSC 108.75 214.1 7 PAD_TG1 1279.2 94.05 2 PAD_OKY 108.75 94.05 8 PAD_TG0 1279.2 214.1 3 PAD_OPA 291.65 94.05 9 VDD 1302.8 867 4 PAD_OPB 573.45 94.05 10 PAD_PWM2 1101.9 867 5 PAD_TG3OPC 764.75 94.05 11 PAD_PWM1 681.1 867 6 PAD_TEST 994.65 94.05 12 VSS 480.2 867 Chip size : 1387.9 x 968 ( Pm)2