APU3046

APU3046 A-POWER | Alldatasheet

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Technical content

Data and specifications subject to change without notice. TYPICAL APPLICATION

DESCRIPTION

The APU3046 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. The Dual synchronous con- troller can be configured as 2-independent or 2-phase controller. In 2-phase configuration, the APU3046 provides a programmable current sharing which is ideal when the output power exceeds any single input power budget. APU3046 provides a separate adjustable output by driv- ing a switch as a linear regulator. This device features programmable switching frequency up to 400KHz per phase, under-voltage lockout for all input supplies, an external programmable soft-start function as well as out- put under-voltage detection that latches off the device when an output short is detected. Dual Synchronous Controller in 24-Pin Package with 1808 out-of-phase operation LDO Controller with Independent Bias Supply Can be configured as 2-Independent or 2-Phase PWM Controller Programmable Current Sharing in 2-Phase Configu- ration Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Programmable Switching Frequency up to 400KHz Soft-Start controls all outputs Precision Reference Voltage Available 500mA Peak Output Drive Capability Short Circuit Protection for all outputs Power Good Output Synchronizable with External Clock RoHS Compliant

FEATURES

DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND LDO CONTROLLER

APPLICATIONS

Technology Licensed from International Rectifier Figure 1 - Typical application of APU3046 configured as 2-phase converter with current sharing. Dual-Phase Power Supply DDR Memory Source Sink Vtt Application Graphic Card Hard Disk Drive Power supplies requiring multiple outputs PACKAGE ORDER INFORMATION TA (°C) DEVICE PACKAGE FREQUENCY

0 To 70

APU3046O 24-Pin Plastic TSSOP (O) 200-400KHz 12V VOUT2 PGood C18 R10 3.3V VOUT1 C16 C17 C10 C13 C11 PGnd VCL VOUT3 LDrv1 HDrv1 Fb1 Vp2 Fb2 LDrv2 HDrv2 VcH1 VcH2 Vcc Gnd Comp2 Fb3 Comp1 SS PGood VREF APU3046 C12 C15 C14 Sync Rt VSEN33 VccLDO 1N4148 1N4148

Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=VCL=VccLDO=12V and TA=0 to 70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case tem- peratures equal to the ambient temperature. ABSOLUTE MAXIMUM RATINGS

PACKAGE INFORMATION

24-PIN PLASTIC TSSOP (O) PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Reference Voltage Section Fb Voltage Fb Voltage Line Regulation UVLO Section UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - VccLDO UVLO Hysteresis - VccLDO UVLO Threshold - VcH1 UVLO Hysteresis - VcH1 UVLO Threshold - VcH2 UVLO Hysteresis - VcH2 UVLO Threshold - Fb UVLO Hysteresis - Fb UVLO Threshold - VSEN33 UVLO Hysteresis - VSEN33 Supply Current Section Vcc Dynamic Supply Current VcH1 Dynamic Supply Current VcH2 Dynamic Supply Current Vcc Static Supply Current VcH1 Static Supply Current VcH2 Static Supply Current VccLDO Static Supply Current 5<Vcc<12 Supply Ramping Up Supply Ramping Up Supply Ramping Up Supply Ramping Up Fb Ramping Down Supply Ramping Up Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF SS=0V SS=0V SS=0V SS=0V 1.225 1.250 0.2 4.2 0.25 4.2 0.25 3.5 0.2 3.5 0.2 0.6 0.1 2.5 0.2 3.5 1.275 V V V V V V V V V V V V V mA mA mA mA mA mA mA θJA = 84°C/W Vcc Comp1 Comp2 Rt Sync VcH2 HDrv2 LDrv2 Fb2 PGnd VCL LDrv1 HDrv1 VcH1 VccLDO VOUT3 Fb3 SS Fb1 VSEN33 Vp2 PGood VREF Gnd TOP VIEW VFB LREG UVLOVCC UVLOVCCLDO UVLOVCH1 UVLOVCH2 UVLOFb UVLOVSEN33 Dyn ICC Dyn ICH1 Dyn ICH2 ICCQ ICH1Q ICH2Q ICLDO

SYM TEST CONDITION MIN TYP MAX UNITS Soft-Start Section Charge Current Power Good Section Fb1 Lower Trip Point Fb1 Upper Trip Point Fb2 Lower Trip Point Fb2 Upper Trip Point Fb3 Lower Trip Point Fb3 Upper Trip Point Power Good Voltage OK Error Amp Section Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance 1 Transconductance 2 Input Offset Voltage for PWM2 Oscillator Section Frequency Ramp Amplitude Output Drivers Section Rise Time Fall Time Dead Band Time Max Duty Cycle Min Duty Cycle LDO Controller Section Drive Current Fb Voltage Input Bias Current SS=0V Fb1 Ramping Down Fb1 Ramping Up Fb2 Ramping Down Fb2 Ramping Up Fb3 Ramping Down Fb3 Ramping Up 5K resistor pulled up to 5V SS=3V SS=0V Fb2 to VP2 Rt=Open Rt=Gnd CL=1500pF CL=1500pF Fb=1V, Freq=200KHz Fb=1.5V 4.5 180 300 1.225 0.9VREF 1.1VREF 0.9VREF 1.1VREF 0.9VREF 1.1VREF 4.8 -0.1 -64 400 600 200 350 1.25 150 1.25 0.5 220 450 100 100 250 1.275 µA V V V V V V V µA µA µmho µmho mV KHz V ns ns ns mA V µA PIN DESCRIPTIONS PIN# PIN SYMBOL PIN DESCRIPTION 5,6 VREF Vp2 Fb2 Fb1 Vcc Comp1, Comp2 Rt Sync VcH2 VcH1 Reference Voltage. Non-inverting input to the second error amplifier. In the current sharing mode, it is con- nected to the programming resistor. In independent 2-channel mode it is connected to VREF pin when Fb2 is connected to the resistor divider to set the output voltage. Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a resistor divider to set the output voltage and Fb2 is connected to programming resistor to achieve current sharing. In independent 2-channel mode, these pins work as feedback inputs for each channel. Supply voltage for the internal blocks of the IC. Compensation pins for the error amplifiers. The switching frequency can be programmed between 200KHz and 400KHz by connect- ing a resistor between Rt and Gnd. By floating the pin, the switching frequency will be 200KHz and by grounding the pin, the switching frequency will be 400KHz. The internal oscillator may be synchronized to an external clock via this pin. Supply voltage for the high side output drivers. These are connected to voltages that must be at least 4V higher than their bus voltages (assuming 5V threshold MOSFET). A mini- mum of 1µF, high frequency capacitor must be connected from these pins to PGnd to provide peak drive current capability. SSIB PGFB1L PGFB1H PGFB2L PGFB2H PGFB3L PGFB3H VPG IFB1 IFB2 gm1 gm2 VOS(ERR)2 Freq VRAMP Tr Tf TDB TON TOFF ILDO VFBLDO ILDO(BIAS)

PIN# PIN SYMBOL PIN DESCRIPTION 10,15 11,14 HDrv2, HDrv1 LDrv2, LDrv1 PGnd VCL VccLDO VOUT3 Fb3 SS VSEN33 PGood Gnd Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from these pins to ground for the application when the inductor current goes negative (Source/Sink), soft-start at no load and for the fast load transient from full load to no load. Output driver for the synchronous power MOSFET. This pin serves as the separate ground for MOSFET’s driver and should be connected to the system’s ground plane. A high frequency capacitor (0.1 to 1µF) must be connected from Vcc, VCL, VcH1 and VcH2 pins to this pin for noise free operation. Supply voltage for the low side output drivers. Separate input supply for LDO controller. Driver signal for the LDO’s external transistor. LDO’s feedback pin, connected to a resistor divider to set the output voltage of LDO. This pin provides soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. The converter can be shutdown by pulling this pin below 0.5V. Sense the LDO input voltage for UVLO. Power good pin. This pin is a collector output that switches Low when any of the outputs are outside of the specified under voltage trip point. Analog ground for internal reference and control circuitry. Connect to PGnd with a short trace. Figure 2 - Block diagram of the APU3046. Bias Generator LDrv2 Two Phase Oscillator 1.25V Ramp1 Fb3 Sync 0.5V POR POR Gnd HDrv2 VcH2 VccLDO SS Comp2 1.25V Error Amp2 PWM Comp2 POR VOUT3 25uA 25K 25K Reset Dom LDrv1 VCL HDrv1 VcH1 Fb1 Comp1 Error Amp1 PWM Comp1 25K 25K Reset Dom Set1 Set2 Ramp2 64uA Max UVLO 4.2V / 4.0V VcH2 3.5V / 3.3V VcH1 3.5V / 3.3V Vsen33 2.5V / 2.3V 4.2V / 4.0V Fb2 25K 25K 40mA LDO Controller PGnd VccLDO Vcc Rt 1.25V 1.25V VSEN33 SS>2V Vp2 VREF PGood Fb3 Fb2 Fb1 PGood Fb2 Monitor Shut Down 10K R S Q Q S R SS BLOCK DIAGRAM

The APU3046 is designed for multi-outputs applications. It includes two synchronous buck controllers and a lin- ear regulator controller. The two synchronous controller operates with fixed frequency voltage mode and can be configured as two independent controller or 2-phase con- troller with current sharing. The timing of the IC is pro- vided through an internal oscillator circuit. These are two out of phase oscillators and can be programmed by us- ing an external resistor from 200KHz to 400KHz per phase. Figure 11 shows switching frequency versus ex- ternal resistor. Independent Mode In this mode the APU3046 provides two independent out- puts with either common or different input voltages. The output voltage of the individual channel is set and con- trolled by the output of the error amplifier, this is the amplified error signal from the sensed output voltage and the reference voltage. This voltage is compared to the ramp signal and generates fixed frequency pulses of vari- able duty-cycle, which drives the two N-channel exter- nal MOSFETs. Current Sharing Mode In the current sharing mode, the two converter’s outputs tied together and provide one single output (see Figure 1). In this mode, one control loop acts as a master and sets the output voltage as a regular Voltage Mode buck controller and the other control loop acts as a slave and monitors the current information for current sharing. The current sharing is programmable and sets by using two external resistors in output currents’ path. The slave's error amplifier, error amplifier 2 (see Block Diagram) mea- sures the voltage drops across the current sense resis- tors, the differential of these signals is amplified and compared with the ramp signal and generate the fixed frequency pulses of variable duty cycle to match the output currents. Out of Phase Operation The APU3046 drives its two output stages 180 o out of phase. In 2-phase configuration, the two inductor ripple currents cancel each other and result to a reduction of the output current ripple and contribute to a smaller out- put capacitor for the same ripple voltage requirement. In application with single input voltage, the 2-phase con- figuration reduces the input ripple current. This results in much smaller RMS current in the input capacitor and reduction of input capacitor. Soft-Start The APU3046 has a programmable soft start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start se- quence initiates when the Vcc, VcH1, VcH2, VccLDO and VSEN33 rise above their threshold and generates the Power On Reset (POR) signal. Soft-start function oper- ates by sourcing an internal current to charge an exter- nal capacitor to about 3V. Initially, the soft-start function clamps the E/A’s output of the PWM converter. As the charging voltage of the external capacitor ramps up, the PWM signals increase from zero to the point the feed- back loop takes control. Shutdown The converter can be shutdown by pulling the soft-start pin below 0.5V. This can be easily done by using an external small signal transistor. During shutdown the MOSFET drivers and the LDO controller turn off. Power Good The APU3046 provides a power good signal. This is an open collector output and it is pulled low if the output voltages are not within the specified threshold. This pin can be left floating if not used. Short-Circuit Protection The outputs are protected against the short circuit. The APU3046 protects the circuit for shorted output by sens- ing the output voltages. The APU3046 shuts down the PWM signals and LDO controller, when the output volt- ages drops below the set values. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs and LDO controller remain in the off state whenever the supply voltages drop below set parameters. Normal operation resumes once the supply voltages rise above the set values. Frequency Synchronization The APU3046 can be synchronized with an external clock signal. The synchronizing pulses must have a minimum pulse width of 100ns. If the sync function is not used, the Sync pin can be either connected to ground or be floating.

APPLICATION INFORMATION

Design Example: The following example is a typical application for APU3046 in current sharing mode. The schematic is Figure 13 on page 15. PWM Section Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb1 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb1 pin when the output is at its desired value. The output voltage is defined by using the following equation: When an external resistor divider is connected to the output as shown in Figure 3. Figure 3 - Typical application of the APU3046 for programming the output voltage. Equation (1) can be rewritten as: If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft start capacitance value. The start up time of the converter can be calculated by using: Where: CSS is the soft-start capacitor (µF) For a start-up time of 7.5ms, the soft-start capacitor will be 0.1µF. Choose a ceramic capacitor at 0.1µF. Boost Supply To drive the high-side switch it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 1. The capacitor is charged up to approximately twice the bus voltage. A capacitor in the range of 0.1µF to 1µF is generally adequate for most applications. Sense Resistor Selection These resistors will determine the current sharing between two channels. The relationship between the Master and Slave output currents is expressed by: For an equal current sharing, RSEN1=RSEN1 Choose RSEN1=RSEN2=5mΩ Input Capacitor selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of control MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: Where: D is the Duty Cycle, simply D=VOUT/VIN. IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For VIN1=5V, IOUT1=8A and D1=0.3 Results to: IRMS1=3.6A And for VIN2=12V, IOUT2=8A and D2=0.125 Results to: IRMS2=2.6A tSTART = 75 × Css (ms) ---(2) Fb1 APU3046 VOUT1 For Switcher: VIN1(MASTER) = 5V VIN2(SLAVE) = 12V VOUT1 = 1.5V IOUT = 16A ∆VOUT = 75mV fS = 200KHz For Linear Regulator: VIN3 = 3.3V VOUT2 = 2.5V IOUT2 = 2A VOUT1 = VREF × 1 + ---(1) ( ) R6 = R5 × - 1 VOUT1 VREF ( ) This will result to: VOUT1 = 1.5V, VREF = 1.25V, R5 = 1K, R6 = 200Ω RSEN1 × IMASTER = RSEN2 × ISLAVE ---(3) IRMS = IOUT D×(1-D) ---(4)

For higher efficiency, a low ESR capacitor is recom- mended. For VIN1=5V, choose two Poscap from Sanyo 6TPB330M (6.3V, 330µF, 40mΩ, 3A) For VIN2=12V, choose two 16TPB47M (16V, 47µF, 70mΩ, 1.4A). Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy sta- bility requirements. The ESR of the output capacitor is calculated by the following relationship: The Sanyo TPC series, Poscap capacitor is a good choice. The 6TPC150M 150µF, 6.3V has an ESR 40mΩ. Se- lecting six of these capacitors in parallel, results to an ESR of ≅ 7mΩ which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capaci- tor, the lower will be the output ripple voltage. The resulting output ripple current is smaller then each channel ripple current due to the 1808 phase shift. These currents cancel each other. The cancellation is not the maximum because of the different duty cycle for each channel. Inductor Selection The inductor is selected based on output power, operat- ing frequency and efficiency requirements. Low induc- tor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor (∆i); the optimum point is usually found between 20% and 50% ripple of the output current. Where: VIN = Maximum Input Voltage VOUT = Output Voltage ∆i = Inductor Ripple Current fS = Switching Frequency ∆t = Turn On Time D = Duty Cycle For the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: For ∆i1=30% of I1, we get: L1=2.18µH For ∆i2=30% of I2, we get: L2=2.7µH The Coilcraft DO5022HC series provides a range of in- ductors in different values and low profile for large cur- rents. For L1 choose: DO5022P-222HC (2.2µH,12A) For L2 choose: DO5022P-332HC (3.3µH,10A) Power MOSFET Selection The selections criteria to meet power transfer require- ments is based on maximum drain-source voltage (VDSS), gate-source drive voltage (VGS), maximum output cur- rent, On-resistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Caution should be taken with devices at very low VGS to prevent undesired turn-on of the complemen- tary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes con- duction and switching losses. For the Buck converter the average inductor current is equal to the DC load cur- rent. The conduction loss is defined as: The total conduction loss is defined as: PCOND (Upper Switch) = ILOAD × RDS(ON) × D × ϑ PCOND (Lower Switch) = ILOAD × RDS(ON) × (1 - D) × ϑ ϑ = RDS(ON) Temperature Dependency PCON(TOTAL)=PCON(Upper Switch)ϑ + PCON(Lower Switch)ϑ ESR ≤ ---(5) ∆VO ∆IO Where: ∆VO = Output Voltage Ripple ∆IO = Output Current ∆VO=75mV and ∆IO=10A, result to ESR=7.5mΩ VIN - VOUT = L× ; ∆t = D× ; D = fS VOUT VIN L = (VIN - VOUT)× ---(6) VOUT VIN×∆i×fS

The master error amplifier is a differential-input transcon- ductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback the transconductance properties of the E/A become evi- dent and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp1 pin to ground as shown in Figure 6. The ESR zero of the LC filter expressed as follows: Figure 6 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): Use the following equation to calculate R4: Where: VIN(MASTER) = Maximum Input Voltage VOSC = Oscillator Ramp Voltage FO1 = Crossover Frequency for the master E/A FESR = Zero Frequency of the Output Capacitor FLC(MASTER) = Resonant Frequency of Output Filter gm = Error Amplifier Transconductor R5 and R6 = Resistor Dividers for Output Voltage Programming This results to: R4=29.7KΩ. Choose: R4=29.4KΩ To cancel one of the LC filter poles, place the zero be- fore the LC filter resonant frequency pole: Using equations (12) and (14) to calculate C9, we get: One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FO1 > FESR and FO1 ≤ (1/5 ~ 1/10)× fS For: VIN(MASTER) = 5V VOSC = 1.25V FO1 = 30KHz FESR = 25.26KHz FLC(MASTER) = 3.57KHz R5 = 1K R6 = 200Ω gm = 600µmho FP = 2π × R4 × C9 × CPOLE C9 + CPOLE C9 = 2003pF Choose: C9 = 2200pF VOUT VREF Ve E/A1 FZ H(s) dB Frequency Gain(dB) Fb1 Comp1 FESR = ---(9) 2π×ESR×Co FZ = ---(12) 2π × R4 × C9 R6 × R5 FZ ≅ 75%FLC(MASTER) FZ ≅ 0.75 × 2π LO × CO ---(14) For: Lo = 2.2µH Co = 900µF Fz = 2.67KHz R4 = 24.9KΩ R4 = ---(13) VOSC VIN(MASTER) FO1×FESR FLC2 R5 + R6 gm H(s) = gm× ---(10) ( ) R6 + R5 1 + sR4C9 sC9

The pole sets to one half of switching frequency which results in the capacitor CPOLE: For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensa- tion network. The typically used compensation network for voltage-mode controller is shown in Figure 7. Figure 7 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: The error amplifier gain is independent of the transcon- ductance under the following condition: By replacing ZIN and Zf according to figure 7, the trans- former function can be expressed as: Ve 1 - gmZf 1 + gmZIN VOUT = As known, transconductance amplifier has high imped- ance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the ampli- fier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two ze- ros and they are expressed as follows: Cross Over Frequency: The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (15) regarding transconduc- tance error amplifier. Select the crossover frequency: Select R7, so that R7 >> Place first zero before LC’s resonant frequency pole. gm Fo < FESR and Fo ≤ (1/10 ~ 1/6)× fS FZ1 ≅ 75% FLC C11 = 2π × FZ1 × R7 CPOLE = ≅ π × R4 × fS - π × R4 × fS For FP << fS FP1 = 0 2π×C10×(R6 + R8) FZ2 = ≅ 2π×C10×R6 FZ1 = 2π×R7×C11 FP3 = ≅ 2π×R7× FP2 = 2π×R8×C10 2π×R7×C12 C12×C11 C12+C11 ( ) VOUT VREF C10 C12 C11 Ve FZ1 FZ2 FP2 FP3 E/A1 Zf ZIN Frequency Gain(dB) H(s) dB Comp1 Fb1 gmZf >> 1 and gmZIN >>1 ---(15) H(s)= sR6(C12+C11) 1+sR7 ×(1+sR8C10) 1 (1+sR7C11)×[1+sC10(R6+R8)] ×[ ( )] C12C11 C12+C11 Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors VIN VOSC 2π×Lo×Co

FP3 = fS Place third pole at the half of the switching frequency. C12 > 50pF If not, change R7 selection. Place R7 in (16) and calculate C10: Place second pole at ESR zero. FP2 = FESR Check if R8 > If R8 is too small, increase R7 and start from step 2. Place second zero around the resonant frequency. FZ2 = FLC Use equation (1) to calculate R5: These design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load tran- sient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to - 12dB). The phase margin should be greater than 458 for overall stability. The slave error amplifier is a differential-input transcon- ductance amplifier as well, the main goal for the slave feed back loop is to control the inductor current to match the masters inductor current as well provides highest bandwidth and adequate phase margin for overall stabil- ity. gm The transfer function of power stage is expressed by: As shown the transfer function is a function of inductor current. The transfer function for the compensation network is given by equation (18), when using a series RC circuit as shown in Figure 8: Figure 8 - The PI compensation network for slave channel. The loop gain function is: Select a zero crossover frequency (FO2) one-tenth of the switching frequency: FO2 = 20KHz Where: VIN = Input Voltage VOUT = Output Voltage L2 = Output Inductor VOSC = Oscillator Peak Voltage C12 = 2π × R7 × FP3 R8 = 2π × C10 × FP2 R6 = - R8 2π × C10 × FZ2 R5 = × R6 VREF VOUT - VREF RS2 RS1 Ve IL2 IL1 Fb2 E/A2 Comp2 Vp2 C10 ≤ × 2π × Lo × FO × Co VOSC VIN G(s) = = ---(17) IL2(s) Ve(s) VIN - VOUT sL2 × VOSC D(s) = = Ve(s) RS2 × IL2(s) 1 + sC2R2 sC2 ( ) RS1 RS2 ( ) gm× ---(18) FO2 = fS H(s)=[G(s) × D(s) × RS2] 1+sR2C2 sC2 ( ) ( ) gm× RS1 RS2 ( ) VIN-VOUT sL2×VOSC H(s)=RS2×

From (18), R2 can be express as: Set the zero of compensator to be half of FLC(SLAVE), the compensator capacitor, C2, can be calculated as: Using equations (20) and (21) we get the following val- ues for R2 and C2. LDO Section Output Voltage Programming Output voltage for LDO is programmed by reference volt- age and external voltage divider. The Fb3 pin is the in- verting input of the error amplifier, which is internally ref- erenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb3 pin when the output is at its desired value. The output voltage is defined by using the following equa- tion: Results to R7=1KΩ C2=6606pF; Choose: C2=6800pF R2=16.45K; Choose: R2=16.5K LDO Power MOSFET Selection The first step in selecting the power MOSFET for the linear regulator is to select the maximum RDS(ON) based on the input to the dropout voltage and the maximum load current. Results to: RDS(ON)(MAX) = 0.4Ω Note that since the MOSFET RDS(ON) increases with tem- perature, this number must be divided by ~1.5 in order to find the RDS(ON)(MAX) at room temperature. The IRLR2703 has a maximum of 0.065Ω RDS(ON) at room temperature, which meets our requirements. Layout Consideration The layout is very important when designing high fre- quency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the con- nection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two par- allel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control cir- cuit ground (analog ground), to which all signals are ref- erenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. R2 = × gm × RS1 2π × FO2 × L2 × VOSC VIN(SLAVE) - VOUT ---(20) R10 VOUT2 = VREF× 1+( ) For: VOUT2 = 2.5V VREF = 1.25V R10 = 1KΩ RDS(ON) = VIN3 - VOUT2 IOUT2 For: VIN3 = 3.3V VOUT2 = 2.5V IOUT2 = 2A H(Fo) = gm×RS1×R2× =1 ---(19) VIN - VOUT 2π×Fo×L2×VOSC FLC(SLAVE) = 2π L2×COUT Fz = FLC(SLAVE) C2 = ---(21) 2π × R2 × Fz Fb3 APU3046 VOUT3 R10 Figure 9 - Programming the output voltage for LDO.

Figure 12 - Typical application for APU3046 configured for DDR memory application. TYPICAL APPLICATION 12V 1.8V @ 2A PGood 33uF 47uF 1uF 47uF 3.3V VDDQ 2.5V @ 4A C16 330uF C17 2x 150uF C10 0.1uF 5600pF 3900pF 1uF 1uF PGnd VCL VOUT3 LDrv1 HDrv1 Fb1 Vp2 LDrv2 HDrv2 VcH1 VcH2 Vcc Gnd Comp2 Fb3 Comp1 SS PGood VREF APU3046 C14 150uF Sync Rt VSEN33 VccLDO 1uH 5.6uH 4.7uH VTT 1.25V @ 4A C12 330uF Fb2 442 10K 16.2K IRLR2703 1/2 of Q2 IRF7313 C13 1uF 1/2 of Q3 IRF7313 VDDQ 1/2 of D1 BAT54A 1/2 of D1 BAT54A 1/2 of Q3 IRF7313 1/2 of Q2 IRF7313

Dual Input: 5V and 12V to 1.5V @ 16A Figure 13 - Demo-board application of APU3046. 12V 2.5V @ 2A PGood C13 47uF 3.3V C29 0.1uF C34 1uF PGnd VCL VOUT3 LDrv1 HDrv1 Fb1 Vp2 Fb2 LDrv2 HDrv2 VcH1 VcH2 Vcc Gnd Comp2 Fb3 Comp1 SS PGood VREF APU3046 IRF7457 IRF7460 Sync Rt VSEN33 VccLDO 1uF R6 10Ω R7 1K R10 C18 47uF R21 16.5K 6.8nF C24 R16 29.4K 2200pF C30 1uF R13 15K IRF7457 IRF7460 33uF 33uF 330uF C31 330uF 1uF 47uF C32 47uF 1uH 1uH 0.1uF BAT54S BAT54A C23 1uF L4 3.3uH L3 2.2uH R17 5mΩ 5mΩ 200 R12 C10,C11,C12 3x 150uF C15 1uF C19,C20,C21 3x 150uF 1.5V @ 16A 1uF R19 4.7Ω C26 470pF C14 470pF 4.7Ω Q3 IRLR2703 BAT54A

Ref Desig Description Value Qty Part# Manuf Web site (www.) Q1,Q4 Q2,Q5 D2,D4 L1,L2 C1,C2 C4,C32 C5,C31 C10,11,12, 19,20,21 C3,C29 C24 C34 C14,C26 C6,7,8, 15,23,30 C13,C18 R2,4,15,18 R16 R21 R5,R19 R7,10,12 R3,R17 R13 MOSFET MOSFET MOSFET Controller Diode Diode Inductor Inductor Inductor Cap, Tantalum Cap, Poscap Cap, Poscap Cap, Poscap Cap, Ceramic Cap, Ceramic Cap, Ceramic Cap, Ceramic Cap, Ceramic Cap, Ceramic Cap, Tantalum Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor IRF7460 IRF7457 IRLR2703 APU3046 BAT54S BAT54A or 1N4148 D03316P-102 D05022P-222HC D05022P-332HC ECS-T1CD336R 16TPB47M 6TPB330M 6TPC150M ECJ-2VF1E104Z ECJ-3YB1E105K ECJ-2VB1H222K ECJ-2VB1H682K ECJ-2VC1H471J ECJ-2VF1C105Z ECS-T1AD476R ERJ-M1WSF5MOU IR IR IR APEC IR IR Any Coilcraft Coilcraft Coilcraft Panasonic Sanyo Sanyo Sanyo Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic 20V, 10mΩ, 12A 20V, 7mΩ, 15A 30V, 0.045Ω, 23A Synchronous PWM Fast Switching Fast Switching 1µH, 6.8A 2.2µH, 12A 3.3µH, 10A 33µF, 16V 47µF, 16V 330µF, 6.3V 150µF, 6.3V, 40mΩ 0.1µF, Y5V, 25V 1µF, X7R, 25V 2200pF, X7R, 50V 6800pF, X7R, 50V 470pF, X7R, 50V 1µF, Y5V, 16V 47µF, 10V 2.15Ω 29.4K 16.5K 4.7Ω 200, 1% 1K, 1% 5mΩ, 1W, 1% 15K 10Ω irf.com coilcraft.com maco.panasonic.co.jp sanyo.com/industrial maco.panasonic.co.jp DEMO-BOARD APPLICATION Application Parts List

Package Outline : TSSOP-24 Millimeters SYMBOLS MIN NOM MAX A 1.20 0.05 0.15 0.08 1.00 1.05 b 0.19 0.30 C 0.09 0.20 D 7.70 7.80 7.90 E 6.40 4.30 4.40 4.50 e 0.65 L 0.45 0.60 0.75 1.00 0.08 θ 0.00 8.00 Part Marking Information & Packing : TSSOP-24 y ADVANCED POWER ELECTRONICS CORP. U3046O YWWSSS Package Code Part Number Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence