APU3037

APU3037 A-POWER | Alldatasheet

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Technical content

Data and specifications subject to change without notice. 200507075-1/18 TYPICAL APPLICATION

DESCRIPTION

The APU3037 controller IC is designed to provide a low cost synchronous Buck regulator for on-board DC to DC converter applications. With the migration of today’s ASIC products requiring low supply voltages such as 1.8V and lower, together with currents in excess of 3A, traditional linear regulators are simply too lossy to be used when input supply is 5V or even in some cases with 3.3V input supply. The APU3037 together with dual N-channel MOSFETs such as AP60T03, provide a low cost solution for such applications. This device features an internal 200KHz oscillator (400KHz for "A" version), under-volt- age lockout for both Vcc and Vc supplies, an external programmable soft-start function as well as output un- der-voltage detection that latches off the device when an output short is detected. Synchronous Controller in 8-Pin Package Operating with single 5V or 12V supply voltage Internal 200KHz Oscillator (400KHz for APU3037A) Soft-Start Function Fixed Frequency Voltage Mode 500mA Peak Output Drive Capability Protects the output when control FET is shorted RoHS Compliant PACKAGE ORDER INFORMATION

FEATURES

8-PIN SYNCHRONOUS PWM CONTROLLER

APPLICATIONS

DDR memory source sink Vtt application Low cost on-board DC to DC such as 5V to 3.3V, 2.5V or 1.8V Graphic Card Hard Disk Drive TA (°C) DEVICE PACKAGE FREQUENCY

0 To 70 APU3037O 8-Pin Plastic TSSOP (O) 200KHz

0 To 70 APU3037M/MP 8-Pin Plastic SOIC NB (M/MP) 200KHz

0 To 70 APU3037AO 8-Pin Plastic TSSOP (O) 400KHz

0 To 70 APU3037AM/AMP 8-Pin Plastic SOIC NB (M/MP) 400KHz

Technology Licensed from International Rectifier Figure 1 - Typical application of APU3037 or APU3037A. APU3037 Vcc Vc HDrv LDrv Fb Gnd Comp SS/SD 0.1uF C4 1uF 0.1uF 2200pF 24k AP60T03GH AP60T03GH 1.24K, 1% 249, 1% 5.6uH, 5.3A 1uHC2 10TPB100M, 100uF, 55m V 47uF 1.5V/5A 2x 6TPC150M, 150uF, 40m V 12V 1N4148

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS Reference Voltage Fb Voltage Fb Voltage Line Regulation UVLO UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - Vc UVLO Hysteresis - Vc UVLO Threshold - Fb UVLO Hysteresis - Fb Supply Current Vcc Dynamic Supply Current Vc Dynamic Supply Current Vcc Static Supply Current Vc Static Supply Current Soft-Start Section Charge Current APU3037 APU3037A 5<Vcc<12 Supply Ramping Up Supply Ramping Up Fb Ramping Down (APU3037) (APU3037A) Freq=200KHz, CL=1500pF Freq=200KHz, CL=1500pF SS=0V SS=0V SS=0V 1.225 0.784 4.0 3.1 0.4 0.3 0.5 -10 1.250 0.800 0.2 4.2 0.25 3.3 0.2 0.6 0.4 0.1 3.3 -20 1.275 0.816 0.35 4.4 3.5 0.8 0.5 4.5 -30 V V V V V V V mA mA mA mA mA VFB LREG UVLO Vcc UVLO Vc UVLO Fb Dyn Icc Dyn Ic ICCQ ICQ SSIB θJA=160°C/W without exposed pad (M)θJA=124°C/W Fb Vcc LDrv Gnd HDrv Vc Comp SS/SD 8Fb Vcc LDrv Gnd SS/SD Comp Vc HDrv4 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc=5V, Vc=12V and TA=0 to 70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.

PACKAGE INFORMATION

8-PIN PLASTIC TSSOP (O) 8-PIN PLASTIC SOIC (M/MP) θJA=80°C/W with exposed pad (MP)

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS PIN DESCRIPTIONS This pin is connected directly to the output of the switching regulator via resistor divider to provide feedback to the Error amplifier. This pin provides biasing for the internal blocks of the IC as well as power for the low side driver. A minimum of 1mF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. Output driver for the synchronous power MOSFET. This pin serves as the ground pin and must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1mF) must be connected from V5 and V12 pins to this pin for noise free operation. Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from this pin to ground for the application when the inductor current goes negative (Source/ Sink), soft-start at no load and for the fast load transient from full load to no load. This pin is connected to a voltage that must be at least 4V higher than the bus voltage of the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of 1mF, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. Compensation pin of the error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. This pin provides soft-start for the switching regulator. An internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. The converter can be shutdown by pulling this pin below 0.5V. Error Amp Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance Oscillator Frequency Ramp-Amplitude Voltage Output Drivers Rise Time Fall Time Dead Band Time Max Duty Cycle Min Duty Cycle SS=3V, Fb=1V SS=0V, Fb=1V APU3037 APU3037A CL=1500pF CL=1500pF Fb=1V, Freq=200KHz Fb=1.5V 450 180 360 1.225 -0.1 -64 600 200 400 1.25 150 750 220 440 1.275 100 100 250 mA mA mmho KHz V ns ns ns PIN# PIN SYMBOL PIN DESCRIPTION Fb Vcc LDrv Gnd HDrv Vc Comp SS / SD IFB1 IFB2 gm Freq VRAMP Tr Tf TDB TON TOFF

Figure 2 - Simplified block diagram of the APU3037. THEORY OF OPERATION Introduction The APU3037 is a fixed frequency, voltage mode syn- chronous controller and consists of a precision refer- ence voltage, an error amplifier, an internal oscillator, a PWM comparator, 0.5A peak gate driver, soft-start and shutdown circuits (see Block Diagram). The output voltage of the synchronous converter is set and controlled by the output of the error amplifier; this is the amplified error signal from the sensed output voltage and the reference voltage. This voltage is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle, which drives the two N-channel ex- ternal MOSFETs.The timing of the IC is provided through an internal oscillator circuit which uses on-chip capaci- tor to set the oscillation frequency to 200 KHz (400 KHz for “A” version). Soft-Start The APU3037 has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start se- quence initiates when the Vc and Vcc rise above their threshold (3.3V and 4.2V respectively) and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start func- tion clamps the E/A’s output of the PWM converter. As the charging voltage of the external capacitor ramps up, the PWM signals increase from zero to the point the feedback loop takes control. Short-Circuit Protection The outputs are protected against the short-circuit. The APU3037 protects the circuit for shorted output by sens- ing the output voltage (through the external resistor di- vider). The APU3037 shuts down the PWM signals, when the Fb voltage drops below 0.6V (0.4V for APU3037A). The APU3037 also protects the output from over-voltaging when the control FET is shorted. This is done by turning on the sync FET with the maximum duty cycle. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if Vc and Vcc fall below 3.3V and 4.2V respec- tively. Normal operation resumes once Vc and Vcc rise above the set values. 20uA 64uA Max POR Oscillator Error Amp Ct Error Comp Reset Dom POR 0.5V FbLo Comp Vc HDrv Vcc LDrv Gnd Vcc 4.0V Vc 3.5V 0.2V 0.2V Bias Generator 1.25V POR 8SS/SD Fb 1 Comp 7 25K 25K 1.25V R S Q

Figure 3 - Typical application of the APU3037 for programming the output voltage.

APPLICATION INFORMATION

Design Example: The following example is a typical application for APU3037, the schematic is Figure 18 on page 14. Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 1.25V (0.8V for APU3037A). The divider is ratioed to pro- vide 1.25V at the Fb pin when the output is at its desired value. The output voltage is defined by using the follow- ing equation: When an external resistor divider is connected to the output as shown in Figure 3. Equation (1) can be rewritten as: Choose R5 = 1KV This will result to R6 = 1.65KV If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft start capacitance value. The start up time of the converter can be calculated by using: Where: CSS is the soft-start capacitor ( mF) For a start-up time of 7.5ms, the soft-start capacitor will be 0.1mF. Choose a ceramic capacitor at 0.1mF. Shutdown The converter can be shutdown by pulling the soft-start pin below 0.5V. The control MOSFET turns off and the synchronous MOSFET turns on during shutdown. Boost Supply Vc To drive the high-side switch it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 18. The capacitor is charged up to approximately twice the bus voltage. A capacitor in the range of 0.1mF to 1 mF is generally adequate for most applications. In application, when a separate voltage source is available the boost circuit can be avoided as shown in Figure 1. Input Capacitor Selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The larger capacitor, the less ripple expected but consider should be taken for the higher surge current during the power-up. The APU3037 provides the soft-start function which controls and limits the current surge. The value of the input capacitor can be calculated by the following formula: Where: CIN is the input capacitance ( mF) IIN is the input current (A) Dt is the turn on time of the high-side switch ( ms) DV is the allowable peak to peak voltage ripple (V) Fb APU3037 VOUT R R tSTART = 753Css (ms) ---(2) VIN = 5V VOUT = 3.3V IOUT = 4A DVOUT = 100mV fS = 200KHz R6 = R5 3 - 1VOUT VREF( ) VOUT = VREF 3 1 + ---(1)R6 R5( ) CIN = ---(3)IIN 3 Dt DV

Assuming the following: By using equation (3), CIN = 193.3mF For higher efficiency, low ESR capacitor is recommended. Choose two 100mF capacitors. The Sanyo TPB series PosCap capacitor 100 mF, 10V with 55mV ESR is a good choice. Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy sta- bility requirements. The ESR of the output capacitor is calculated by the following relationship: The Sanyo TPC series, PosCap capacitor is a good choice. The 6TPC150M 150mF, 6.3V has an ESR 40mV. Selecting two of these capacitors in parallel, results to an ESR of ≅ 20mV which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capaci- tor, the lower will be the output ripple voltage. Inductor Selection The inductor is selected based on output power, operat- ing frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. Gener- ally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor (Δi). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: If Di = 20%(IO), then the output inductor will be: The Toko D124C series provides a range of inductors in different values, low profile suitable for large currents, 10mH, 4.2A is a good choice for this application. This will result to a ripple approximately 14% of output cur- rent. Power MOSFET Selection The APU3037 uses two N-Channel MOSFETs. The se- lections criteria to meet power transfer requirements is based on maximum drain-source voltage (V DSS), gate- source drive voltage (VGS), maximum output current, On- resistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and cau- tion should be taken with devices at very low VGS to pre- vent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes con- duction and switching losses. For the Buck converter the average inductor current is equal to the DC load cur- rent. The conduction loss is defined as: The RDS(ON) temperature dependency should be consid- ered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. PCOND (Upper Switch) = ILOAD 3 RDS(ON) 3 D 3 q PCOND (Lower Switch) = ILOAD 3 RDS(ON) 3 (1 - D) 3 q q = RDS(ON) Temperature Dependency Where: DVO = Output Voltage Ripple DIO = Output Current DVO=100mV and DIO=4A Results to ESR=25m V ESR [ ---(4)DVO DIO Where: VIN = Maximum Input Voltage VOUT = Output Voltage Δi = Inductor Ripple Current fS = Switching Frequency Δt = Turn On Time D = Duty Cycle VIN - VOUT = L3 ; Dt = D3 ; D =Di Dt fS VOUT VIN L = (VIN - VOUT)3 ---(5)VOUT VIN3Di3fS L = 7mH Dt = D 3 Dt = 3.3ms1 fS IIN = IIN = 2.93A DV = 1%(VIN), Efficiency(h) = 90% VO 3 IO h 3 VIN

Note that this method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5KHz to 50KHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as fol- lows: Figure 6 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): Use the following equation to calculate R4: Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 and R6 = Resistor Dividers for Output Voltage Programming gm = Error Amplifier Transconductance This results to R4=104.4KV. Choose R4=105KV To cancel one of the LC filter poles, place the zero be- fore the LC filter resonant frequency pole: Using equations (11) and (13) to calculate C9, we get: One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to supress the switching noise. The additional pole is given by: The pole sets to one half of switching frequency which results in the capacitor C POLE: For: VIN = 5V VOSC = 1.25V Fo = 30KHz FESR = 26.52KHz FLC = 2.9KHz R5 = 1K R6 = 1.65K gm = 600mmho C9 = 698pF Choose C9 = 680pF FP = 2p 3 R4 3 C9 3 CPOLE C9 + CPOLE V OUT V REF R R R C VeE/A FZ H(s) dB Frequency Gain(dB) Fb Comp FESR = ---(8)1 2p 3 ESR 3 Co FZ ≅ 75%FLC 2p LO 3 CO For: Lo = 10mH Co = 300mF FZ = 2.17KHz R4 = 86.6KV Fo > FESR and FO [ (1/5 ~ 1/10)3 fS R6 + R5 1 + sR4C9 sC9 FZ = ---(11)1 2p3R43C9 R63R5 R4 = ---(12)VOSC VIN Fo3FESR FLC2 R5 + R6 gm3 33 CPOLE = p3R43fS - for FP << fS ≅ 1 p3R43fS

For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensa- tion network. The typically used compensation network for voltage-mode controller is shown in Figure 7. Figure 7 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: The error amplifier gain is independent of the transcon- ductance under the following condition: By replacing ZIN and Zf according to Figure 7, the trans- former function can be expressed as: As known, transconductance amplifier has high imped- ance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the ampli- fier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two ze- ros and they are expressed as follows: Cross Over Frequency: The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (14) regarding transconduc- tance error amplifier. 1) Select the crossover frequency: Fo < FESR and Fo [ (1/10 ~ 1/6)3 fS 2) Select R7, so that R7 >> 3) Place first zero before LC’s resonant frequency pole. FZ1 ≅ 75% FLC 4) Place third pole at the half of the switching frequency. C12 > 50pF If not, change R7 selection. 5) Place R7 in (15) and calculate C10: gm 1 - gmZf 1 + gmZIN Ve VOUT Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors C11 = 1 2p 3 FZ1 3 R7 C12 = 1 2p 3 R7 3 FP3 FP3 = fS C10 [ 32p 3 Lo 3 Fo 3 Co VOSC VIN FP1 = 0 2p3C103(R6 + R8)FZ2 = ≅ 1 2p3C103R6 FZ1 = 1 2p3R73C11 FP3 = ≅1 C123C11 C12+C11 2p3R73 2p3R73C12 FP2 = 1 2p3R83C10 ( )V OUT V REF R R C C C 11R Ve FZ 1 FZ 2 FP 2 FP E/A Zf Z IN Frequency Gain(dB) H(s) dB Fb Comp gmZf >> 1 and gmZIN >>1 ---(14) H(s)= 3 (1+sR7C11)3[1+sC10(R6+R8)]1 sR6(C12+C11) 1+sR7 3(1+sR8C10)[ ( )] C123C11 C12+C11 FO = R73C103 3 ---(15)VIN VOSC 2p3Lo3Co

6) Place second pole at the ESR zero. FP2 = FESR Check if R8 > If R8 is too small, increase R7 and start from step 2. 7) Place second zero around the resonant frequency. FZ2 = FLC 8) Use equation (1) to calculate R5. These design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load tran- sient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to - 12dB). The phase margin should be greater than 458 for overall stability. IC Quiescent Power Dissipation Power dissipation for IC controller is a function of ap- plied voltage, gate driver loads and switching frequency. The IC's maximum power dissipation occurs when the IC operating with single 12V supply voltage (Vcc=12V and Vc≅24V) at 400KHz switching frequency and maxi- mum gate loads. Figures 9 and 10 show voltage vs. current, when the gate drivers loaded with 470pF, 1150pF and 1540pF ca- pacitors. The IC's power dissipation results to an exces- sive temperature rise. This should be considered when using APU3037A for such application. Layout Consideration The layout is very important when designing high fre- quency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the con- nection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two par- allel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control cir- cuit ground (analog ground), to which all signals are ref- erenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. Figure 8 shows a suggested layout for the critical com- ponents, based on the schematic on page 14. Figure 8 - Suggested layout. (Topside shown only) gm R8 = 1 2p 3 C10 3 FP2 R6 = - R 8 2p 3 C10 3 FZ2 R5 = 3 R6 VREF VOUT - VREF C D D

2 APU3037

C2A, B C7A, B Analog Gnd PGnd PGnd Vout PGnd D Single Point Analog Gnd Connect to Power Ground plane Analog Gnd PGnd

Figure 18 - Typical application of APU3037 in an on-board DC-DC converter using a single 5V supply. APU3037 Vcc Vc HDrv LDrv Fb Gnd Comp SS/SD 0.1uF 1uF 0.1uF 680pF 105K AP60T03GH AP60T03GH 1K, 1% 1.65K, 1% 744311470 4.7uH 1uH 2x 10TPB100ML, 100uF, 55m V 47uF Tantalum 3.3V @ 4A 2x 6TPC150M, 150uF, 40m V 0.1uF 1N4148 1N4148 1N4148 1N4148

Figure 19 - Typical application of APU3037 or APU3037A in an on-board DC-DC converter providing the Core, GTL+, and Clock supplies for the Pentium II microprocessor. TYPICAL APPLICATION Dual Supply, 5V Bus and 12V Bias Input APU3037 Vcc Vc HDrv LDrv Fb Gnd Comp SS/SD Vcc Vc HDrv LDrv Fb Gnd Comp 12V APU1206-18 2.5V/2A 1.8V/1A 47uF 47uF 1uH 10TPB100M, 100uF, 55m V, 1.5A rms AP60T03GH 3.5uH @ 2.5AQ2 AP60T03GH 1K, 1% 1uF 0.1uF 0.1uF 2200pF 14K C10 0.1uF C11 1uF C13 0.1uF C14 2200pF 14K 1K, 1% 1.65K, 1% AP60T03GH 3.4uH @ 2A AP60T03GH 10TPB100M, 100uF, 55m V, 1.5A rms 3.3V/1.8A 3.5uH @ 2.5A 5.7uH @ 2.5A 6TPB150M, 150uF, 55m V (Qty 2) 6TPB150M, 150uF, 55m V (Qty 1) 6TPB150M, 150uF, 55m V C12 6TPB150M, 150uF, 55m V APU3037 U2SS/SD 1N4148 1N4148

1.8V to 7.5V / 0.5A Boost Converter Figure 20 - Typical application of APU3037 as a boost converter. SS/SD Comp Vc HDrv Fb Vcc LDrv Gnd APU3037 10K 20K Vpwr (1.5V Min) Vc/Vcc VOUT (7.5V / 0.5A) Gnd 2x 47uF 1N5817 1uH 2x 68uF 5K, 1%1K, 1% 1uF 25K 20K 2N2222 2N2222 1uF AP60T03GH 0.01uF 0.1uF C10 100pF R5 R6

5V or 12V to 3.3V @ 10A Ref Desig Description Value Qty Part# Manuf D1, D2, D4 C2A, C2B C9B, C9C C5, C6 C8, C13, C19 MOSFET MOSFET Controller Diode Inductor Inductor Capacitor, Tantalum Capacitor, Poscap Capacitor, Poscap Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Resistor Resistor Resistor Resistor AP60T03GH AP60T03GH APU3037 LL4148 7445601 7443550320 ECS-T1CD336R 16TPB47M 6TPC150M ECJ-2VF1E104Z ECJ-3YB1E105K ECJ-2VB1H222K ECJ-2VB2D471K ECJ-2VF1C105Z APEC APEC APEC Application Parts List 30V, 12mV, 4 5A 0V, 12mV, 45A Synchronous PWM Fast Switching 1mH, 10A 3.2mH, 12A 33mF, 16V 47mF, 16V, 70mV 150mF, 6.3V, 40mV 0.1mF, Y5V, 25V 1mF, X7R, 25V 2200pF, X7R, 50V 470pF, X7R 1mF, Y5V, 16V 20K, 5% 4.7V, 5% 1K, 1% 1.65K, 1% Figure 21 - Demo-board application of APU3037. APU3037 Vcc Vc HDrv LDrv FbGnd Comp SS/SD Gnd Gnd V IN 5V or 12V AP60T03GH AP60T03GH C2A 47uF 16V C2B 47uF 16V 20K 33uF 16V LL4148 LL4148 0.1uF 3.2uH 470pF 4.7V C9B 150uF 6.3V C13 1uF 1uH 1uF C19 1uF 1uF 0.1uF 2200pF 1.65K LL4148 V OUT 3.3V @ 10A C9C 150uF 6.3V WE WE 1N4148