APR6008

APR6008 APLUS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 23

Technical content

Features

• Multi-level analog storage - High quality audio recording and playback
• Dual mode storage of analog and/or digital data - Eliminates the need for separate digital memory
• Advanced, non-volatile Flash memory technology - No battery backup required
• SPI interface - Allows any commercial microcontroller to control the device
• Programmable Sampling Clock - Allows user to choose quality and duration levels
• Single 3V power supply
• Low power consumption - Playback operating current: 15 mA typical - Standby current: 1 uA maximum - Automatic power-down
• Multiple package options available - CSP, SOP, PDIP, Bare Die
• On-board clock prescaler - Eliminates the need for external clock dividers
• Automatic squelch circuit - Reduces background noise during quiet passages General Description The APR6008 offers non-volatile storage of voice and/or data in a dvanced M ulti-Level F lash m emory. Up t o 8 m inutes of audio recording and playback can be accommodated. A max- imum o f 3 0K b its o f d igital da ta can be s tored. devices can b e cas caded for longer du ration r ecording or greater d igital storage. D evice control is accomplished through a n i ndustry st andard SP I i nterface that allows a microcontroller to manage message recording and playback. This f lexible a rrangement allows f or the widest va riety of messaging options. The APR6008 is ideal for use in cellular and cordless phones, telephone answering devices, personal digital a ssistants, pe rsonal voice r ecorders, and voice pa g- ers. APLUS Integrated achieves this high level of storage capabi- lity by using a proprietary analog multi-level storage te chnol - logy i mplemented in an advanced non-volatile Flash memory process. Eac h m emory ce ll ca n typically s tore 256 voltage levels. Th is a llows t he APR6008 voice to reproduce audio signals in their natural form, eliminating the need for enco- ding and compression which can introduce distortion. Figure 1 APR6008 Pinout Diagrams /C S DI DO V SSD NC NC NC A N A O U T - A N A O U T + NC /R ES E T V S SA A UD O UT S Q L C AP S C L K V CCD E X T C L K /IN T S A C V S SA NC /B U S Y NC NC V CCA A N A IN + A N A IN - /S Q LO U T 28 pin DIP INTEGRATED CIRCUITS INC. APR6008

Page 2 Voice Recording & Playback Device Revision 2.1 Functional Description The EXTCLK p in a llows the us e of an ex ternal sam pling clock. Th is input ca n a ccept a wide range of f requencies depending on the divider ratio p rogrammed into t he d ivider that follows the clock. Alternatively, the programmable inter- nal oscillator can b e used to supply the sampling clock. The Mux following both signals automatically selects the EXTCLK signal if a c lock is p resent, o therwise the internal oscillator source is chosen. Detailed information on how to program the divider and internal oscillator can be found in the explanation of t he PWRUP command, whi ch appe ars in t he OpCode Command Description section. Guidance on how to choose the appropriate sample clock frequency can be found in the Sampling Rate & Voice Quality section. The au dio s ignal con taining the content you wish to r ecord should be fed into t he di fferential inputs ANAI N-, a nd ANAIN+. After pre-amplification the signal is routed into the anti-aliasing filter. The anti-aliasing filter automatically adapts its response based on the sample rate being used. No exter- nal anti-aliasing filter is therefore required. After passing through the anti-alias filter, the signal is fed into the sam ple and ho ld circuit which works i n conjunction with the Ana log W rite C ircuit t o store ea ch analog sample in a flash memory cell. When a read operation is d esired the A nalog Re ad C ircuit extracts t he ana log data f rom the m emory a rray an d f eeds the signal to the Internal Low P ass Filter. The low pass filter converts the individual samples into a continuous output. The output signal then goes to the squelch control circuit and d i- fferential output driver. The differential output driver feeds the ANAOUT+ an d ANAO UT- pins. Bo th differential output p ins swing around a 1.23V potential. The s quelch control circuit automatically reduces the o utput signal by 6 dB during quiet passages. A copy of the squelch control s ignal i s present on t he SQLOUT p in to f acilitate reducing gain in the external amplifier as well. For more infor- mation, refer to the Squelch section. After pass ing t hrough the squelch c ircuit the o utput s ignal goes to the output amplifier. The output amplifier drives a sin- gle ended output on the AUDOUT pin. The single ended out- put swings around a 1.23V potential. All SPI c ontrol and hand sh aking s ignals are routed to the Master Control Circuit. This circuit decodes all the SPI signals and generates all the internal control signals. It also contains the status r egister u sed for ex amining the c urrent s tatus of the APR6008 . Figure 2 APR6008 Block Diagram SAC Low Pass Master Control Circuit Amp SCLK /CS DI DO /INT /RESET AUDOUT /SQLOUT Squelch Amp A NAOU T + A N AOU T - /BUSY SQLCAP R ow De coder Column Decoder Column Address Row Address Single Analog Memory Cell

1.92 Mcell Memory Array

Voice Recording & Playback Device Page 3 Revision 2.1 Memory Organization The APR6008 memory array is organized to allow the great- est flexibility in m essage m anagement a nd d igital s torage. The sm allest addressable m emory un it i s ca lled a “sector”. The APR6008 contains 640 sectors. Figure 3 Memory Map. Sectors 0 through 639 can be used for analog storage. Du - ring audio recording o ne m emory ce ll is u sed p er sample clock cycle. When recording is stopped an end of data (EOD) bit is programed into the memory. This prevents playback of silence when partial sectors are use d. Unused memory that exists between the EOD bit and the end of the sector can not be used. Sectors 0 through 9 are t ested and guaranteed f or di gital storage. Other sectors, with the exception of sector 639, can store data but have not been tested, and are thus not guaran- teed to provide 100% good b its. This can be managed with error correction o r f orward che ck-before-store m ethods. Once a write cycle is initiated all previously written data in the chosen sector is lost. Mixing audio signals and digital data within the same sector is not possible. Note: There are a total of 15bits reserved for addressing. The APR6008 only requires 10 bits. The additional 5 bits are used for larger devices within the APR6008 family. SPI Interface All memory management is handled by an external host pro- cessor. The host processor communicates with the APR6008 through a simple S erial Pe ripheral Interface (SPI) Po rt. The SPI p ort can run on a s l ittle as three wi res or as m any as seven de pending o n t he am ount o f c ontrol ne cessary. This section will describe how to manage me mory u sing t he APR6008 SPI Po rt an d associated O pCode com mands. This topic is broken down into the following sections:

• Sending Commands to the Device
• OpCode Command Description
• Receiving Device Information
• Current Device Status (CDS)
• Reading the Silicon Identification (SID)
• Writing Digital Data
• Reading Digital Data
• Recording Audio Data
• Playing Back Audio Data
• Handshaking Signals Sending Commands to the Device This se ction describes the p rocess o f sen ding OpCodes to the APR6008 All Opcodes are sent in the same way with the exception of the DIG_WRITE a nd DIG_READ commands. The DIG_WRITE and DIG_READ commands are described in the Writing Digital Data and Reading Digital Data sections that follow. The minimum SPI configuration nee ded to send commands uses the DI, /CS, and SCLK pins. The device will accept inputs o n the D I pin whene ver the /CS pi n is l ow. OpCode commands are clocked in on the rising edge of the SPI c lock. F igure 4 shows the t iming d iagram f or sh ifting OpCode commands into the device. Figure 5 is a description of the OpCode stream. You must wait for a command to finish executing before send- ing a new command. This is accomplished by monitoring the / BUSY p in. You can su bstitute monitoring of the busy pin by inserting a fixed delay be tween com mands. The required delay is specified as T ne xt1,T next2,T ne xt3 or T ne xt4. Figure 6 shows the timing di agram for se nding consecutive com- mands. Table 1 describes which Tnext specification to use. Sector 0 Sector 1 Sector 639 Can Not be Used for Digital Data SAC Trigger Point APR6008

Voice Recording & Playback Device Page 5 Revision 2.1 Table 1 Sequential Command Timing OpCode Command Description Designers have access t o a total of 1 4 OpCodes. These OpCodes a re listed in Table 2. The nam e o f the O pcode appears in the left hand column. The following two columns represent the actual binary information contained in the 20 bit data s tream. Som e com mands have l imits on wh ich com - mand can follow them. These limits are shown in the “Allow- able Follow on Com mands” column. T he la st c olumn summarizes each command. Combinations o f O pCodes can be u sed to accommodate almost any memory management scheme. Table 2 APR6008 Operational Codes Current Command Next command Timing Symbol NOP SID Any Command Tnext1 5u SEC PWRUP Any Command Tnext2 5m SEC STOP_PWDN PWRUP Tnext2 5m SEC SET_REC REC STOP, STOP_PWDN, SET_REC, REC,NOP Within SAC Low Time SET_PLAY PLAY STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP SET_FWD FWD SET_FWD, FWD, STOP, STOP_PWDN DIG_WRITE DIG_READ DIG_ERASE Any Digital Command, STOP, STOP_PWDN Note: For partial DIG_READ Tnext2 is measured from the extra clock low that follows the 8K sampling rate: 376m SEC 4K sampling rate: 752 m SEC rise of /CS, not from the rise of /CS Tnext3 STOP Any Command Tnext4 470m SEC Instruction Name OpCode (5 bits) Opcode Parameters (15bits) Allowable Follow on Commands Summary [Op4 - Op0] [Address MSB - Address LSB] [Address 14 - Address 0] NOP [00000] [Don’t Care] All Commands No Operation SID [00001] [Don’t care] All Commands Causes the silicon ID to be read. SET_FWD [00010] Sector Address [A14 - A0] SET_FWD, FWD, STOP, STOP_PWDN Starts a fast forward operation from the sector address specified. FWD [00011] [Don’t care] SET_FWD, FWD, STOP, STOP_PWDN Starts a fast forward operation from the current sector address. PWRUP [00100] [A14-A10]: all zeros [A9-A2]: EXTCLK divider ratio [A1-A0]: Sample Rate Frequency All Commands Resets the device to initial conditions. Sets the sample frequency and divider ratios. STOP [00110] [Don’t care] All Commands Stops the current operation. STOP_PWDN [00111] [Don’t care] PWRUP Stops the current operation. Causes the device to enter power down mode. APR6008

Page 6 Voice Recording & Playback Device Revision 2.1 The NOP command performs no operation in the device. It is most often used wh en reading the current device status. For more i nformation o n reading d evice s tatus see t he Current Device Status section. THE SID operation instructs the device to return the contents of its silicon ID register. For more information see the Read- ing the SID section. The SET_FWD command instructs the device to fast forward from the be ginning of the sector specified in the O pCode parameter field. The device will fast forward until either an EOD bit, or the end of the sector is reached. If no EOD bit or forthcoming c ommand h as b een received w hen the end of the sector is reached, the device will loop back to the begin- ning of the same sector and begin the same process again. If an EO D b it is found the de vice w ill stop an d generate an interrupt on the /INT pin. The output amplifiers are muted dur- ing this operation. The FWD command instructs the device to fast forward from the start of the current sector to the next EOD marker. If no EOD marker is found within the current sector the device will increment to the next sequential sector and continue looking. The device will co ntinue to fast forward in this manner un til either an EOD is reached, a new command is sent, or the end of the m emory array is reached. W hen a n EO D is reached the device will stop and generate an interrupt on the /INT pin. The output amplifiers are muted during this operation. The PWRUP command causes the device to enter power up mode and s et the internal c lock frequency an d EXTCLK divider ratio. To select an Internal oscillator frequency set the [A1 - A0] bits according to the following binary values: If you a re u sing an external sample c lock s ignal you m ust also set the EXTCLK d ivider ratio. This divider ratio is equal to N:1 where N is an integer between 1 and 256, excluding 2. The N value should be selected to satisfy the following equa- SET_REC [01000] Sector Address [A14 - A0] STOP, STOP_PWDN, SET_REC, REC,NOP Starts a record operation from the sector address specified. REC [01001] [Don’t care] STOP, STOP_PWDN, SET_REC, REC,NOP Starts a record operation from the current sector address. DIG_ERASE [01010] Sector Address [A14 - A0] All Commands Erases all data contained in specified sec- tor. You must not erase a sector before recording voice signals into it. You must erase a sector before storing digital data in it. DIG_WRITE [01011] [A14 - A0][XXXX][D0 - D3004][XXXX] All Commands This command writes data bits D0 - D3003 starting at the specified address. All 3004 bits must be written. DIG_READ [01111] Sector Address [A14 - A0] All Commands This command reads data bits D0 - D3003 starting at the specified address. SET_PLAY [01100] Sector Address [A14 - A0] STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP Starts a play operation from the sector address specified. PLAY [01101] [Don’t care] STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP Starts a play operation from the current sector address. Instruction Name OpCode (5 bits) Opcode Parameters (15bits) Allowable Follow on Commands Summary [Op4 - Op0] [Address MSB - Address LSB] [Address 14 - Address 0] A1 A0 Sample rate 0 0 6.4 kHz 0 1 4.0 kHz 1 0 8.0 kHz 1 1 5.3 kHz

Voice Recording & Playback Device Page 7 Revision 2.1 tion as closely as possible: EXTCLK freq = (N) * (128) * (selected sampling frequency) Example: Suppose that 8 .0 KH z sampling is d esired. As sume that the frequency of the signal present on EXTCLK = 8MHz. Rounding up, N = 8 The O p Code Pa rameter b it stream, composed of b its [A9 - A2 ][A1 - A 0], therefore becomes binary [00001000][10]. The STOP Command causes the devi ce to stop the current operation. The STOP_PWDN command cau ses the devi ce to stop t he current command and enter power down mode. During power down the device c onsumes significantly less powe r. The PWRUP com mand m ust be u sed to force the de vice into power up mode before any commands can be executed. The SET_REC co mmand i nstructs the device t o be gin recording at the sector address specified. Th e d evice will continue t o record un til the end o f t he cu rrent se ctor i s reached. I f n o f orthcoming command has b een received when t he end of the s ector is r eached the de vice wi ll loop back t o the beginning of the same sector and overwrite the previously recorded material. If the next command is another SET_REC or REC command the device will execute the com- mand immediately following the end o f the current sector so that no audio information is lost. For more information see the section entitled Recording Audio Data. The REC command instructs the device to begin recording in the current sector. If no new command is received before the device reaches the end of the sector the device will automati- cally increment to the next se quential sector and continue recording. The dev ice will continue to record in this manner until the m emory is exhausted or a STOP or STOP_PWDN command is received. For more information see the section entitled Recording Audio Data. The DIG_ERASE command erases all data contained in the sector specified. Erase should not be done before recording voice signals into a sector. Erase must be done before storing digital data in a sector. The DIG_WRITE com mand st ores 3K bi ts of digital da ta in the s pecified sector. A ll 3K b its must be wr itten, n o pa rtial usage of the sector is possible. The memory acts as a FIFO, the first data bit shifted in will be the first data bit shifted out. A sector m ust be e rased using the DIG_ERASE co mmand BEFORE data can be written to the sector. For more informa- tion on s toring d igital data, s ee the section entitled Writing Digital Data. The DIG_READ com mand i nstructs t he device t o r etrieve digital data that was previously written to the specified sector. The first bit shifted out is the first bit that was written. The last bit shifted out is the last bit that was wr itten. For more infor- mation on reading digital data see the section entitled Read- ing Digital Data. The SET_PLAY command instructs the device to begin play- back a t t he spe cified s ector. If no f orthcoming command is received, or EOD bit encountered, before the end of the sec- tor is reached the device will loop back to the beginning of the same sector and continue playback with no noticeable gap in the audio output. If the next command is another SET_PLAY or PLAY c ommand the d evice will execute t he c ommand immediately following the end of the current sector so that no gap in playback is present. For more information see the sec- tion entitled Playing Back Audio Data. The PLAY command instructs the device to begin playback at the current sector. If no forthcoming command is received, or EOD bit enco untered, before the device reaches the en d of the sector the device will automatically increment to the next sequential sector and con tinue playing. The dev ice will con- tinue to play in this manner until the memory is exhausted or a STOP or STOP_PWDN com mand is received. For m ore information see the section entitled Playing Back Audio Data. N 8000000 APR6008

Page 14 Voice Recording & Playback Device Revision 2.1 low edge of the SAC signal as an indicator that the next seg- ment needs to be selected, and do so before the SAC signal returns high. Failing to specify the next command before the current se gment is exhausted (either du ring r ecording or playback) will result in a noticeable gap during playback. The /BUSY pin indicates when the device is performing either a play, record or fast forward function. The host microproces- sor c an m onitor t he bus y pin t o confirm t he st atus of these commands. The Busy pin is normally high and goes low while the device is busy. The low time is governed by the length of recording or playback specified by the user. Sampling Rate and Voice Quality The Nyquist Sampling Theorem requires that the highest fre- quency component a sam pling system can ac commodate without the introduction of aliasing errors is equal to half the sampling frequency. The APR6008 au tomatically fi lters its input, based on the selected sampling frequency, to meet this requirement. Higher sam pling rates increase recording bandw idth, and hence voice quality, but also use m ore memory cells for the same am ount o f recording time. The APR6008 accommo- dates sampling rates as high as 8kHz. Lower sampling rates use less memory cells and effectively increase t he du ration capabilities o f the de vice, but also reduce recording ban dwidth. The APR6008 allows sam pling rates as low as 4 kHz. Designers can thus con trol t he quality/duration t rade-off by controlling the sampling frequency. Sampling frequency c an be controlled by using the PWRUP command. This command can c hange sam pling f requency r egardless of whe ther t he internal oscillator is used or an external clock is used. The APR6008 d erives its sampling c lock f rom o ne o f two sources; internal or external. If a clocking signal is present on the EXTCLK input the device will automatically use this signal as t he s ampling clock source. I f n o input i s p resent o n t he EXTCLK input the device automatically defaults to the inter- nal clock source. When the EXTCLK pin is not used it should be tied to GND. An internal clock divider is provided so that external clock sig- nals can be di vided down t o a de sired sam pling rate. This allows high frequency signals of up to 10 MHz to be fed into the EXTCLK p in. Us ing t his feature s implifies designs b y allowing use o f a c lock a lready p resent in t he system, as opposed to having to generate or ex ternally divide d own a custom c lock. Details for p rograming the c lock divider a re described in the SP I i nterface section unde r the PW RUP paragraph. The default power up condition for the APR6008 is to use the internal oscillator at a sampling frequency of 6.4 kHz. Storage Technology The APR6008 stores vo ice signals b y sam pling i ncoming voice data and storing the sampled signals d irectly in to FLASH memory cells. Each FLASH ce ll can support voltage ranges from 1 to 256 levels. These 256 d iscrete voltage lev- els a re t he e quivalent o f e ight (28=256) b it b inary enc oded values. During playback the stored signals are retrieved from memory, sm oothed to form a c ontinuous signal an d f inally amplified before being fed to an external speaker amplifier. Squelch The APR6008 i s e quipped with an internal squelch feature. The Squelch circuit automatically attenuates the output signal by 6 db during quiet passages in the playback material. Mut- ing the output s ignal d uring quiet pas sages he lps e liminate background no ise. Background no ise may enter the system in a number of ways including: present in the original signal, natural no ise p resent i n some power am plifier designs, or induced through a poorly filtered power supply. The response time of the squelch circuit is controlled by the time constant of the capacitor connected to the SQLCAP pin. The r ecommended va lue o f this capa citor is 1. 0 uF. The squelch feature can be disabled by connecting the SQLCAP pin to VCC. The active low output /SQL goes low wh enever the internal squelch activates. This signal can be used to squelch the out- put power amplifier. Squelching the output amplifier results in further reduction of noise; especially when the powe r ampli- fier is run at high gain & loud volumes. APR6008

Page 16 Voice Recording & Playback Device Revision 2.1 Pin Descriptions Table three sh ows p in descriptions for the APR6008 device. All pins ar e listed i n numerical o rder with t he exception of VCC, VSS and N C pins which a re l isted a t the end o f the table. Table 3 APR6008 28 Pin Number & Description Pin Name Pin No. 28 pin SOP Pin No. 28 pin DIP Pad No. (Die) Reference Figure Functionality SAC 24 24 27 Sector Address Control Output: This active low output indicates when the device is nearing the end of the current segment. /INT 25 25 28 Interrupt Output: This active low open drain output goes low whenever the device reaches the end of a message or the device overflows. When connected to the interrupt input of the host microcontroller this output can be used to imple- ment powerful message management options. EXTCLK 26 26 29 External Clock Input: This input can be used to feed the device an external sample clock instead of using the internal sampling clock. This pin should be con- nected to VSSA when not in use. SCLK 28 28 33 SPI Clock Input: Data is clocked into the device through the DI pin upon the ris- ing edge of this clock. Data is clocked out of the part through the DO pin on the falling edge. /CS 1 1 2 Chip Select Input: This active low input selects the device as the currently active slave on the SPI interface. When this pin is high the device tri-states the DO pin and ignores data on the DI pin. DI 2 2 3 Data Input: The DI input pin receives the digital data input from the SPI bus. Data is clocked on the rising edge of the SCLK input. DO 3 3 4 Data Output: Data is available after the falling edge of the SCLK input. ANAOUT- 8 8 9 Negative Audio Output: This is the negative audio output for playback of pre- recorded messages. This output is usually fed to the negative input of a differen- tial input power amplifier. The power amplifier drives an external speaker. ANAOUT+ 9 9 10 Positive Audio Output: This is the positive audio output for playback of pre- recorded messages. This output is usually fed to the positive input of a differential input power amplifier. The power amplifier drives an external speaker. /RESET 11 11 11 Reset Input: This active low input clears all internal address registers and restores the device to its power up defaults. AUDOUT 13 13 15 Single Ended Audio Output: This is the audio output for playback of pre- recorded messages. This output is usually fed to the input of a power amplifier for driving an external speaker. SQLCAP 14 14 16 Squelch Capacitor I/O: This pin controls the attack time of the squelch circuitry. Connect his pin to GND through a 1.0 uf capacitor to enable the squelch feature. The capacitor’s time constant will affect how quickly the squelch circuitry reacts. Connect this pin to VCCA to disable the squelch feature. /SQL 15 15 17 Squelch Output: This active low output indicates when the internal squelch cir- cuitry has activated. This signal can be used to automatically squelch the external power amplifier. Squelching the external power amplifier can result in an even greater reduction of background noise. ANAIN- 16 16 18 Inverting Analog Input: This input is the inverting input for the analog signal that the user wishes to record. When the device is used in a differential input configu- ration this pin should receive a 16 mV peak to peak input coupled through a 0.1uF capacitor. When the device is used in a single ended input configuration this input should be tied to VSSA through a 0.1 uF capacitor.

Voice Recording & Playback Device Page 17 Revision 2.1

Electrical Characteristics

The following tables list Absolute Maximum Ratings, Recom- mended DC Ch aracteristics, and recommended AC Ch arac- teristics for the APR6008 device. Absolute Maximum Ratings Stresses greater than those listed in Table 4 may cause per- manent dam age to t he device. These spe cifications r epre- sent a stress rating only. Operation of the device at these or any o ther con ditions a bove those spe cified in the recom- mended DC Char acteristics or recommended AC Character- istics of this specification is not implied. Maximum conditions for extended periods may affect reliability. Table 4 Absolute Maximum Ratings. ANAIN+ 17 17 19 Non-Inverting Analog Input: This input is the non-inverting input for the analog signal that the user wishes to record. When the device is used in a differential input configuration this pin should receive a 16 mV peak to peak input coupled through a 0.1 uF capacitor. When the device is used in a single ended input con- figuration this pin should receive a 32 mV peak to peak input coupled through a 0.1 uF capacitor. /BUSY 21 21 23 Busy Output: This active low output is low during either a record, playback or fast forward operation. The pin is tri-stated otherwise. This pin can be connected to an LED to indicate playback/record operation to the user. This pin can also be connected to an external microcontroller as an indication of the status of play- back, record, forward, or digital operation. VCCD 27 27 30, 31, 32 Digital Power Supply: This connection supplies power for all on-chip digital cir- cuitry. This pin should be connected to the 3.0 V power plane through a via. This pin should also be connected to a 0.1 uF bypass cap as close to the pin as possi- ble. VCCA 18 18 20, 21 Analog Power Supply: This connection supplies power for all on-chip analog circuitry. This pin should be connected to the 3.0 V power plane through a via. This pin should also be connected to a 0.1 uF bypass cap as close to the pin as possible. VSSA 12,23 12,23 12, 13, 14, 24, 25, 26 Analog Ground: These pins should be connected to the ground plane through a via. The connection should be made as close to the pin as possible. VSSD 4 4 5, 6 Digital Ground: This pin should be connected to the ground plane through a via. The connection should be made as close to the pin as possible. NC 5, 6, 7, 10, 19, 20, 22 5, 6, 7, 10, 19, 20, 22 1, 7, 8, 22 No Connect: These pins should not be connected to anything on the board. Con- nection of these pins to any signal, GND or VCC may result in incorrect device behavior or cause damage to the device. Pin Name Pin No. 28 pin SOP Pin No. 28 pin DIP Pad No. (Die) Reference Figure Functionality Item Symbol Condition Min Max Unit Power Supply voltage VCC TA = 25 C -0.3 7.0 V Input Voltage VIN TA = 25 C Device VCC = 3.0 V -0.3 5.5 V Storage Temperature TSTG - -65 150 oC Temperature Under Bias TBS - -65 125 oC Lead Temperature TLD <10s 300 oC

Page 18 Voice Recording & Playback Device Revision 2.1 Table 5 DC Characteristics Table 6 AC Characteristics Item Symbol Condition Min Typ Max Unit Operating Voltage VCCA VCCD 2.9 3.0 3.3 V Operating Temperature TA 0 +70 oC Input High Voltage VIH VCC = 2.9V 2.4 3 5.5 V Input Low Voltage VIL VCC = 3.3V VSS - 0.3V 0 .4 V Output High Voltage VOH VCC = 2.7V IOH=-1.6mA VCCD - 0.5V V Output Low Voltage VOL VCC = 2.7V IOL=1.0mA 0.4 V Input Leakage Current IIH VCC = 3.3V VIH=VCC 0.3 1 uA Input Leakage Current IIL VCC = 3.3V uA VIL=VSS 0 -1 Output Tristate Leakage Current IOZ VCC = 3.3V VOUT=VCC uA or VOUT=Vss Operating Current Consumption ICC VCC = 3.3V Recording Playback Idle 2.5 mA mA mA Standby Current Consumption ICCS VCC = 3.3V uA After 20 sec. Item Symbol Condition Min Typ Max Unit ANAIN+ or ANAIN- input voltage VMI 45 50 mVP-P ANAIN+ input resistance RANAIN Ohm3 k ANAIN+/ANAIN- Gain GANAIN 22 23 dB ANAOUT Output Voltage VANOUT 560 700 mVP-P Total Harmonic Distortion THD @ 1kHz & 45mVP-P input 0.5 1 % VCC ready to fall /CS Tpwrup 90% of VCC min. specification 10 ms /RESET low time TloRST 1 ms Rise /RESET to fall /CS TRdone 1 ms /CS fall to clock edge Tfcs 500 ns SPI Data set-up time TsuDI 200 ns Period SPI clock TpSCLK 1000 ns SPI data hold time ThDI 200 ns SPI clock low time TloSCLK 400 ns

Voice Recording & Playback Device Page 19 Revision 2.1 SPI clock high time ThiSCLK 400 ns Clock to rising edge of /CS TrCS 200 ns Fall of /CS to DO output TfcsDO 200 ns Fall of SCLK to data out valid TfSCLK 1000 ns Rise of /CS to DO high Z ThzDO 500 ns Period SPI clock for digital read, write DTpSCLK @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 500 uS 250 uS Equation 1 S First SET_REC command to start recording Tarec @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 376 188 Equation 2 ms ms S Rise of SAC after STOP Com- mand to end of recording TSarec @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 376 188 Equation 2 ms ms S First SET_PLAY command to audio output Taplay @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 376 188 Equation 2 ms ms S STOP after SET_PLAY or PLAY to end of audio output TSaplay @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 376 188 Equation 2 ms ms S SAC period TpSAC REC, PLAY @4kHz REC, PLAY @8kHz REC, PLAY EXTCLK FWD @4kHz FWD @8kHz FWD @ EXTCLK 752 376 Equation 3 Equation 4 ms ms ms ms S SAC low time TloSAC REC, PLAY @4kHz REC, PLAY @8kHz REC, PLAY EXTCLK FWD @4kHz FWD @8kHz FWD @ EXTCLK equation 5 0.25 0.125 Equation 6 ms ms ms ms S See Figure 6 and Table 1 Tnext1 5 uS See Figure 6 and Table 1 Tnext2 mS5 See Figure 6 and Table 1 Tnext3 @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 752 376 Equation 3 ms ms S Item Symbol Condition Min Typ Max Unit

Page 20 Voice Recording & Playback Device Revision 2.1 Notes: See Figure 6 and Table 1 Tnext4 Previous command = SET_REC, REC, SET_PLAY, PLAY @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 470 235 Equation 7 ms ms S Previous command = SET_FWD, FWD @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 1.25 0.625 Equation 8 ms ms Previous command = All Others @4kHz Internal sample clock @8kHz Internal sample clock External sample clock 5 uS 5 uS 5 uS Item Symbol Condition Min Typ Max Unit Equat ion1 Exter nalCloc kPeriod Equat ion2 1504 Ex terna lClockPe rio d() Equat ion3 3008 Ex terna lClockPe rio d() Equat ion4 8 Extern alClockP erio d() Equat ion5 376 Ex ternalC lockPer iod() Equat ion6 Exter nalCloc kPeriod Equat ion7 1880 Ex terna lClockPe rio d() Equati on8 5 Externa lClockPe rio d()

Page 21 Voice Recording & Playback Device Figure 18 Bond Pad Layout and Coordinates Table 7 Coordinate Information Pad Number Pad Name X Coordinate Y Coordinate

1 NC 5149 2069

3 DI 5149 1243

4 DO 5149 901

5 VSSD 5149 610

6 VSSD 5149 383

7 NC 4795 108

8 NC 4412 108

9 ANAOUT- 560 108

10 ANAOUT+ 108 288

12 VSSA 108 655

13 VSSA 108 827

14 VSSA 108 1113

15 AUDOUT 108 1426

16 SQLCAP 108 1834

18 ANAIN- 108 2795

19 ANAIN+ 108 3066

20 VCCA 108 3397

21 VCCA 108 3627

X Coordinate Y Coordinate

22 NC 248 4106

24 VSSA 4314 4106

25 VSSA 4486 4106

26 VSSA 4658 4106

27 SAC 4906 4106

29 EXTCLK 5149 3478

30 VCCD 5149 2992

31 VCCD 5149 2760

32 VCCD 5149 2588

33 SCLK 5149 2362

DIE SIZE : 4340µm x 5380µm PAD SIZE : 100µm x 100µm DIE THICKNESS : Approximately 25 mils

9 ANAOUT

10 ANAOUT+11 /

12 VSSA

13 VSSA

14 VSSA

15 AUDOUT

16 SQLCAP

18 ANAIN-

19 ANAIN+

20 VCCA

21 VCCA

/CS 2 NC 1 SCLK 33 VCCD 32 VCCD 31 VCCD 30 EXTCLK 29 /INT 28 SAC 27 VSSA 26VSSA 25VSSA 24 X CoordinateOrigin Y Coordinate Connect substrate to ground. /CS 2 NC 1 SCLK 33 VCCD 32 VCCD 31 VCCD 30 EXTCLK 29 /INT 28 SAC 27 VSSA 26VSSA 25VSSA 24 X CoordinateOrigin Y Coordinate /CS 2 NC 1 SCLK 33 VCCD 32 VCCD 31 VCCD 30 EXTCLK 29 /INT 28 SAC 27 VSSA 26VSSA 25VSSA 24 X CoordinateOrigin Y Coordinate Connect substrate to ground.

Page 22 Voice Recording & Playback Device

APR6008 SOP Pin-out Diagram