APE17024

APEXX24 APLUS | Alldatasheet

Document overview

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Technical content

APLUS MAKE YOUR PRODUCTION A-PLUS APExx24 Series DATA SHEET APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115)台北市南港區成功路㆒段32 號 3 樓之 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw Sales E-mail: sales@aplusinc.com.tw Technology E-mail: service@aplusinc.com.tw

Rev 1.1 2003/9/2 1

1.0 General Description

The APExx24 series are very low cost voice and melody synthesizer with 4-bits CPU. They have various features including 4-bits ALU, ROM, RAM, I/O ports, timers, clock generator, voice and melody synthesizer, and PWM (Direct drive) or D/A current outputs, etc. The audio synthesizer contains one voice-channel and two melody-channels. Furthermore, they consist of 27 instructions in these devices. With CMOS technology and halt function can minimize power dissipation. Their architectures are similar to RISC, with two stages of instruction pipeline. They allow all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles).

2.0 Features

(1) Single power supply can operate from 2.4V to 5.5V at 4MHz or 8MHz. (2) Program ROM: 64k x 10 bits (3) 1 set of 16-bits DPR can access up to 64k x 10 bits melody data memory space, and 1 set of 20-bits VPR can access up to 1024k x 10 bits voice data memory space. Product Voice Duration (sec) Voice Pointer (VPR) ROM Size (10-bits) APE12724 127 19-bits 384k APE17024 170 19-bits 512k APE25524 255 20-bits 768k APE34024 340 20-bits 1024k (4) Data Registers: a). 128 x 4-bits data RAM (00-7Fh) b). Unbanked special function registers (SFR) range: 00h-2Fh (5) I/O Ports: a). PRA: 4-bits I/O Port A (10h) can be programmed to input/output individually. (Register control) b). PRB: 4-bits I/O Port B (13h) can be configured to input/output individually. (Mask option) c). PRC: 4-bits I/O Port C (14h) can be programmed to input/output individually. (Register control) d). PRD: 4-bits I/O Port D (15h) can be programmed to input/output individually. (Register control) e). PRE: 4-bits I/O Port E (17h) can be programmed to input/output individually. (Register control) f). PRF: 4-bits I/O Port F (18h) can be programmed to input/output individually. (Register control) (6) On-chip clock generator: Resistive Clock Drive (RM) or Crystal oscillator (HM) (7) Timer: 1-set Voice Interrupt (Timer0: a 9-bits auto-reload timer/counter). (8) Stack: 2-level subroutine nesting. (9) Built-in 4 Level Volume Control can be programmed. (10) Built-in 8 Level DAC Current Control can be configured. (Mask option) (11) Built-in IR Carry Output: Port B[1] can be configured as IR pin by 38k / 56kHz. (Mask option)

Rev 1.1 2003/9/2 2 (12) External Reset: Port B[3] can be configured as reset pin. (Mask opton) (13) HALT and Release from HALT function to reduce power consumption (14) Watch Dog Timer ( WDT) (15) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles (16) Number of instruction: 27 (17) DAC: 1 channel voice and dual tone melody synthesizer (One 9-bits Cout or 8-bits PWM output). FIGURE 1 : ROM Map of APExx24 Series 16-bit x 2 STACK Reset Vector 00000h-0FFFFh 16-bit Data Pointer PC[15:0] Reserved for Testing 000FFh-00400h 00401h 00000h 000FEh Program ROM 00000h-0FFFFh Data ROM for Melody 20-bit Voice Pointer 00000h-FFFFFh Voice ROM for Voice

Rev 1.1 2003/9/2 3

3.0 Pin Description

Pad Name Pin Attr. Description PWM2/Cout O PWM2 output, or Current Output of Audio. PWM1 O PWM1 output. Vdd1~3 Power Power supply during operation. PRA0~3 PRC0~3 PRD0~3 PRE0~3 PRF0~3 I/O I/O port can be programmed to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. PRB0 / OSC2 I/O I/O port can be configured to input/output individually or HM OSC pad. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. PRB1 / IR I/O I/O port can be configured to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. Mask option selected as an IR Carrier Output with 38k / 56kHz PRB2 I/O I/O port can be configured to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. PRB3 / Reset I/O I/O port can be configured to input/output individually. Input type with weak pull-low or fix-input-floating capability. Buffer Output type. Mask option selected as an external RESET pin with weak pull-low capability. OSC1 I RM/HM mode Oscillator input GND1~4 Power Ground Potential

4.0 DC Characteristics

Symbol Parameter Vdd Min. Typ. Max. Unit Condition Vdd Operating voltage 2.4 3 5.5 V depending on Freq. 3 1 Isb Standby 4.5 1 uA 4MHz, RM, in HALT Mode 3 2 Iop Supply current Operating 4.5 7 mA 4MHz, RM, IO Floating 3 3 Iih Input current (Internal pull low) 4.5 10 uA Input ports with weak pull-low 3 -3 Ioh Output-high current 4.5 -10 3 7 Iol Output-low current 4.5 19 mA 4MHz, RM (IO ports) 3 0.8 ~ 4.8 Cout DAC output current (8-level option) 4.5 0.9 ~ 6.5 mA 4MHz, RM (Full scale) dF/F Frequency stability -5 5 % Fosc(3v- 2.4v) Fosc (3v) dF/F Fosc lot variation -10 10 % Vdd=3V, Rosc=180k, 4MHz

Rev 1.1 2003/9/2 4 FIGURE 2 : Frequency vs. Rosc (at 3V) Resistor (Rosc ohms) 110k 200k 300k 430k Frequency (MHz) 14.84 8.25 5.54 3.92

5.0 Application Circuit

Rosc vs Freq. 5.54 3.92 8.25 14.84 0 100 200 300 400 500 Rosc (k ohm) Freq. (MHz)

Rev 1.1 2003/9/2 5

6.0 Bonding Diagram of APE12724 / APE17024

Pad # Pad Name X Y Pad # Pad Name X Y

1 GND4 75 404 18 GND1 2033 2688

2 GND3 57 293 19 PRC1 1920 2688

3 PWM1 56 145 20 PRC2 1807 2688

4 Vdd3 183 60 21 PRC3 1694 2688

5 PWM2/Cout 467 58 22 PRD0 1581 2688

6 Vdd2 988 86 23 PRD1 1468 2688

7 OSC1 1106 86 24 PRD2 1355 2688

8 PRB0/OSC2 1224 86 25 PRD3 1242 2688

9 PRB1/IR 1342 86 26 PRE0 1129 2688

10 PRB2 1460 86 27 PRE1 1016 2688

11 PRB3/Reset 1578 86 28 PRE2 903 2688

12 PRA0 1696 86 29 PRE3 790 2688

13 PRA1 1814 86 30 PRF0 676 2688

14 PRA2 1932 86 31 PRF1 563 2688

15 PRA3 2050 86 32 PRF2 450 2688

16 PRC0 2168 86 33 PRF3 337 2688

17 GND2 2160 230 34 Vdd1 223 2688

6 7 8 9 10 13 11 12 14 15 16 PRE0 OSC1 Vdd2 GND2 PRB2 PRB1 PRB0 PRB3 PRA3 PRA2 PRA1 PRA0 GND3 PWM2/Cout GND4 1 Chip Size : 2330 um x 2860um Pad Size : 80 um x 80 um * The IC substrate must be connected to GND. PWM1 Vdd3 19 20 PRD2 PRD3 (0,0) 28 27 26 25 24 23 22 18 33 32 31 30 29 34 PRC0 GND1 PRD0 PRE1 PRC3 PRC2 PRC1 Vdd1 PRF3 PRF2 PRF1 PRF0 PRE3 PRE2

Rev 1.1 2003/9/2 6

6.2 Bonding Diagram of APE25524 / APE34024

Pad # Pad Name X Y Pad # Pad Name X Y

1 GND4 75 404 18 GND1 2033 4508

2 GND3 58 293 19 PRC1 1920 4508

3 PWM1 56 145 20 PRC2 1807 4508

4 Vdd3 183 60 21 PRC3 1694 4508

5 PWM2/Cout 467 58 22 PRD0 1581 4508

6 Vdd2 988 86 23 PRD1 1468 4508

7 OSC1 1106 86 24 PRD2 1355 4508

8 PRB0/OSC2 1224 86 25 PRD3 1242 4508

9 PRB1/IR 1342 86 26 PRE0 1129 4508

10 PRB2 1460 86 27 PRE1 1016 4508

11 PRB3/Reset 1578 86 28 PRE2 903 4508

12 PRA0 1696 86 29 PRE3 790 4508

13 PRA1 1814 86 30 PRF0 676 4508

14 PRA2 1932 86 31 PRF1 563 4508

15 PRA3 2050 86 32 PRF2 450 4508

16 PRC0 2168 86 33 PRF3 337 4508

17 GND2 2160 230 34 Vdd1 223 4508

6 7 8 9 10 13 11 12 14 15 16 PRE0 OSC1 Vdd2 GND2 PRB2 PRB1 PRB0 PRB3 PRA3 PRA2 PRA1 PRA0 GND3 PWM2/Cout GND4 1 Chip Size : 2330 um x 4680 um Pad Size : 80 um x 80 um * The IC substrate must be connected to GND. PWM1 Vdd3 19 20 PRD2 PRD3 (0,0) 28 27 26 25 24 23 22 18 33 32 31 30 29 34 PRC0 GND1 PRD0 PRE1 PRC3 PRC2 PRC1 Vdd1 PRF3 PRF2 PRF1 PRF0 PRE3 PRE2