AP160F

AP160 AMICC | Alldatasheet

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8-BIT MICROCONTROLLER DATA SHEET WITH 8KB OTP October 2001 Version 0.0 1 AMIC Technology, Inc. GENERAL DESCRIPTION The AP160 is a wide operating voltage, Low power consumption and high performance with AMIC high -density CMOS technology. All instruction set of AP160 are fully compatible with the standard 8051. The AP160 contains 8K bytes OTP EPROM, 256 bytes RAM, four 8-bit bi-directional and bit addressable I/O ports, three 16 -bit timer/counter and eight interrupt sources. To reduce power consumption, idle mode and power down mode are provided to implementation. For data protection, program lock bits can be performed through programming LB1, LB2 and LB3. The AMIC AP160 is a useful and powerful microcontroller in many control system application.

FEATURES

l Compatible with MCS-51 Products l 256 X 8 bit internal Data RAM. l 8KB On-Chip OTP EPROM. l 2.7V~5.5V Operating Range. l Fully Static Operation : 0Hz to 16 MHz l 0~33MHZ speed range at VCC=5V. l 32 Programmable I/O pins l Three 16-Bit Timers/Counters. l Programmable clock out. l Full-duplex UART l Eight interrupt sources. l 2 level priority-interrupt. l Power reduction control modes n Idle mode n Power-down mode l 3 security bits. l Low EMI (Inhibit ALE) l Wake-up from Power Down by an external interrupt. l Available in PLCC and QFP44 packages.

Version 0.0 2 AMIC Technology, Inc. PIN CONFIGURATIONS n PLCC AP160L P1.5 P1.4 P1.3 P1.2 P1.1 (T2EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 (WR) P3.6 n QFP AP160F P1.5 P1.4 P1.3 P1.2 P1.1 (T2EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4

Version 0.0 3 AMIC Technology, Inc. BLOCK DIAGRAM PORT 0 DRIVERS PORT 2 DRIVERS RAM ADDR. REGISTER RAM PORT0 LATACH PORT2 LATACH QUICK FLASH PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNER DPTR B REGISTER ACC STACK POINTER TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT1 LATACH PORT3 LATACH TIMING AND CONTROL INSTRUCTION REGISTER OSC PORT 1 DRIVERS PORT 3 DRIVERS VCC GND PSEN PROGALE/ /VPPEA RST

Version 0.0 4 AMIC Technology, Inc. PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTIONS VSS I Ground. VCC I Supply voltage. P0.0-P0.7 I/O Port 0 is an 8-bit open drain, bidirectional I/O port. When 1s are written to port 0 pins, the pins can be used as high -impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memo ry. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during programming on -chip OTP EPROM and outputs the code bytes during program verification. External pullups are required during program verification. P1.0-P1.7 I/O Port 1 is an 8 -bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are ex ternally being pulled low will source current ( ILI ) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following: T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock -Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control. Port 1 also receives the low -order address bytes during program ming on -chip OTP EPROM and verification. P2.0-P2.7 I/O Port 2 is an 8 -bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pul lups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current ( ILI ) because of the internal pullups. Port 2 emits the high -order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8 -bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during programming on -chip OTP EPROM and verification. P3.0-P3.7 I/O Port 3 is an 8 -bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current ( ILI ) because of the pullups. Port 3 also serves the functions of various special features of the AP160, as shown below: RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 3 also receives some control signals for programming and verification. RST I Reset input. A h igh on this pin for two machine cycles while the oscillator is running resets the device.

Version 0.0 5 AMIC Technology, Inc. SYMBOL TYPE DESCRIPTIONS ALE/PROG O/I Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Programming on-chip OPT EPROM. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE puls e is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setti ng the ALE -disable bit has no effect if the microcontroller is in external execution mode. PSEN O Program Store Enable is the read strobe to external program memory. When the AP160 is executing code from external program memory, PSEN is activated twice ea ch machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/Vpp I External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations start ing at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12 -volt programming enable voltage (VPP) during programming OTP EPROM. XTAL1 I Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 O Output from the inverting oscillator amplifier.

Version 0.0 6 AMIC Technology, Inc. A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Table 1. AP160 SFR Map and Reset Values features. In that case the reset or inactive values of the new bits will always be 0.

Version 0.0 7 AMIC Technology, Inc. counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Table 2. T2CON – Timer/Counter 2 Control Register either RCLK = 1 or TCLK = 1. serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. Table 3. Timer 2 Operating Modes

1 X 1 Baud Rate Generator

Counter function, the register is incremented in response to a 1 -to-0 transition at its corresponding external input pin, T2. In this function, the external input is samples show a high in on e cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. held for at least one full machine cycle.

Version 0.0 9 AMIC Technology, Inc. RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software. Table 3. T2MOD (Timer 2 Mode Control Register) T2OE Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter. Figure 3. Timer 2 Auto Reload Mode (DCEN=1)

Version 0.0 10 AMIC Technology, Inc. determined by Timer 2’s overflow rate according to the following equation.

2 RateOverflowTimer

state time (at 1/2 the oscillator frequency). The baud rate formula is given below. where (RCAP2H,RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. turned off (clear TR2) before accessing the timer 2 or RCAP2 register. Figure 4. Timer 2 in Baud Rate Generator Mode

Version 0.0 11 AMIC Technology, Inc. (RCAP2H, RCAP2L), as shown in the following equation. Figure 5. Timer 2 in Clock-Out Mode

Version 0.0 12 AMIC Technology, Inc. at S2P2 and is polled in the same cycle in which the timer overflows. Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. source is individually enabled or disabled by setting or clearing its enable bit. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. Figure 6. Interrupt Sources

Version 0.0 13 AMIC Technology, Inc. DATA MEMORY The AP160 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail -able as stack space. POWER MANAGEMENT IDLE MODE In idle mode, the CPU puts itself to sleep while all the on -chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. POWER DOWN MODE In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The way to exit from power down mode is either hardware reset or external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Status of External Pins During Idle and Power Down Modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. REDUCED EMI All port pins of the AP160 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times. AUXR Address = 8EH Bit 7 6 5 4 3 2 1 0 - - - - - - - AO NOTE: The AO bit (AUXR.0) in the AUXR register when set disables the ALE output.

Version 0.0 14 AMIC Technology, Inc. table 8. The programming and verification waveform is shown in Figure 9. VCC must be rising to VCC1 during Figure 7. Programming the EPROM MEMORY Figure 8. Verifying the EPROM MEMORY.

Version 0.0 15 AMIC Technology, Inc. Table 8. EPROM PROGRAMMING MODE (30H) = 37H indicates manufactured by AMIC. (31H) = 6EH indicates embedded OTP device. (32H) = 7FH indicates JEDEC continuation code.

Version 0.0 16 AMIC Technology, Inc. PROGRAM MEMORY LOCK BITS The AP160 has three lock bits that can be left unprogrammed(U) or can be programmed (P) to obtain the additional features listed in the following table. Program Lock Bits LB1 LB2 LB3 Protection Type

1 U U U No program lock features

2 P U U MOVC instructions executed from external program memory are disabled from fetching

code bytes from internal memory, EA is sampled and latched on reset, and further programming of the OPT EPROM is disabled. 3 P P U Same as mode 2, but verify is also disabled. 4 P P P Same as mode 3, bur external execution is also disabled. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pi ns can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external cloc k signal, because the input to the internal clock circuitry is through a divide -by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.

Version 0.0 17 AMIC Technology, Inc. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Operating temperature under bias -55 to +125 °C Storage temperature range -65 to +150 °C Voltage on EA/V PP pin to V SS 0 to +12.5 V Voltage on any other pin to V SS -0.1 to +7.0 V Maximum Operating Voltage 6.0 V Maximum I OL per I/O pin 15.0 mA NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This This is a stress rating only and functional operation of the device at these or any other conditions beyo nd those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC CHARACTERICSTICS The values shown in this table are valid for T A = -40°C to 85°C and V CC = 2.7V to 5.5V, unless otherwise noted. Symbol Parameter Condition Min Max Units ILV Input Low Voltage (Except EA) -0.5 0.2 VCC-0.1 V IL1V Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V IHV Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V IH1V Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V OLV Output Low Voltage (Ports 1,2,3) OLI = 1.6mA 0.45 V OL1V Output Low Voltage (Port 0, ALE, PSEN) OLI = 3.2mA 0.45 V OHI =-60uA, VCC=5V±10% 2.4 V OHI =-25uA 0.75 VCC V OHV Output High Voltage (Port 1,2,3, ALE, PSEN) OHI =-10uA 0.9 VCC V OHI =-800uA, VCC=5V±10% 2.4 V OHI =-300uA 0.75 VCC V OH1V Output High Voltage (Port 0 in External Bus Mode) OHI =-80uA 0.9 VCC V ILI Logical 0 Input Current (Ports 1,2,3) INV =0.45V -50 uA TLI Logical 1 to 0 Transition Current (Ports 1,2,3) INV =2V, VCC=5V±10% -650 uA LII Input Leakage Current (Port 0, EA) 0.45< INV < VCC ±10 uA RRST Reset Pulldown Resistor 50 300 KΩ IOC Pin Capacitance Test Freq. =1 MHZ, AT =25°C 10 PF Active Mode, 12 MHZ 25 mA Power Supply Current Idle Mode, 12MHZ 6.5 mA VCC = 5.5V 100 uA CCI Power Down Mode VCC = 3V 40 uA Notes: 1. Under steady state (non-transient) conditions, OLI must be externally limited as follows: Maximum OLI per port pin: 10mA Maximum OLI per 8-biit port: Port 0: 26mA, Ports 1,2,3: 15mA Maximum total OLI for all output pins: 71mA If OLI exceeds the test condition, OLV may exceed the related specification. Pins are not guaranteed to sink currenr greater than the listed test condition. 2. Minimum VCC for Power Down is 2V.

Version 0.0 18 AMIC Technology, Inc. AC CHARACTERISTICS Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS 12MHZ Oscillator Variable Oscillator Symbol Parameter Min Max Min Max Units CLCL1/t Oscillator Frequency 0 16 MHZ LHLLt ALE Pulse Width 127 2 CLCLt -40 ns AVLLt Address Valid to ALE Low 43 CLCLt -40 ns LLAXt Address Hold After ALE Low 48 CLCLt -35 ns LLIVt ALE Low to Valid Instruction In 233 4 CLCLt -100 ns LLPLt ALE Low to PSEN Low 43 CLCLt -40 ns PLPHt PSEN Pulse Width 205 3 CLCLt -45 ns PLIVt PSEN Low to Valid Instruction In 145 3 CLCLt -105 ns PXIXt Input Instruction Hold After PSEN 0 0 ns PXIZt Input Instruction Float After PSEN 59 CLCLt -25 ns PXAVt PSEN to Address Valid 75 CLCLt -8 ns AVIVt Address to Valid Instruction In 312 5 CLCLt -105 ns PLAZt PSEN Low to Address Float 10 10 ns RLRHt RD Pulse Width 400 6 CLCLt -100 ns WLWHt WR Pulse Width 400 6 CLCLt -100 ns RLDVt RD Low to Valid Data In 252 5 CLCLt -165 ns RHDXt Data Hold After RD 0 0 ns RHDZt Data Float After RD 97 2 CLCLt -70 ns LLDVt ALE Low to Valid Data In 517 8 CLCLt -150 ns AVDVt Address to Valid Data In 585 9 CLCLt -165 ns LLWLt ALE Low to RD or WR Low 200 300 3 CLCLt -50 3 CLCLt +50 ns AVWLt Address to RD or WR Low 203 4 CLCLt -130 ns QVWXt Data Valid to WR Transition 33 CLCLt -50 ns QVWHt Data Valid to WR High 433 7 CLCLt -150 ns WHQXt Data Hold After WR 33 CLCLt -50 ns RLAZt RD low to Address Float 0 0 ns WHLHt RD or WR High to ALE High 43 123 CLCLt -40 CLCLt +40 ns

Version 0.0 19 AMIC Technology, Inc. External Program Memory Read Cycle A8-A15 ALE tLHLL tAVLL tLLPL tPLPH tPLIV tPLAZ tLLAX tPXAV tPXIZ tPXIX tAVIV A8-A15 A0-A7INSTR IN PSEN PORT 0 PORT 2 tLLIV A0-A7 External Data Memory Read Cycle ALE tLHLL tWHLH DATA IN PSEN PORT 0 PORT 2 tRLRH tLLDV tLLWL RD tLLAX tAVLL tRLDV tRHDX tRHDZ tRLAZ tAVWL tAVDV A0-A7 FROM RI OR DPL A0-A7 FROM PCL INSTR IN P2.0-P2.7 OR A8-A15 FORM DPH A8-A15 FROM PCH

Version 0.0 20 AMIC Technology, Inc. EXTERNAL CLOCK DRIVE WAVEFORMS 0.45V VCC-0.5V

0.7 VCC

0.2 VCC-0.1V tCHCX tCLCX tCLCL tCLCH tCHCL tCHCX EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/ CLCLt Oscillator Frequency 0 16 MHZ CLCLt Clock Period 62.5 ns CHCXt High Time 20 ns CLCXt Low Time 20 ns CLCHt Rise Time 20 ns CHCLt Fall time 20 ns

Version 0.0 21 AMIC Technology, Inc. SERIAL PORT TIMING: SHIFT REGISTER MODE TEST CONDITIONS The values in this table are valid for VCC = 2.7V to 5.5V and Load Capacitance = 80pF 12MHZ Osc Variable Oscillator Symbol Parameter Min Max Min Max Units XLXLt Serial Port Clock Cycle Time 1.0 12 CLCLt ns QVXHt Output Data Setup to Clock Rising Edge 700 10 CLCLt -133 ns XHQXt Output Data Hold After Clock Rising Edge 50 2 CLCLt -117 ns XHDXt Input Data Hold After Clock Rising Edge 0 0 ns XHDVt Clock Rising Edge to Input Data Valid 700 10 CLCLt -133 ns SHIFT REGISTER MODE TIMING WAVEFORMS 0 1 2 3 4 5 6 7 8INSTRUCTION tXLXL tQVXH tXHQX tXHDV tXHDX VALID VALID VALID VALID VALID VALID VALID VALID 0 1 2 3 4 5 6 7 SET TI SET RI ALE CLOCK OUTPUT DATA INPUT DATA WRITE TO SBUF CLEAR RI AC TESTING INPUT/OUTPUT WAVEFORMS VCC-0.5V 0.45V 0.2 VCC + 0.9V TEST POINTS 0.2 VCC - 0.1V Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V IH min. for a logic 1 and V IL max. for a logic 0. FLOAT WAVEFORMS TIMING REFERENCE POINTS VLOAD + 0.1V VLOAD - 0.1V VLOAD VOL - 0.1V VOL + 0.1V Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V OH /VOL level occurs.

Version 0.0 22 AMIC Technology, Inc.

ORDERING INFORMATION

AP160L PLCC -40°C ~ +85°C AP160F QFP -40°C ~ +85°C NOTE : AMIC Technology, Inc. reserves the right to make changes without prior notice.

Version 0.0 23 AMIC Technology, Inc.

Package Information

PLCC 44L Outline Dimension unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. HD D 18 28 E HE 44 40 A1 A2 A e GD Seating Plane b1 b 0.150 REF0.020 MIN L 0.630/0.590 0.050 REF 0.022/0.016 0.032/0.026 GE C 0.630/0.590 0.014/0.0008 D 0.004 y

Version 0.0 24 AMIC Technology, Inc. QFP 44L Outline Dimensions unit: inches/mm be A A2A1 D0.10 See Detail A L 1.6 DETAIL A θ 12 22 3444 E D C 0.25 Gauge Plane Seating Plane 0.20 min min0° Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max b 0.012 TYP 0.3 TYP e 0.0315 TYP 0.80 TYP θ 0° - 7° 0° - 7° Notes: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Dimension b does not include dambar protrusion.

Version 0.0 25 AMIC Technology, Inc. Corporation Headquarters 6F, No. 5, Li-Shin Road VI, Hsin Chu, HSIP, Taiwan, R.O.C. Tel : 886-3-567-9966 Fax : 886-3-567-9977 Web : www.amic.com.tw ASIA Pacific AMIC Technology, Inc. 17F-8, No. 77, Shin Tai Wu Road, Shi Chi, Taipei, Taiwan, R.O.C. Tel : 886-2-2698-1131 Fax : 886-2-2698-1030 Europe AMIC Technology (EUROPE) B.V. Crown Point Building, De Paal 1-6,13351 JA, P.O Box 50053,1305 AB, Almere, The Netherlands Tel. +31-36-5359666 Fax. +31-36-5401888 US and Canada AMIC Technology Inc. 2518 Mission College Blvd., Suite 102 Santa Clara, CA 95054, U.S.A. Tel. +408-988-8818 Fax. +408-988-8817 Copyright © 2001 AMIC Technology, Inc. Specification subject to change without notice. All rights reserved.