AP1270 A-POWER | Alldatasheet
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Electronics Corp. 3A SINK/SOURCE BUS TERMINATION REGULATOR FEATURES DESCRIPTIOON Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink and Source 3A Continuous Current Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL_18, HSTL, SCSI-2 and SCSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in TO-252-5L & ESOP-8 Packages V IN and VCNTL No Power Sequence Issue RoHS Compliant and 100% Lead (Pb)-Free APPLICATION Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems Data and specifications subject to change without notice 201011055 AP1270 TYPICAL APPLICATION The AP1270 is a simple, cost-effective and high- speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 3A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2V DDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The AP1270 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AP1270 are available in the TO-252-5L & ESOP-8 (Exposed Pad) surface mount packages. R1 = R2 = 100KΩ, RTT = 50Ω / 33Ω / 25Ω COUT,min = 10uF (Ceramic) + 1000uF under the worst case testing condition CSS = 1µF, CIN = 470µF(Low ESR), CCNTL = 47µF VIN VCNTL REFEN VOUT GND RTT EN VIN=2.5V/1.8V/1.5V VCNTL=3.3V CSS CIN COUT CCNTL 2N7002 AP1270 RDUMMY
Electronics Corp. AP1270 ABSOLUTE MAXIMUM RATINGS(Note1) ESOP-8 28°C/W TO-252-5L 6°C/W Note1 : Exceeding the absolute maximum rating may damage the device. OPERATING RATING(Note2) Note2 : The device is not guaranteed to function outside its operating conditions. ORDERING / PACKAGE INFORMATION (VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10uF(Ceramic), TA =25oC, unless otherwise specified) Parameter SYM TEST CONDITION MIN TYP MAX UNITS VCNTL Operation Current ICNTL IOUT = 0A - 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown), RLOAD = 180Ω - 50 90 uA Output Offset Voltage(Note3) VOS IOUT = 0A -20 - 20 IOUT = 10mA ~ 3A -20 - 20 IOUT = -10mA ~ -3A -20 - 20 Current Limit ILIM 3.2 - - A Thermal Shutdown Temperature T SD 3.3V < VCNTL < 5V 130 160 - Thermal Shutdown Hysteresis ΔTSD 3.3V < VCNTL < 5V - 30 - VIH Enable 0.65 - - VIL Shutdown - - 0.2 Note3. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note4. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 3A. Thermal Resistance from Junction to Case (Rthjc) ELECTRICAL SPECIFICATIONS Input Output (DDR / DDRII / DDRIII) Load Regulation(Note4) ΔVLoad mV Protection oC REFEN Shutdown Shutdown Threshold V ( Top View) REFEN ESOP-8 NC NCGND VIN NC VCNTL VOUT GND Rthja = 75oC/W AP1270X-HF MP : ESOP-8 Halogen-Free H : TO-252-5L TO-252-5L 1V I N 4V R E F E N 3V C N T L 2G N D 5V O U T ( Top View ) (S i d e V i e w) Metal Tab VCNTL Rthja = 40oC/W
Electronics Corp. AP1270 PIN DESCRIPTIONS PIN SYMBOL PIN DESCRIPTION VIN Power Input Voltage. GND Ground Pin VOUT Output Voltage VCNTL Gate Drive Voltage REFEN Reference Voltage Input and Chip Enable BLOCK DIAGRAM
APPLICATION INFORMATION
Input Capacitor and Layout Consideration EA Current Limit Thermal Protection REFEN VOUT VINVCNTL Place the input bypass capacitor as close as possible to the AP1270. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1270 and the preceding powe converter.
Electronics Corp. AP1270 Consideration while designs the resistance of voltage divider Thermal Consideration Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. AP1270MP regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125oC. The power dissipation definition in device is: P D = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( TJ(MAX) -TA ) / Rthja Where TJ(MAX) is the maximum operation junction temperature 125oC, TA is the ambient temperature and the Rthja is the junction to ambient thermal resistance. The junction to ambient thermal resistance (Rthja is layout dependent) for ESOP-8 package (Exposed Pad) is 75oC/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25oC can be calculated by following formula: P D(MAX) = (125oC - 25oC) / 75oC/W = 1.33W The thermal resistance Rthja of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow.
Electronics Corp. AP1270 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 1.8V, VCNTL = 3.3V, IOUT = 0A, Source test V IN = 1.8V, VCNTL = 3.3V, IOUT = 10mA, Source test IOUT = 0A, Source test Load Transient (Source test) Load Transient (Sink test) VIN = 1.8V, VCNTL = 3.3V V IN = 1.8V, VCNTL = 3.3V VREF = 0.9V Supplied by a regulatorVREF = 0.9V Supplied by a regulator IOUT = 0A, Source test VIN VOUT IOUT VIN VOUT IOUT Output Voltage vs. Temperature 0.7 0.8 0.9 1.1 -50 -25 0 25 50 75 100 125 Temperature (oC) Output Voltage (V) Shutdown Threshold vs. Temperature 0.25 0.3 0.35 0.4 0.45 0.5 0.55 -50 -25 0 25 50 75 100 125 Temperature (oC) Shutdown Threshold (V) Turn On Turn Off VIN Current vs. Temperature -50 -25 0 25 50 75 100 125 Temperature (oC) VIN Current (uA) VCNTL Current vs. Temperature 1.5 2.5 3.5 -50 -25 0 25 50 75 100 125 Temperature (oC) VCNTL Current (mA) VIN=1.8V, VCNTL=5V VIN=1.8V, VCNTL=5V VIN=1.8V, VCNTL=3.3V VIN=1.5V, VCNTL=5V VIN=1.5V, VCNTL=3.3V VIN=1.8V, VCNTL=3.3V
Electronics Corp. AP1270 TYPICAL PERFORMANCE CHARACTERISTICS Source Current Limit vs. Temperature 4.5 5.5 -50 -25 0 25 50 75 100 125 Temperature (oC) Source Current Limit (A) Sink Current Limit vs. Temperature 3.5 4.5 5.5 -50 -25 0 25 50 75 100 125 Temperature (oC) Sink Current Limit (A) VIN=1.8V, VCNTL=3.3V VIN=1.8V, VCNTL=5V VIN=1.8V, VCNTL=3.3V VIN=1.8V, VCNTL=5V
Electronics Corp. AP1270 MARKING INFORMATION ESOP-8 TO-252-5L 1270MP YWWSSS Part Number Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence Package Code Part Number Package Code 1270H YWWSSS Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence LOGO