AP1250CMP A-POWER | Alldatasheet
Document overview
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Technical content
Features
¾ Ideal for DDR-I, DDR-II and DDR-III VTT Applications ¾ Sink and Source 2A Continuous Current ¾ Integrated Power MOSFETs ¾ Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces. ¾ High Accuracy Output Voltage at Full-Load ¾ Output Adjustment by Two External Resistors ¾ Low External Component Count ¾ Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output ¾ Current Limiting Protection ¾ On-Chip Thermal Protection ¾ Available in ESOP-8 (Exposed Pad) Packages ¾ V IN and VCNTL No Power Sequence Issue ¾ RoHS Compliant and 100% Lead (Pb)-Free Pin Configuration Application ¾ Desktop PCs, Notebooks, and Workstations ¾ Graphics Card Memory Termination ¾ Set Top Boxes, Digital TVs, Printers ¾ Embedded Systems ¾ Active Termination Buses ¾ DDR-I, DDR-II and DDR-III Memory Systems Block Diagram Pin Description Pin Name Pin function VIN Power Input GND Ground VCNTL Gate Drive Voltage REFEN Reference Voltage input and Chip Enab le VOUT Output Voltage Advanced Power Electronics Corp. AP1250CMP 2A Sink/Source Bus Termination Regulator 200901074 GND VOUT VIN REFEN NC VCNTL NC NC ESOP-8 (MP) (Top View) GND
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units Input VCNTL Operation Current ICNTL IOUT=0A -- 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown),RLOAD = 180Ω -- 50 90 µA Output (DDR / DDR II / DDR III) Output Offset Voltage(3) VOS IOUT= 0A -20 -- +20 IOUT= +2A Load Regulation(4) ΔVLOAD IOUT= -2A -20 -- +20 mV Protection Current limit ILIM 2.2 -- -- A Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V 125 170 -- Thermal Shutdown Hysteresis ΔTSD 3.3V ≤ VCNTL ≤ 5V -- 35 -- REFEN Shutdown VIH Enable 0.6 -- -- Shutdown Threshold VIL Shutdown -- -- 0.2 V Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. AP1250CMP Advanced Power Electronics Corp. Absolute Maximum Rating (1) Parameter Sy mbol Value Unit Input Voltage VIN 6 V Control Voltage VCNTL 6 V Power Dissipation PD Internally Limited -- Storage Temperature Range TS -65 to 150 °C Lead Temperature (Soldering, 5 sec.) TLEAD 260 °C Package Thermal Resistance ΘJC 28 ºC/W Operating Rating(2) Parameter Sy mbol Value Units Input Voltage VIN 2.5 to 1.5 ±3% V Control Voltage VCNTL 5.5 or 3.3 ±5% V Ambient Temperature TA -40 to +85 ℃ Junction Temperature TJ -40 to +125 ℃
Application Information
Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the AP1250CMP. A low ESR capacito r larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1250CMP and the preceding powe r converter. Consideration while designs the resistance o f voltage divider Make sure the sinking current capability o f pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. Thermal Consideration AP1250CMP regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do no t exceed maximum operation junction temperature 125℃. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( TJ(MAX) -TA ) /ΘJA Where T J(MAX) is the maximum operation junction temperature 125℃, TA is the ambient temperature and the ΘJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance ( Θ JA is layout dependent) for ESOP-8 package (Exposed Pad) is 75 ℃/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25℃ can be calculated by following formula: The thermal resistanceΘ JA of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. AP1250CMP Advanced Power Electronics Corp.
R1 = R2 = 100KΩ, RTT = 50Ω/33Ω/25Ω COUT, min = 10µF (Ceramic) + 1000µF under the worst case testing condition CSS = 1µF, CIN = 470µF(Low ESR), CCNTL = 47µF AP1250CMP Advanced Power Electronics Corp.
Package Outline : ESOP-8 Millimeters SYMBOLS MIN NOM MAX A 5.80 6.00 6.20 B 4.80 4.90 5.00 C 3.80 3.90 4.00 D 0 °4 °8 ° E 0.40 0.65 0.90 F 0.19 0.22 0.25 M 0.00 0.08 0.15 0.35 0.42 0.49 L 1.35 1.55 1.75 J K G 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : ESOP-8 1.27 TYP. H ADVANCED POWER ELECTRONICS CORP. 0.375 REF. 45° J L 1250CMP YWWSSS Package Code Part Number Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence G H 5678 C A B I NOTES:Thermal Pad Dimemsions 2.25 ±0.1