AP1210MP

AP1210MP A-POWER | Alldatasheet

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Electronics Corp. 2.5A SINK/SOURCE BUS TERMINATION REGULATOR FEATURES DESCRIPTIOON Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink and Source up to 2.5Amp Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL_18, HSTL, SCSI-2 and SCSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Built-in Soft-start Function Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in ESOP-8 (Exposed Pad) Packages V IN and VCNTL Under Voltage Protection RoHS Compliant and Halogen Free APPLICATION Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems Data and specifications subject to change without notice 20141009V2 AP1210MP TYPICAL APPLICATION The AP1210MP is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2.5A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2V DDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The AP1210MP also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection.Built-in softstart function avoids a misoperation by inrush current. The AP1210MP are available in the ESOP-8 (Exposed Pad) surface mount packages. VIN Shutdown Enable VCNTL VOUT VIN REFEN VCNTL VOUT GND R2 CSS CIN CCNTL COUT RDUMMY RTT AP1210MP R1 = R2 = 100KΩ , RTT = 50Ω / 33Ω / 25Ω COUT = 10uF ( + 100 uF under the worst case testing condition ) CSS = 1uF , CIN = 470 uF (Low ESR) , CCNTL = 47uF

Electronics Corp. AP1210MP ABSOLUTE MAXIMUM RATINGS(Note1) 28°C/W Note1 : Exceeding the absolute maximum rating may damage the device. OPERATING RATING(Note2) Note2 : The device is not guaranteed to function outside its operating conditions. ORDERING / PACKAGE INFORMATION (VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10uF(Ceramic), TA =25oC, unless otherwise specified) Parameter SYM TEST CONDITION MIN TYP MAX UNITS VCNTL Operation Current ICNTL IOUT = 0A - 0.5 2.5 mA Standby Current ISTBY VREFEN= 0V (Shutdown) - 25 uA VIN Shutdown Current IVIN VREFEN= 0V (Shutdown) - - 5 uA VCNTL UVP Rising Threshold VCOP VCNTL Rising 1.9 2.3 2.7 V VCNTL UVP Hysteresis VCHYS - 0.35 -V VIN UVP Rising Threshold VIOP VIOP Rising 0.7 0.84 1V VIN UVP Hysteresis VIHYS - 0.1 -V IOUT = 10mA -20 - 20 IOUT = -10mA -20 - 20 VIN=1.8V, VREFEN=0.9V, IOUT=+10mA ~ +2.5A -20 - 20 VIN=1.5V, VREFEN=0.75V, IOUT=+10mA ~ +2.5A -20 - 20 VIN=1.2V, VREFEN=0.6V, IOUT=+10mA ~ +2.5A -20 - 20 VIN=1.1V, VREFEN=0.55V, IOUT=+10mA ~ +2.5A -20 - 20 ELECTRICAL SPECIFICATIONS Input mV ΔVLoad Thermal Resistance from Junction to Case (Rthjc) Output (DDR / DDRII / DDRIII) UVP Function Output Offset Voltage(Note3) ΔVOS Load Regulation(Note4) (Top View) REFEN ESOP-8 NC NCGND VIN NC VCNTL VOUT GND Rthja = 75oC/W AP1210X Package Type MP : ESOP-8 .

Electronics Corp. AP1210MP Parameter SYM TEST CONDITION MIN TYP MAX UNITS Current Limit I LIM 3-- A Thermal Shutdown Temperature T SD 3.3V < VCNTL < 5V - 150 - Thermal Shutdown Hysteresis ΔTSD 3.3V < VCNTL < 5V - 20 - REFEN Threshold V EN 0.15 - 0.4 V Soft-Start Interval T SS ∆VOUT=1V - 0.2 - ms Note3. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note4. Regulation is measured at constant junction temperature by using a 1ms(on) / 9ms(off) current pulse. Devices are tested for load regulation in the load range from 10mA to 2.5A for source and -10mA to -2.5A for sink capability. PIN DESCRIPTIONS PIN SYMBOL PIN DESCRIPTION VIN Power Input Voltage. GND Ground Pin VOUT Output Voltage VCNTL Gate Drive Voltage REFEN Reference Voltage Input and Chip Enable BLOCK DIAGRAM ELECTRICAL SPECIFICATIONS (CONTINUED) ENABLE and Soft-Start Protection oC VCNTL ENABLE FUNCTION Soft-Start Function GATE CONTROL LOGIC (RS-LATCH) OCP Function UVP Function OTP Function REFEN VIN VOUT GND ERROR AMPLIFIER

Electronics Corp. AP1210MP

APPLICATION INFORMATION

Input Capacitor and Layout Consideration Consideration while designs the resistance of voltage divider Thermal Consideration Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.15V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft- start while another is for noise immunity. AP1210MP regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125oC. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( TJ(MAX) -TA ) / Rthja Where T J(MAX) is the maximum operation junction temperature 125 oC, T A is the ambient temperature and the R thja is the junction to ambient thermal resistance. The junction to ambient thermal resistance (R thja is layout dependent) for ESOP-8 package (Exposed Pad) is 75 oC/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at T A = 25oC can be calculated by following formula: PD(MAX) = (125oC - 25oC) / 75oC/W = 1.33W The thermal resistance R thja of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow Place the input bypass capacitor as close as possible to the AP1210MP. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1210MP and the preceding powe converter. AP1210MP AP1210MP

Electronics Corp. AP1210MP MARKING INFORMATION ESOP-8 1210MP YWWSSS Part Number Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence Package Code