PAL20X10A AMD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 23
Technical content
fF | COM’L: A/B/-20/AL_ MIL: A Pa | PAL20X10A Series Advanced AmPAL20L10B/-20/AL Micro XOR Registered 24-pin TTL Programmable Array Logic Devices rear EE DISTINCTIVE CHARACTERISTICS ™ XOR gates on registered outputs ™ Register preioad for testability | Efficient implementation of counters ™ Easy design with PALASM® software © Popular 24-pin architectures: 20L10, 20X10, ™ Programmable on standard PAL® device 20X8, 20X4 programmers ™ Programmable replacement for high-speed = 24-pin SKINNYDIP® and 28-pin PLCC TTL logic Packages save space =| Power-up reset for initialization ie EY GENERAL DESCRIPTION The PAL20X10A Series offers Exclusive-OR gates pre- The PAL device implements the familiar Boolean logic ceding each flip-flop. The XOR gate combines two sum transfer function, the sum of products. The PAL device terms, each composed of two product terms. This extra. _is a programmable AND array driving a fixed OR array. level of logic is very efficient for counter applications. The AND array is programmed to create customproduct a" terms, while the OR array sums selected terms at the The combinatorial member of the family, the PAL20L10, P, id follow. offers three product terms per output wih no XOR gate, gulp. lnadalion. the PAL device Provides he olow A fourth product term provides the enable term. While the registered devices are offered in only one pertorm- — Variable inpuvoutput pin ratio ance option, the 20L10 is offered in four performance - Programmable three-state outputs. grades. Note that three of these options follow the “old” — Registers with feedback AMD part numbering systemwhile the fourth follows the “ i Product terms with all fuses opened assume the logical ‘okt MMI part numbering system, as do the registered GH state; product terms connected to both true and * complement of any single input assume the logical LOW The family utilizes Advanced Micro Devices’ advanced _ state. Registers consist of D-type flip-flops that are bipolar process and fuse-link technology. The devices loaded on the LOW-1o-HIGH transition of the clock. Un- provide user-programmable logic for replacing conven- used input pins should be tied to Vec or GND. tional SS/MSI and flip-flops at a reduced chij count. gates liplops at a 1 'P The entire PAL device family is supported by the PALASM software package. The PAL family is pro- The family allows the systems engineer to implement grammed on conventional PAL device programmers the design on-chip, by opening fuse links to configure —_ with appropriate personality and socket adapter mod- AND and OR gates within the device, according to the ules. See the Programmer Reference Guide for ap- desired logic function. Complex interconnections be- proved programmers. Once the PAL device is pro- tweengates, which previously requiredtime-consuming grammed and verified an additional fuse may be opened layout, are lifted from the PC board and placed on sili- to prevent pattern readout. This feature secures proprie- con, where they can be easily modified during prototyp- _tary circuits. ing or production. PRODUCT SELECTOR GUIDE [veces | DEDICATED PRODUCT TERMS/ INPUTS. OUTPUT “AmPAL2OL10B 210 ‘AmPAL20L10-20 8 comb. 3 prog. 165 ‘AmPAL20L10AL 2 comb. 3 prog. 105 PAL20L10A 165 PAL2OXI0A— [100 reg [4 XOR [reg pin 30 ts) | 180 | PAL20X8A ere 4 reg. Ths part covered by varus US. ana foreign pens onned by avarice Mc Dees. " Icsue Date Janvayy 1980 2-188
‘AND Array (40 x 40) TESTS TS TSS Lah UIBUIBUIRU/RUL RU RUIRU| RO] Y oO; WO2 Ws VOs Ws Ws WOr Ws Ws Or 10303-0014 a PAL20X10 LK Inputs oF Uv 0 y) 10 b v M v AND Array (40 x 40) U U 9, U Uv 0 U Vv) U V) oO; O2 O3 O« Os Os O7 Os Os Oro 10303-0024 a PAL20X10A Series/AMPAL20L10 2-189
a BLOCK DIAGRAMS PAL20X8 cK Inputs OE
9 U Y
(40x 40) eae eoiraie PSE aE He ale Ie aie sie i | + aan Se Se a a a a wo © (o 7 Os Os oO; Os 0 Wr 10303-003A PAL20X4 CLK Inputs OE 9) 9 y) Vv M Vv AND Array (40 x 40) eS LS ESE ES La Ly y—$ Sp sp —_4 0 4] 0 Vv Vv Vv Vv a) 0 Q VO: We Ws Os Os Or Ws Ws Wr 10303-004A 2-190 PAL20X10A Series/APAL20L10
SKINNYDIP/FLATPACK PLCC (except AmPAL20L10) (wow 1) CY 241 Vee EE 4) C2 2a [7] (note 12) oo 22 328 12} 22[_] (Note 11) OOOO Lustre a nO} 21] OTE 10) wots ° [pore x uCs 20} _} (nore 9) us cd 5, fs 19 [_] wore 6) sc af Qoores C17 18 [_] (Note 7) neEfe z2[Aooren "je 17 [7] (NOTE 6) «Cle afoot Ce 16 [_] NOTE 5) ne wf] ores) 1, Cho 15[-] (note «) cm to wae a i uF ore 9 eau ww ono Efe taf] wore 10303-005A 222 10303-006A PLCC AmPAL20L10 only 12 [Note [ 2ovto [20x10 | zoxe | 20x4 | atatatatatat A EE Pa fe Tax Tax [ax | , ots sD i w]e af reat af, Le [wo Too | ow | om | AIALATOOINL [efi [oo | oo fo | Pe fo [oo | o | o | seso-074 [10 [vo [oom | om | me | Lee [| [oo fo |v 2 £8 Lie Tow | o% [we | vow | yer b3et Last) nls . anc PIN DESIGNATIONS “ys 2) (OTE 10) GND Ground tle voren ! Input 2 “ vo Input/Output io 10 20] mores NC No Connect "Oe myers
0 Output anweunw
OE Output Enable 22 geeg? Vee Supply Voltage 2228 10303-008A Note: Pin 1 is marked for orientation. a PAL20X10A Serles/AMPAL20L10 2-194
a
ORDERING INFORMATION
Commercial Products (MMI Marking Only) [AMD commercial programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: a. Family Type b. Number of Array Inputs ¢. Output Type 4. Number of Outputs ©. Speed 1. Operating Conditions 9. Package Type h. Optional Processing PAL 20 X 10A CNS a. FAMILY TYPE _ id PAL = Programmable Array Logic b. NUMBER OF h. OPTIONAL PROCESSING ARRAY INPUTS Blank = Standard Processing ©. OUTPUT TYPE 9. PACKAGE TYPE X = XOR Registered NS = 24-Pin 300-mil Plastic L = Active-Low Combinatorial NL SKINNYOIR {Fipscat) = 28-Pin Plastic Loa d. NUMBER OF OUTPUTS 5 = oti Carer (L028) JS = 24-Pin 300-mil Coramic ®. SPEED SKINNYOIP (CD3024) A = 30nstep {OPERATING CONDITIONS € = Commercial (0°C to +75°C) noon abl ts alld Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm ONS. CNL. avalabity of specfc valid combination, and to ONL, check on newly released combinations. Note: Marked with MMI logo. 2-192 PAL20X10A Serles
a Commercial Products (AMD Marking Only) AMD commercial programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: a. Family Type b. Number of Array Inputs ¢. Output Type d. Number of Outputs @. Spood f. Power g. Package Type h. Operating Conditions 1. Optional Processing AmPAL20 LiOALPC_ ° a. FAMILY TYPE __ AmPAL = Programmable Array Logic b. NUMBER OF L OPTIONAL PROCESSING ARRAY INPUTS Blank = Standard Processing ¢. OUTPUT TYPE h. OPERATING CONDITIONS L = Active-Low Combinatorial C = Commercial (0°C to +75°C) g. PACKAGE TYPE d. NUMBER OF OUTPUTS Pris 24Pin 300 i Paste SKINNYDIP (PD3024) © SPEED ot J = 28-Pin Plastic Leaded = PD Chip Carrier (PL 028) B = 15nstep D = 24-Pin 300-mil Ceramic A = 25nsteo SKINNYDIP (CD3024) f. POWER Blank = Full Power (165-210 mA Icc) L = Low Power (105 mA lec) [atid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. AmPAL20L10 | B, -20, PG, go Consult the local AMD sales office to confirm AL availability of specific valid combinations, and to check on newly released combinations. Note: Marked with AMD logo. oy AmPAL20L10 2-193
AMD programmable logic products for Aerospace and Defense applications are available with several ordering op- tions. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: a. Family Type b. Numbor of Array Inputs €. Output Type d. Number of Outputs @. Speed 1. Operating Conditions g. Package Type h. Device Class PAL 20 X 10A M JS /883B a. FAMILY TYPE __ ft PAL = Programmable Array Logic b. NUMBER OF h. DEVICE CLASS ARRAY INPUTS. 7838 = Class B © OUTPUT TYPE 9. PACKAGE TYPE X = XOR Registered JS = 24-Pin 300-mil Ceramic L_ = Active-Low Combinatorial w SKINNYDIP (cpgo24) = 24-Pin Ceramic Flatpack d. NUMBER OF OUTPUTS (Grises L_ = 28-Pin Ceramic ¢. SPEED Leadless Chip Cartier Ae Sonate (CL.028) {. OPERATING CONDITIONS M-= Military (55°C to +125°C) bition al ae [alld Combinations The Valid Combinations tabla lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm Mus/e83B, availabilty of specific valid combinations, to MW/s83B, check on newly released combinations, and to eer obtain additional data on AMD's standard military [razon | arate produc Note: Marked with MMI logo. Group A Tests Group A Tests consist of Subgroups: 1, 2,3, 7, 8, 9, 10, 11. Military Burn-in Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A through E. Test conditions are selected at AMD's option. SE 2-194 PAL20X104 Serles
Four different devices are available in the 20X10 Series, Security Fuse "i in ure’ re IMIMIN ‘secul AND gale array, and connections may be selectively re- Gace programm oa by hele Note Teed joke moved by applying appropriate voltages to the circuit - ; * ove’ ng @ the internal programmed pattern by a device program- Utilizing an easily-implemented programming algo- fer "sacuring proprietary designs from competitors rithm, these products can be rapidly programmed to any » Securing Pr s. customized pattern. Information or approved program. When the security fuse is programmed, the array will mers can be foundin the Programme entrance Guide, read asif every fuse is intact, Forthe AmPAL20L 10, the Extra test words are pre-programmed during manutac. 2""@Y will ead as if every fuse is programmed. turing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent Pinouts Parametric correlation. All members of the PAL20X10 Family have the same SKINNYDIP pinouts independent of technology, per- Variable Input/Output Pin Ratio formance, and operating conditions. Because the , ; , 24-pin SKINNYDIP requires four no-connects when The registered devices have ten dedicated input lines, . pi and each combinatorial outputis an VOpin. The 20.10 CPP Fe tne ee PLCC/LCC packages, the has twelve dedicated input lines, and only eight of the Pp ry, ten combinatorial outputs are VO pins. Buffers forde- Two different PLCC pinouts are offered. The vice inputs have complementary outputs to provide — AmPAL20L10 and all future devices will follow the user-programmable input signal polarity. Unused input JEDEC electronics committee's standard pinout pins should be tied to Vec or GND. (“JEDEC pinout”) with no-connects on pins 1, 8, 15, and 22. The older PAL20X10A Series devices retain their Programmable Three-State Outputs oyna! pinouts, with no-connects on pins 5, 8, 11, and Each output has a three-state output buffer with three- ° state contro!. On combinatorial outputs, a product term A different LCC pinout is offered for military prod- controls the butter, allowing enable and disable tobe a__ucts. The older PAL20X10A Series devices retain their function of any product of device inputs or output feed- _ original pinouts, with no-connects on pins 4, 11, 18, and back. The combinatorial output provides a bidirectional 25. VO pin, and may be configured as a dedicated input if Somi om the buffer is always disabled. On registered outputs, an PLec tec input pin controls the enabling of the three-state outputs. No-connects_| No-connects Registers with Feedback Registered outputs are provided for data storage and synchronization. Registers are composed of D-type flip fae PALSOLIOAS 4,11, 18, 25 flops that are loaded on the LOW-to-HIGH transition of * the clock input. Power-Up Reset Quality and Testability All fip-tlops power-up to a logic LOW for predictable The PAL20X10 Series offers a very high level of builtin system initialization. Outputs of the PAL20X10A Series Quality. Extra programmable fuses provide a means of will be HIGH due to the active-low outputs. The Vcc rise _etilying performance of all AC and DC parameters. In must be monotonic and the reset delay time is 1000 ns addition, this verifies complete programmability’ and maximum. functionality of the device to provide the highest pro- gramming yields and post-programming functional . ields in the industry. Register Preload ” ua The register on the PAL20X10A Series can be Technology preloaded from the output pins to facilitate functional ; testing of complex state machine designs. This feature TN@ PAL2OX10A Series is fabricated with AMD's ad- ° " | © vanced junction-isolated bipolar process. The array allows direct loading of arbitrary states, making it unnec- ti ‘ormed with TW fuses for rok essary 10 cycle through long test vector sequences to SPmenUne Bre formed wi Broven TIW fuses for rell- teach a desired state. In addition, transitions fromillegal___!€ operation. states can be verified by loading illegal states and ob- The AmPAL20L 10 is fabricated with the IMOX™ oxide- serving proper recovery. isolated bipolar process using proven PISituses. PAL20X10A Series/AMPAL20L.10 2-195
a LOGIC DIAGRAM SKINNYDIP (PLCC, PAL20L10A only) Pinouts ‘See Connection Diagrams for LCC and AMPAL20L10 PLCC Pinouts 20L10 of © 34 78 1112 1516 1920 2324 2728 3132 3536 39 Belicc OSE SEH HEH HEHEHE BR, Pe @ {2} > PATHE tee @ OTA PERSE HEE Bhatia ny HH tee ttt | 123] > a CARH ett et niiiny roc ett | [oe > ed AesgggeGGM0 0000000 0000110111 we TCH ee BEEBE Ey > —falio, a 2) Hy) Het tt |e 7 on > en SO ee PA ttt ttt @ TT EEE EEE EE EHH EJ >of, - B Prec | ih ee > a ee ee atone ttt ttt ttt TT ee EEE EE HE Rdg oe SEE I Ys SOOTHE at 2) PP Ed oe > Se (Anion cet tht @ Stee EEE ER ob oho pes scmsicmtismetscmersmersmtremtrsmstemeeies = 7 Poet PC) ee > a ee (Att wo EERE EEE EH RL, atuoy Cr | t[ 8} eee Ah a Te EEE HH Rg ratio, ESE HES SEE Rr | OP EL) gy > ee Att a tHe Ee EERE EE EEE EEE E ERE RE EEE > 9h fia] o; Pee a Wot} Ee 113} 44 (14) (76) oo ost Te ne be We na ae ne em 15) = 10000.00 a 2-196 PAL20X10A Series/AMPAL20L10
a LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts See Connection Diagrams for LCC Pinout 20X10 only P 0 34 78 1112 1516 1920 224 2728 232 3536 30 vee oH ee ee > MHC HPLilow ERE oe BD (| - @ Lea a eee aBiiBiiiaitiatt pes WH Fee eee Qs WES | Hoy tn HICH tI =< Pa D--{z]o5 " Hee a MAHmiiamalimiiimiTimilimiiie ea ee CE a eee a EHinitiaiaiaiii resh rpBHetrrS PEE EET ® «tC Foc | HH ee BD mR HHL ee i = De ztjog we HEE EBT i B Cae era tiBiiinitiaiiiait pe sh nl HoT oo eee eee © oy TTT ACs. | 12 HE oD © Hott Pete te D-—{20]0, oy SEE BY [| 2) SE a Tee TS HRTTiaitiaiil pesh WEHRe Hert ttt ttt} @ Te | HH oy > rR HHI LI Let Pe i Dofis}og gs CE BH lu @) WT TOT resh A o> rote ttt = @ oC CC ep | HSE Ee > ir HHP Ee a De-fislos wo SB [| @) CO a ee er atiimiiiiii resh eC Hee Tote ® eI CCS | He HE ef tH HHL EL ty a Poofiz7}ox sn SCE BH [| ey TT CT rey {a} Soe eee fant ttt
9 TE CCD |
PE er By > ir Hite tet Pt fe op} fislos se SSE Bt [| 2) TO TTT pe sh AC o> ee ee ott
6 CHS |
canes Seees dee eee soeeees eee esse et see es seeeesess 5 3D ir Pe a> Pe{islo. oy ZOE BT a oy} PEPE Ere Hee HHH re ish Tot iis os Hip. | HH eee By > ir HILL et = i at + P-fr4]o, 7s SEES BT > [ a Pee be yo EEE <pfisjoe (14) (8) GND 0 34 78 1112 1516 1920 2324 2728 3132 3536 39 10303-010A, ee PAL20X10A Series/AMPAL20L10 2-197
a LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts See Connection Diagrams for LCC Pinout 20x8 D LTD ae na ne pm mM Tm NR Bo 0 alee OSE EES be lo i IML eetetee t| ca) y}RHES (APO tt ttt @ sO EE or > In CT = > P—falos 9) SEER ee BF > [| 3) CT te zh tes} ee PHT eet tt ® eC Ee et ee Bi lR HC = Ppi]o5
99 OEE > | @)
(4-e— TT TAI tet tt @ eT ee a > is Ce <a> b-{zs}o; ar SSE Be > | 4) CC re ah 7 > ee Att ttt ttt; © 2th Ce | EE EB th CCT = a> pfiglog as TO ee BS > | @) He re ah se ero (APT @ oe SOC Et 35> ir <> Pp—{ilos ws Se Be > | @) CO re ah 6H ot Antti tht ® eT Ce | et te Bi im CC <> D{i7]o, sy EEE EE BD | @ CO =) 2B Hert (Att oo 6 TT CD | EO et tt Ff In Ce =a De-{i]og so SO ee oe BF > [| 20) COE teh lo > en 0 ee (Att TTT el | I et et Ry > rm CO =< De{is]o.
7 OE ee BF > [| (8)
1910) eet ttt 9 oe CO BEERS EEE EEE BS oh Fao, SAT TL tyoLt4} ETT TTT TTT —< <pfisloe ra) ic) GND a 0 34 78 1912 1516 1920 2324 2728 3132 35% 39 (8) > 10303-011A a 2-198 PAL20X10A Series/AMPAL20L10
a LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts See Connection Diagrams for LCC Pinout 20X4 out 0 34 78 1112 1516 1920 2324 2728 3192 3596 99 Balvoc ° os ESE 72 Se iriaiiiniiiniiiniiimiimiiniliniinitiicml ae {2} STS TSTMTSTBHiaiiaiiaiiniii @ Ce “SCTE | ° t[3} SE TS RIIEiTtaiiiaiiiaiiirmemas @ ye SC “RAMON | = @ a CT Ae | 2 HHL Ltt et et Tt << > { th-fea]o, CSesiiimiiimiiin) imiiimiiimiiimiiiwilimilicoames <) iia eH ES SE © ST Ee | ote HIM te I a Ppofrs]og Seiiimiiimiiamiiin|/iniiimiiimisimiiniiiie eae i ts[e} pS Ha i ae CTT Se | ot Ht tet tee Pe P< > De-fis]os, oe CR | 2) SURRO LER AED ROEM ELE EY TOT res eH et Ht a Ce | ot HICH Defiz]o,
5 SEE eB [] er
“STATA | =" ta[>} Oe CTT TTT EEE EEE EEE EE {15]wo2 ° : MT | id tg[10} Too eee (Add
6 See aaa esas neeaeessascesasccsasacsesases s+ Dan {ia}io,
ho RE <p—[is]e 4) (a) 10303-012A a PAL20X10A Serles/AMPAL20L10 2-199
a ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65°C to +150°C Commercial ({C) Devices Ambient Temperature with ‘Ambient Temperature (Ta) Power Applied 55°C to +125°C Operating in Free Air 0°C to +75°C ' Supply Voltage with Supply Voltage (Voc) Respect to Ground 05 V10+7.0V with Respect to Ground +4.75 V0 +5.25 V DC Input Voltage “15 VtoVcc+05V Operating ranges define those limits between which the func- DC Output or VO Pin Voltage ~-0.5V toVcc +0.5V tionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. By. Programming conditions may Caer DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specitied Parameter Symbol _| Parameter Description Test Conditions Vou Output HIGH Voltage fon =-3.2MA Vin = Vii Or Vi Vv Veo = Min. Vou Output LOW Voltage lo =24mA Vin = Vir or Vi. Vv Voc = Min. Viv Input HIGH Voltage Guaranteed Input Logical HIGH Vv Vottage for all Inputs (Note 1) Vi Input LOW Voltage Guaranteed Input Logical LOW Vv Vottage for all Inputs (Note 1) Input Clamp Voltage In=—18 MA, Voc = Min. [fs] vi [Im ___| Input HIGH Current Vin= 2.4 V, Voc = Max. (Note 2) [| 25[ pa | [in| Input LOW Current Vin= 0.4 V, Voc = Max. (Note 2) [| -250[ na | [__| Maximum Input Current Vin = 5.5 V, Voo_= Max. [| 700] pA | Off-State Output Leakage Vout = 2.4 V, Vcc = Max. nA Current HIGH Viv = Vivor Vu (Note 2) Off-State Output Leakage Vout = 0.4 V, Voc = Max. WA Current LOW Vin = Vinor Vi (Note 2) ‘Output Short-Circuit Current | Vour = 0.5 V, Vcc = Max. -30 | -130 (Note 3) 20X10A, Viv= 0 V, Outputs Open | 20X8A, lee Supply Current {lour = 0 MA), Voc = Max.| 20X4A_ Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. WO pin leakage is the worst case of lt. and loz. (oF li and loz). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by taster ground degradation. 2-200 PAL20X10A Series (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Pym renner ousuen | mm | |u| Input or Feedback to 20L10A, 20X8A, ns [i [Sarma ae] | | [is] Setup Time from inputor Feedback To Giock | ee [| Hodtime [oo [ts [me] aoxron, 2oxea,[ 25 || ne _| ES c5s wan Face —————} zoxe [5 [as | Po ae [eee [ee | Note 2) [2s [| ete | [tex [Oe to Ouputenabie [| 20 T ns | a Ls RaLioA POKER] [30 ne | axa [| 0 [os | 4. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is moditied where frequency may be affected. NN PAL20X10A Series (Com’l) 2-201
a ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65°C to +150°C Military (M) Devices (Note 1) A it (Ta) ‘Ambient Temperature ‘Ambient Temperature (Ta) ; with Power Applied ~55°C to +125°C. Operating in Free Air 55°C Min. ‘Supply Voltage with Operating Case (Tc) Respect to Ground ~0.5V10+7.0V Temperature 125°C Max. DC Input Voltage -15V to5.5V Supply Voltage (Vcc) DC Output or YO Pin Voltage -0.5V to5.5V with Respect to Ground +450 V to +5.50V Stresses above those listed under Absolute Maximum Rat- Operating ranges define those limits between which the func- ings may cause permanent device failure. Functionality at or anality of the device is quarantoed. above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabi- Note: ‘ty. Programming conditions may differ. Absolute Maximum apse . Ratings are for system design reference; parameters given _\\- Miltary products are tested at Tc = +25°O, +125°C, ‘are not tested, and ~55°C per MIL-STD-883. ee DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified (Note 2) Parameter | aan | | une | Symbol__| Parameter Description Vou Output HIGH Voltage lon=-2 MA Viv= Vin or Vi. v Voc = Min. Vow ‘Output LOW Voltage la =12MA Vin= Vin or Va, v Vee = Min. Vin Input HIGH Voltage Guaranteed Input Logical HIGH Vv Voltage for all Inputs (Note 3) Vit Input LOW Voltage Guaranteed Input Logical LOW Vv Voltage for all inputs (Note 3) Tapa Cap Varese [w= =18 mA Voc=min. | | 8] v | Input LOW Current Vai = 0.4 V, Voc = Max. (Note 4) |_| -250] pa | [| Maximum input Curent [Vn=55V.veo=Mox | | 1 ma | loz Off-State Output Leakage Vout = 2.4 V, Vec = Max. pA Current HIGH Viv = Vin or Vu (Note 4) loz Off-State Output Leakage Vour = 0.4 V, Veo = Max. BA Current LOW Viv = Vin or Vu (Note 4) Output Short-Circuit Current__| Vour = 0.5 V, Vec = Max. (Note 5) 30 | -130 [ma | 20X10A, Vin= 0 V, Outputs Open | 20X8A, lec Supply Current (lour= 0 mA), Voc = Max.|_20X4A mA zoioa_[ || Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vi. and Vi are input conditions of output tests and are not themselves directly tested. Vi and Viv are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment 4, W/O pin leakage is the worst case of I and loai (or Im and loz). 5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-202 PAL20X10A Series (Mil)
a SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 1) Parameter Symbol p Input or Feedback to 20L10A, 20X8A, 35 ns Combinatorial Output 20X4A [ts | Setup Time from Input or Feedback to Clock fo [ns | [tm [Hodtime fo [| ns | [_tco___| Clock to Output or Feedback (fs [ns Fj zoxtoa,2oxea,[ 35 [| ns | [tm | Com with zoxsa [20 | | ons | Maximum Wits + tco) [isa [| Mee | en Nowe)” __[NoFeedback [tun +t re ce GE to Output Enable (Note 3) Cts [ns] ‘GE to Output Disable (Note 3) [| 2s [ns | Term Control (Note 3) : 20L10A, 20X8A, Input to Output Disable Using Product 20X4A, Term Control (Note 3) | 2 Notes: 1. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. a PAL20X10A Series (Mil) 2-203
a ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65°C to +150°C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) Power Applied -55°C to +125°C Operating in Free Air 0°C to +75°C ‘Supply Voltage with Supply Voltage (Vcc) Respect to Ground ~0.5 V10 +7.0V with Respect to Ground +4.75 V to +5.25 V OC Input Voltage “O05 Vt0+5.5V Operating ranges define those limits between which the func- OC Output or VO Pin Voltage -0.5 V to Voc Max. tionality of the device is guaranteed. DC input Current 30 MA to +5 mA Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- ‘mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter ‘Symbol Parameter Description Test Conditions Vow Output HIGH Voltage lon =-3.2MA Vin = Vis oF Vin v Vee = Min. Vou Output LOW Voltage l= 24mA— Vin=Vinor Vin v Voc = Min. Vin Input HIGH Voltage Guaranteed Input Logical HIGH Vv Vottage for all Inputs (Note 1) Vi Input LOW Voltage Guaranteed Input Logical LOW Vv Voltage for all Inputs (Note 1) Tapal Clan Votage [w= 8 mA,Voo=min |_| et Vv [tm _| Input HIGH Current Vin = 2.7 V, Veo = Max. (Note 2) [| 5 | na | [tu _| input Low Current Vin = 0.4 V, Veo = Max. (Note 2) [|__| -100 | na | [| Maximum input Current | Vn= 5.5 V, Veo = Max. Pt | ma | Off-State Output Leakage Vout = 2.7 V, Vec = Max. HA Current HIGH Vin = Vin or Vi. (Note 2) Off-State Output Leakage Vout = 0.4 V, Vec = Max. HA Current LOW Vin = Vin or Vi. (Note 2) [Isc | Output Short-Circuit Current _[ Vour=0.5V, Voc =Max.(Note3) | -30 | -90 | ma | zoos | [210 | Pie | Supply Current t= 0 V, Outputs Open -20ci0-20 || 165 | Glour = 0.mA) Voo = Max [2octoaL |] 105 | Notes: 1. Those are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included 2. VO pin leakage is the worst case of I, and loz (oF Ii and lozH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-204 AmPAL20L.10 (Com't)
CAPACITANCE (Note 1) Parameter Symbol _| Parameter Description Test Conditions Typ. [ Others | Ta= 425°C [ 6} og i Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter [201108 [2011020 [ 20u10at | Input or Feedback to 15 Combinatorial Output Input to Output Enable Using Product Term Control ter Input to Output Disable Using Product Term Control 2 Notes: 2. See Switching Test Circuit for test conditions. AmPAL20L10 (Com’t) 2-205
a SWITCHING WAVEFORMS Input or Input or teo ts uw Combinatorial Output vr Clock vr tco 12015-010A Combinatorial Output Registered Output vr 12015-012A Registered Output tw wt o . = =e 7 W355 LV baad Output EE SEEN Ol 12015-0114, Clock Width 12016-0134 Input to Output Disable/Enable OE texz tex Output vr 12015-0144 GE to Output Disable/Enable Notes:
1 Vret5V
- Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2-5 ns typical. an 2-206 PAL20X10A Serles/AMPAL20L10
KEY TO SWITCHING WAVEFORMS WAVEFORM — INPUTS outputs Must be Willbe Steady Steady WAL fn BS Change Changing fromHtoL ——fromHtoL May Will be ‘Chango Changing fromLtoH from LtoH Don'tCare; Changing, ‘Any Change —Sttate Permitted Unknown Does Not Centor Apply Line is High- 2 Impedance “Off State KS000010-PAL SWITCHING TEST CIRCUIT Vee h si Ry Output Test Point Re T a = = 10303-0134 Measured Specitication la heehee Output Value [wots | Gmee | te2x, tea ZH: Open 15V ZL: Closed 200 7500 texz, ter HZ: Open 5 pF HZ: Vou-0.5V L+2: Closed L>Z:Vo.+05V PAL20X10A Serles/AMPAL20L10 2-207
INPUT/OUTPUT EQUIVALENT SCHEMATICS Typical Input Typical Output Veo Vee
40 Q NOM
12350-020A ‘Output , Input, , Program/Veril Program/Verify/ “Bircuitry pe. Test Circuitry ins Preload Circuitry . 10303-0144, 2-208 PAL20X10A Series/AMPAL20L10
The preload function allows the register to be loaded preload a LOW in the flip-flop. Leave combinatorial from the output pins. This feature aids functional testing outputs floating of sequential designs by allowing direct setting of output states. The procedure for-preloading follows. 5. Lowerpin 10 to Vip. 4. Raise Vee to Vocu. 6. Remove Vip/Vup from all registered output pins. 2. Set OE to Vive to disable output registers. 7. Lower OE to Vip to enable the output registers. 3. Raise pin 10 to Vis to enter preload mode. 8. Verity VoL/Vou atall registered output pins. Note that because of the output inverter, a register that has 4. Apply either Vip or Vip to alll registered outputs. Use been preloaded HIGH will provide a LOW at the Vine to preload a HIGH in the flip-flop; use Virp to output. Parameter Symboi Parameter Description Super-tevel input voltage [19 | 20 Joa |v | Low-level input voltage po Jo J os Tv | High-level input voltage [24 | 50 [55 | v | Power supply during preload re [to Belaytime 100 200 T1000 [ns | 12 to to to to to —— Vy OE T\\ " Var —— Vin Pin 10 Vur | =e Registered 4 ly Vou ‘Output Vor ~TT7 Vee 10303-0154 Output Register Preload Waveform PAL20X10A Series/AMPAL20L10 2-209
a POWER-UP RESET ‘The power-up reset feature ensures that alflip-lops will __can rise to its steady state, two conditions are required be reset to LOW after the device has been powered up. _to ensure a valid power-up reset. These conditions are: The output state will be HIGH due to the inverting output ; , buffer. This feature is valuable in simplifying state ma-__- The Vc rise must be monotonic. chine initialization. A timing diagram and parameter ta- >. Following reset, the clock input must not be driven ble are shown below. Due to the synchronous operation from LOWto HIGH until all applicable input and teed- of the power-up reset and the wide range of ways Vcc back setup times are met. Parameter Symbol Parameter Description [tern | Power-up Reset Time [1000 ns [ts | __Inputor Feedback Setup Time See Switching [tw | __ Clock Width LOW Characteristics av Vee Power ter Registered Active-Low Output ts Clock tw 12360-0240 Power-Up Reset Waveform ——eeSeeSeSSSSSSSSSSSSSSSeeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsssssseses 2-210 PAL20X10A Series/AMPAL20L10