AMIS-42700

AMIS-42700 AMI | Alldatasheet

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Technical content

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

1.0 Key Features

Controller area network (CAN) is a serial communication protocol, which supports distributed real-time control and multiplexing with high safety level. Typical applications of CAN-based networks can be found in automotive and industrial environments. The AMIS-42700 Dual-CAN transceiver is the interface between up to two physical bus lines and the protocol controller and will be used for serial data interchange between different electronic units at more than one bus line. It can be used for bot h 12V and 24V systems. The circuit consists of following blocks:

• Two differential line transmitters
• Two differential line receivers
• Interface to the CAN protocol handler
• Interface to expand the number of CAN busses
• Logic block including repeater function and the feedback suppression
• Thermal shutdown circuit (TSD)
• Short to battery treatment circuit Due to the wide commo n-mode vo ltage ra nge of the rec eiver i nputs, the AMIS-427 00 is abl e to reach o utstanding lev els of electromagnetic suscepti bility (EMS). Sim ilarly, extremely lo w e lectromagnetic emis sion (EME) is achieved by the e xcellent matching of the output signals.

2.0 Key Features

• Fully compatible with the ISO 11898-2 standard
• Certified “Authentication on CAN Transceiver Conformance (d1.1)”
• High speed (up to 1 Mbit/s)
• Ideally suited for 12V and 24V industrial and automotive applications
• Low EME common-mode-choke is no longer required
• Differential receiver with wide common-mode range (+/- 35V) for high EMS
• No disturbance of the bus lines with an un-powered node
• Transmit data (TxD) dominant time-out function
• Thermal protection
• Bus pins protected against transients in an automotive environment
• Power down mode in which the transmitter is disabled
• Short circuit proof to supply voltage and ground
• Logic level inputs compatible with 3.3V devices
• ESD protection guaranteed up to ±8KV 3. 0 Tec hnic a l C h ar ac ter i s t i c s Table 1: Technical Characteristics Symbol Parameter Conditions Min. Max. Unit VCANH DC voltage at pin CANH 0 < VCC < 5.25V; no time limit -45 +45 V VCANL DC voltage at pin CANL 0 < VCC < 5.25V; no time limit -45 +45 V Vi(dif)(bus_dom) Differential bus output voltage in dominant state 42.5Ω < RLT < 60Ω 1.5 3 V tpd(rec-dom) Propagation delay TxD to RxD See Figure 7 70 245 ns t pd(dom-rec) Propagation delay TxD to RxD See Figure 7 100 245 ns CM-range Input common-mode range for comparator Guaranteed differential receiver threshold and leakage current -35 +35 V VCM-peak Common-mode peak See Figure 8 and 9 (note) -500 500 mV VCM-step Common-mode step See Figure 8 and 9 (note) -150 150 mV Notes: The parameters VCM-peak and VCM-step guarantee low EME. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 1 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

4.0 Ordering Information

Marketing Name Package Temp. Range AMIS 42700FHA SOIC-20 300 G -40°C… 125°C 5. 0 B l ock D i agr a m CANH1 CANL1 AMIS-40700 GNDRx0VREF 18Driver control 2 x timer clock COMP Vcc/2 Ri(cm) Ri(cm) Timer VCC Logic Unit Driver control Thermal shutdown COMP Vcc/2 Ri(cm) Ri(cm) Timer VCC POR 10 3 4 7 9 25 6 15 16 17 PC20050502.1 Feedbeck Surpression Feedbeck Surpression RintTx0TextENB1 ENB2 VCC CANH2 CANL2 Figure 1: Block Diagram

6.0 Typical Application

6.1 Application Description

AMIS-42700 is especially designed to provide the link between a CAN controller (protocol ic) and two physical busses. It is able to operate in three different modes:

• Dual CAN
• A CAN bus extender
• A CAN bus repeater AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 2 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

6.2 Application Schematics

4 CANH2

PC20050511.6 5 6 15 16 17 CANL2 CANH1 CD RLT 60 Ω CAN BUS 2CAN BUS 1 RLT 60 Ω 100 nF VBAT 5V-reg Figure 2: Application Diagram CAN-Bus Repeater AMIS-42700 EN1 EN2 Text Rx0 Tx0 Rint VBAT CANH2 CANL1 GND VCC VrefVCC 1312 GND CAN con- troller PC20050502.3 5V-reg 5 6 15 16 17 CANL2 CANH1 CDCD RLT 60 Ω CAN BUS 2CAN BUS 1 RLT 60 Ω 100 nF100 nF µC Figure 3: Application Diagram Dual-CAN AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 3 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 4 www.amis.com AMIS-42700 EN1 EN2 Text Rx0 Tx0 Rint VBAT CANH2 CANL1 GND VCC VrefVCC 1312 GND CAN con- troller 5V-reg 5 6 15 16 17 CANL2 CANH1 CDCD RLT 60 Ω CAN BUS 2CAN BUS 1 RLT 60 Ω 100 nF100 nF µC PC20050502.9 AMIS-42700 EN1 EN2 Text Rx0 Tx0 Rint 60 Ω CAN BUS 4CAN BUS 3 RLT 60 Ω 100 nF Figure 4: Application Diagram CAN Bus Extender AMI Semiconductor – Rev. 1.4, May 05 - Preliminary

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

6.3 Pin Description

6.3.1 Pinout (top view)

PC20050502.2 NC GND GND CANL2 CANH2 Text EN2 Figure 4: Pin Configuration

6.3.2 Pin Description

Table 2: Pinout Pin Name Description

1 NC Not connected

2 ENB2 Enable input, bus system 2

3 Text Multi system transmitter input

4 Tx0 Transmitter input

5 GND Ground connection, note 1

6 GND Ground connection, note 1

7 Rx0 Receiver output

8 VREF1 Reference voltage

9 Rint Multi system receiver output

10 ENB1 Enable input, bus system 1

11 NC Not connected

12 VCC Positive supply voltage

13 CANH1 CANH transceiver I/O bus system 1

14 CANL1 CANL transceiver I/O bus system 1

15 GND Ground connection, note 1

16 GND Ground connection, note 1

17 GND Ground connection, note 1

18 CANL2 CANL transceiver I/O bus system 2

19 CANH2 CANH transceiver I/O bus system 2

20 NC Not connected

Notes: 1) In order to ensure the chip performance, these pins need to be connected to GND on the PCB. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 5 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 7. 0 F u nc ti onal De scr i pti on

7.1 Overall Functional Description

The CAN transceiver is specially designed to provide the link between the protocol IC (CAN controller) and two physical bus lines. Data interchange between those t wo bus lines is real ized via the interfa ce. Bitwise arbitration is e xtended on b oth buses. A fault like short circuit is limited to that bus line where it occurs. Data interchange from the protocol IC to the other bus system and on this bus system itself can be continued. The transceiver can also be used for o nly one bus system. If the connections for the second bus system are simply left op en it serves as a single transceiver for an electronic unit. For correct operation it is necessary to terminate an open bus. If not, the open bus will disturb the other one, e.g. in case of open load. The bus lines can have two logical states, dominant or recessive. A bus is i n the recessive state when the driving sections of all transceivers connected to the bus are passive. The differential voltage between the two wires is approximately zero. If at least one driver is active the bus changes into the dominant state. This state is represented by a differential voltage greater than a minimum threshold and therefore by a current flow through the terminating resistors of the bus line. The recessive state is overwritten by the dominant state. To provide an independent switch-off of the transceiver units for both bus systems by a third device (e.g. the µC) enables inputs for the corresponding driving and receiving sections to be included.

7.2 Transmitter

The transceiver includes two transmitters, one for eac h bus line and a driver control circuit. Each transmitter is implemented as a push and a pull driver. The drivers will be active if the transmi ssion of a dominant bit i s required. During the tra nsmission of a recessive bit all drivers ar e passive. T he transmitters hav e a bu ilt-in cur rent limitin g cir cuit t hat prote cts the driver stage s from damage caused by accidental short circuit to either pos itive supply voltage or to ground. Additionally a thermal protection circuit is integrated. The driver co ntrol circuit ensures that th e drivers are switched on and off with a controlled slope to limit EME. The driver c ontrol circuit will be controlled itself by the thermal protection circuit, the timer circuit, the ENBx inputs, and the logic unit. The domin ant time out timer circuit pr events the o utput d rivers from dri ving a p ermanent dom inant state (block ing all network communication) if pin Tx0 or the bus lines of the other bus are forced p ermanently dominant by a hardware and/or software failure (see tdom(TxD)). The enable signal ENBx allows the transmitter to be s witched off by a third device (e.g. the µC). In th e disabled state (ENBx = high) the corresponding transmitter behaves as in the rece ssive state and does not depend on the input voltage at Tx0 nor on the state of the other bus system.

7.3 Receiver

Two b us recei ving secti ons sense the stat es of the bus lines. Eac h receiver sectio n cons ists of an input f ilter an d a fast and accurate com parator. The ai m of the input filter is to improve the im munity against h igh-frequency disturbances a nd als o to convert the voltage at the bus lines CANHx and CANLx, which can vary from –12V to +12V, to voltages in the range 0 to 5V, which can be applied to the comparators. The output s ignal of th e comparators is gated by the ENBx signal. In the disabled state (ENBX = high) the output signal of t he comparator will be rep laced by a p ermanently recessive state and does not depend on the bus v oltage. In the enab led state the receiver signal sent to the logic unit is identical to the comparator output signal. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 6 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

7.4 Feedback Suppression

To provide proper function a feedback suppression must be included. This circuit replaces the reception of a dominant bit detected by the receiving section with a recessive bit if the corresponding transmitter is active. The feedback suppression must be activated immediately after the transmitter is requested to drive, i.e. before the receiver detects the d ominant state at th e bus. After d eactivating the tra nsmitter, the f eedback sup pression must sta y activ e l ong en ough t o guarantee that the corresponding receiver has sufficient time to change its state from dominant to recessive. Including the feedback, suppression is pos sible b ecause a transmitter becomes active if the other bus s ystem or Tx0 is i n t he dominant state, so the re ception of a domi nant bit is alrea dy realized and need not be d one additionally by this receiving section. Without feedback suppression the whole system would stay constantly in the dominant state after the occurrence of one dominant bit. The logic is im plemented in such a way that the suppression blocks in the two busses work independently of each other, and are identical so that both busses have the same priority. Furthermore the oscillation or single pulsing, that could occur at the dominant to recessive edge when the transceiver has received acknowledges from both busses, is avoided with this implementation. If both buses are driven externally and go from dominant to recessive with some delay between each other, no spurious pulses are seen at RINT and Rx0. However, it is possible to have the driving section of one bus going active while that bus is still driven externally. To minimize the chanc e of this cond ition, an additional delay of typical 50ns is adde d that blocks the re quirement to drive the driving section after the bus is forced externally from dominant to recessive.

7.5 Logic Unit and CAN Controller Interface

The central logic unit provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus. Digital input stages co nvert the input voltage at T x0 and TEXT into a logical v alue for the log ic unit. All di gital inputs, including ENBx, have an internal pull up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted. Output stages convert the logical value provided by the logic unit into voltages corresponding to the input signal specification of the CAN controller at Rx0 and RINT. A dominant state on the bus line is represented by a low-level at the digital interface, a recessive state is represented by a high-level. Vref provides an analog voltage of Vcc/2 as a reference for CAN controller with analog inputs. Input and output signals of th e logic unit are related in such a way that a dominant state on a ny bus or T x0 causes a domi nant state on both buses, RINT and Rx0. The output si gnal at R x0 cor responds to th e in puts T x0 and T EXT, independent of the state of th e two e nable in puts. T his is realized by an internal logical connection. The pins T EXT and RINT are us ed for c onnecting the internal logics of several ICs to obtain versions with more than t wo bus outputs. If a domin ant bit is receiv ed from at least one of the t wo bus systems (under the con dition of feedback su ppression) or from Tx0, RINT carries the lo w-level. Otherwise RINT is high. A low-level at TEXT activates both transmitters causing a dominant state on both busses and sets Rx0 to the low-level. A high-level at TEXT does not influence the transceiver.

7.6 Power-on-Reset (POR)

While Vcc voltage is below the POR level, the POR circuit makes sure that:

• The counter is kept in the reset mode and stable state without current consumption
• Inputs are disabled (don't care)
• Outputs are high impedant; only Rx0 = high-level
• Analog blocks are in power down
• Oscillator not running and in power down
• CANHx and CANLx are recessive
• VREF output high impedant for POR not released AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 7 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

7.7 Time Out Timer

The Tx0 dominant time out timer circuit prevents the output drivers from driving a permanent dominant state (blocking all network communication) if pin Tx0 or the bus lines of the other bus are forced permanently dominant by a hardware and/or software failure. The timer is triggered by a negative edge of the TIMERIN signal. If the d uration of the low-level on TIMERIN exceeds the internal timer value TIMERDEL, the timer output TIMEROUT becomes high, disabling the transmitter (bus returns into the recessive state). The timer is reset by a positive edge of the TIMERIN signal.

7.8 Over Temperature Detection

A thermal protection c ircuit i s integr ated to preve nt the transce iver from dama ge if th e ju nction tem perature e xceeds therm al shutdown l evel. Because th e transmitter dissipates most of the total p ower, the tr ansmitter will be s witched off onl y to re duce power dissipation and IC temperature. All other IC functions continue to operate.

7.9 Fault Behavior

A fault like a short circuit is l imited to that b us line where it occurs, henc e data i nterchange from th e protocol IC to th e other bus system is not affected. When the v oltage at the b us lines is g oing out of the normal o perating ran ge (-1 2V to + 12V), the receiv er is n ot allo wed to erroneously detect a dominant state.

7.10 Short Circuits

As specified in the maximum ratings, short c ircuits of the b us wires CANHx and CANLx to the posit ive supply voltage Vbat or to ground must not destroy the transceiver. To provide sufficient safety for automotive applications the v oltage range for permanent short circuits is extended to 50V dc. A short circuit between CANHx and CANLx must not destroy the IC as well. The dedicate d comparator ( L2VBAT) on CANL pin det ects the short to batter y an d after debo unce time-o ut sw itches off the affected driver only. The receiver of the affected driver has to operate normally.

7.11 Faulty Supply

In case of a fault y s upply ( missing co nnection of the el ectronic u nit o r the transceiv er to groun d, missing co nnection of the electronic unit to Vbat or missing connection of the transceiver to Vcc) the power supply module of the electronic unit will operate such that the transceiver is not supplied, i.e. the voltage Vcc is below the POR level. In this co ndition the bus c onnections of the transceiver must be in the POR state. If the ground line of the electronic unit is interrupted, Vbat may be applied to the Vcc pin (measured relative to the original ground potential, to which the other units on the bus are connected).

7.12 Reverse Electronic Unit (ECU) Supply

If the connections for ground and supply voltage of an electronic unit (ECU) (max. 50V) which provides Vcc for the transceiver are exchanged, this transceiver has a ground potential which may be up to 50V higher than that of the other transceivers. In this case no transceiver must be destroyed even if several of them are connected via the bus system. Any exchange among the si x connections CANH1, CANH 2, CANL1, CA NL2, ground, and supply voltage of the elect ronic unit at the connector of the unit must never lead to the destruction of any transceiver of the bus system. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 8 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet 8. 0 E l ec tr ic al C h ar ac ter i s t i c s

8.1 Definitions

All voltages are referenced to GND. Positive currents flow into the IC. Sinking current means that the current is flowing into the pin. Sourcing current means that the current is flowing out of the pin.

8.2 Absolute Maximum Ratings

Stresses above those listed in the following table may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings Symbol Parameter Conditions Min. Max. Unit VCC Supply voltage -0.3 +7 V VCANH DC voltage at pin CANH 0 < VCC < 5.25V; no time limit -45 +45 V VCANL DC voltage at pin CANL 0 < VCC < 5.25V; no time limit -45 +45 V VTxD DC voltage at pin TxD -0.3 VCC + 0.3 V VRxD DC voltage at pin RxD -0.3 VCC + 0.3 V VS DC voltage at pin S -0.3 VCC + 0.3 V VREF DC voltage at pin VREF -0.3 VCC + 0.3 V Vtran(CANH) Transient voltage at pin CANH Note 1 -150 +150 V Vtran(CANL) Transient voltage at pin CANL Note 1 -150 +150 V Vtran(VSPLIT) Transient voltage at pin Vsplit Note 1 -150 +150 V Vesd(CANL/CANH) ESD voltage at CANH and CANL pin Note 2 Note 4 -500 +500 kV V Vesd ESD voltage at all other pins Note 2 Note 4 -250 +250 kV V Latch-up Static latch-up at all pins Note 3 100 mA Tstg Storage temperature -55 +155 °C Tamb Ambient temperature -40 +125 °C Tjunc Maximum junction temperature -40 +150 °C Notes: 1) Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 4). 2) Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is ±2 kV. 3) Static latch-up immunity: static latch-up protection level when tested according to EIA/JESD78. 4) Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.

8.3 Thermal Characteristics

Symbol Parameter Conditions Value Unit Rth(vj-a) Thermal resistance from junction to ambient in SO8 package In free air 145 K/W Rth(vj-s) Thermal resistance from junction to substrate of bare die In free air 45 K/W AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 9 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

8.4 DC Characteristics

Table 4: DC Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Supply (pin VCC) ICC Supply current Dominant; VTXD =0V Recessive; VTXD =VCC mA mA Transmitter Data Input (pin TxD) VIH High-level input voltage Output recessive 2.0 - VCC V VIL Low-level input voltage Output dominant -0.3 - +0.8 V IIH High-level input current VTxD =VCC -1 0 +1 µA IIL Low-level input current VTxD =0V -75 -200 -350 µA Ci Input capacitance Not tested - 5 10 pF Mode Select (pin S) VIH High-level input voltage Silent mode 2.0 - VCC V VIL Low-level input voltage High-speed mode -0.3 - +0.8 V IIH High-level input current VS =2V 20 30 50 µA IIL Low-level input current VSTB =0.8V 15 30 45 µA Receiver Data Output (pin RxD) VOH High-level output voltage IRXD = - 10mA 0.6 x VCC 0.75 x VCC V VOL Low-level output voltage IRXD = 6mA 0.25 0.45 V Ioh High-level output current Vo=0.7 x VCC -5 -10 -15 mA Iol Low-level output current Vo=0.3 x VCC 5 10 15 mA Reference Voltage Output (pin VREF) VREF Reference output voltage -50µA < IVREF < +50µA 0.45 x VCC 0.50 x VCC 0.55 x VCC V VREF_CM Reference output voltage for full common mode range -35V <VCANH< +35V; -35V <VCANL< +35V 0.40 x VCC 0.50 x VCC 0.60 x VCC V Bus Lines (pins CANH and CANL) Vo(reces)(CANH) Recessive bus voltage at pin CANH VTxD =VCC; no load 2.0 2.5 3.0 V Vo(reces)(CANL) Recessive bus voltage at pin CANL VTxD =VCC; no load 2.0 2.5 3.0 V Io(reces) (CANH) Recessive output current at pin CANH -35V <VCANH< +35V; Io(reces) (CANL) Recessive output current at pin CANL -35V <VCANL < +35V; Vo(dom) (CANH) Dominant output voltage at pin CANH VTxD = 0V 3.0 3.6 4.25 V Vo(dom) (CANL) Dominant output voltage at pin CANL VTxD = 0V 0. 5 1.4 1.75 V VTxD = 0V; dominant; 42.5Ω < RLT < 60Ω 1.5 2.25 3.0 V Vi(dif) (bus) Differential bus input voltage (VCANH - VCANL) VTxD =VCC; recessive; no load -120 0 +50 mV Io(sc) (CANH) Short circuit output current at pin CANH VCANH =0V;VTxD =0V -45 -70 -95 mA Io(sc) (CANL) Short circuit output current at pin CANL VCANL =36V; VTxD =0V 45 70 120 mA Vi(dif)(th) Differential receiver threshold voltage -5V <VCANL < +12V; -5V <VCANH < +12V; see Figure 5 0.5 0.7 0.9 V Vihcm(dif) (th) Differential receiver threshold voltage for high common-mode -35V <VCANL < +35V; -35V <VCANH < +35V; see Figure 5 0.3 0.7 1.05 V Vi(dif) (hys) Differential receiver input voltage hysteresis -35V <VCANL < +35V; -35V <VCANH < +35V; see Figure 5 50 70 100 mV Ri(cm)(CANH) Common-mode input resistance at pin CANH 15 26 37 KΩ Ri(cm) (CANL) Common-mode input resistance at pin CANL 15 26 37 KΩ Ri(cm)(m) Matching between pin CANH and pin CANL common-mode input resistance VCANH =VCANL -3 0 +3 % Ri(dif) Differential input resistance 25 50 75 KΩ Ci(CANH) Input capacitance at pin CANH VTxD =VCC; not tested 7.5 20 pF Ci(CANL) Input capacitance at pin CANL VTxD =VCC; not tested 7.5 20 pF Ci(dif) Differential input capacitance VTxD =VCC; not tested 3.75 10 pF ILI(CANH) Input leakage current at pin CANH VCC =0V; VCANH = 5V 10 170 250 µA AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 10 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet Table 4: DC Characteristics (Continued) Symbol Parameter Conditions Min. Typ. Max. Unit Bus Lines (pins CANH and CANL) ILI(CANL) Input leakage current at pin CANL VCC =0V; VCANL = 5V 10 170 250 µA VCM-peak Common-mode peak du ring t ransition from dom → rec or rec → dom See Figure 8 and 9 -500 500 mV VCM-step Difference in common-mode between dominant and recessive state See Figure 8 and 9 -150 150 mV Power-on-Reset PORL POR level CANH, CA NL, Vref in tr i- state below POR level 2.2 3.5 4.7 V Thermal Shutdown Tj(sd) Shutdown junction temperature 140 160 190 °C Timing Characteristics (see Figure 6 and 7) td(TxD-BUSon) Delay TxD to bus active Vs = 0V 40 85 130 ns td(TxD-BUSoff) Delay TxD to bus inactive Vs = 0V 30 60 105 ns td(BUSon-RXD) Delay bus active to RxD Vs = 0V 25 55 105 ns td(BUSoff-RXD) Delay bus inactive to RxD Vs = 0V 65 100 155 ns tpd(rec-dom) Propagation d elay TxD to R xD f rom recessive to dominant Vs = 0V 70 230 ns td(dom-rec) Propagation del ay T xD to RxD from dominant to recessive Vs = 0V 100 245 ns tdom(TXD) TXD dominant time for time out VTxD = 0V 250 450 750 µs

8.5 Measurement Setups and Definitions

Schematics are given for single CAN transceiver. AMIS-42700 EN1 EN2 Text Rx0 Tx0 Rint CANH2 CANL1 GND VrefVCC 1312 PC20050502.5 CANL2 CANH1 100 nF +5V 56151617 1 nF 1 nF Transient Generator VRxD Vi(dif)(hys) High Low 0,5 0,9PC20040829.7 Hysteresis Figure 5: Hysteresis of the Receiver Figure 4: Test Circuit for Automotive Transients AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 11 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

9.0 Package Outline

SOIC-20: Plastic small outline; 20 leads; body width 300mil. AMIS reference: SOIC300 20 300 G AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 14 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

10.0 Soldering

10.1 Introduction to Sold ering Surface Mount Packages

This text giv es a ver y brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.

10.2 Re-flow Soldering

Re-flow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be a pplied to the pr inted- circuit board by screen-printing, stencilling or pressur e-syringe dispensing before package placement. Several me thods exist for re-flowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical re-flow peak temperatures range from 215 to 250°C. The top-surface temperature of the packages should preferably be kept below 230°C.

10.3 Wave Soldering

Conventional single wave soldering is n ot recommended for surface mount devices (SMDs) or printe d-circuit boards with a high component d ensity, as s older bridg ing and non- wetting c an present maj or prob lems. T o overcom e th ese pro blems the do uble- wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:

• Use a d ouble-wave s oldering meth od c omprising a turb ulent wave with hig h upward pressure fol lowed by a smo oth laminar wave.
• For packages with leads on two sides and a pitch (e): o Larger than or equal to 1.27mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; o Smaller th an 1.27mm, the fo otprint l ongitudinal axis must be p arallel to t he trans port di rection of the printed- circuit board. The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45º angle to the transport direction of the printed- circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fi xed with a droplet of ad hesive. The adhesive can be applied by screen-printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is four seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

10.4 Manual Soldering

Fix the component by first so ldering two diagonally-opposite end leads. Use a low voltage (24V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320°C. Table 11: Soldering Process Soldering Method Package Wave Re-flow(1) BGA, SQFP Not suitable Suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS Not suitable (2) Suitable PLCC (3) , SO, SOJ Suitable Suitable LQFP, QFP, TQFP Not recommended (3)(4) Suitable SSOP, TSSOP, VSO Not recommended (5) Suitable Notes: 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a ri sk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.” 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering i s considered, then the package must be plac ed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pi tch (e) equal to or larger than 0.65mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5mm. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 15 www.amis.com

AMIS-42700 Dual High-Speed CAN Transceiver Preliminary Data Sheet

11.0 Company or Pr oduct Inquiries

For more information about AMI Semiconductor, our technology and our product, visit our website at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or b y description, regarding the information set forth herein or regarding t he freedom of the described dev ices from patent infringement. AMI S makes no warranty of merchantability or fitness for any purposes. AMIS re serves the right to discontinue production and change specifications and prices at any time and w ithout notice. AM I Semi conductor's products are in tended f or use in commercial applications. App lications requiri ng extended t emperature range, unusual e nvironmental requ irements, or hi gh reliab ility applica tions, su ch as mili tary, medical li fe-support or life- sustaining eq uipment, are specifically not recommended without additional processing by AMIS for such applications. Copyright ©2005 AMI Semiconductor, Inc. AMI Semiconductor – Rev. 1.4, May 05 - Preliminary 16 www.amis.com