AMIS-30522

AMIS-30522 AMI | Alldatasheet

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AMIS-30522 Micro-stepping Motor Driver Data Sheet

1.0 Introduction

The AMIS-30522 is a micro-stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a SPI interface with an external microcontroller. It has an on-chip voltage regulator, reset-output and watchdog reset, able to supply peripheral devices. AMIS-30522 contains a current-trans lation table and takes the next micro-step depending on the clock sig nal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The chip provides a so-called “speed and load angle” output. This allows the cre ation of stal l d etection algorithms and c ontrol lo ops b ased on l oad-angle to adj ust torque a nd sp eed. It is using a proprietary PWM algorithm for reliable current control. The AMIS-30522 is implemented in I2T100 technology, enabling both high-voltage analog circuitry and digital functionality on the same chip. The chip is fully compatible with the automotive voltage requirements. The AMIS-30522 is id eally s uited for g eneral-purpose ste pper motor applications i n th e autom otive, i ndustrial, med ical, and m arine environment. With the on-chip voltage regulator it further reduces the BOM for mechatronic stepper applications.

2.0 Key Features

• Dual H-Bridge for 2-phase stepper motors
• Programmable peak-current up to 1.6A using a 5-bit current DAC
• On-chip current translator
• SPI interface
• Speed and load angle output
• Seven step modes from full step up to 32 micro-steps
• F ully integrated current-sense
• PWM current control with automatic selection of fast and slow decay
• Low EMC PWM with selectable voltage slopes
• Active fly-back diodes
• Full output protection and diagnosis
• Thermal warning and shutdown
• Compatible with 5V and 3.3V microcontrollers
• Integrated 5V regulator to supply external microcontroller
• Integrated reset function to reset external microcontroller
• Integrated watchdog function

3.0 Ordering information

Table 1: Ordering Information Part No. Package Peak Current Temp. Range Ordering Code Tubes Ordering Code Tapes AMIS-30522 ANA NQFP-32 (7 x 7mm) 1600mA -40°C… ..125°C 0C522-001-XTD 0C522-001-XTP AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

4.0 Block Diagram

Temp. Sense SPI OTP Timebase POR DI DO CS CLK NXT SLA DIR ERR Band- gap Load Angle AMIS-30522 Logic & Registers Chargepump T R A N S L A T O R Vreg CLR PC20070322.2 VBB P W M I-sense EMC P W M I-sense EMC VDD GND MOTXP MOTXN MOTYP MOTYN CPN CPP VCP POR/WD Figure 1: Block Diagram AMIS-30522

5.0 Pin Description

Table 2: Pin List and Description Name Pin Description DO 31 SPI data output VDD 32 Logic supply output (needs external decoupling capacitor) GND 1 Ground, heat sink DI 2 SPI data in CLK 3 SPI clock input NXT 4 Next micro-step input DIR 5 Direction input ERRB 6 Error output SLA 7 Speed load angle output CPN 9 Negative connection of charge pump capacitor CPP 10 Positive connection of charge pump capacitor VCP 11 Charge pump filter-capacitor CLR 12 “Clear” = chip reset input CSB 13 SPI chip select input VBB 14 High voltage supply Input MOTYP 15, 16 Negative end of phase Y coil output GND 17, 18 Ground, heat sink MOTYN 19, 20 Positive end of phase Y coil output MOTXN 21, 22 Positive end of phase X coil output GND 23, 24 Ground, heat sink MOTXP 25, 26 Negative end of phase X coil output VBB 27 High voltage supply input / 8, 30 No function (to be left open in normal operation) PORB/WD 28 Power-on-reset (POR)and watchdog reset output TSTO 29 Test pin input (to be tied to ground in normal operation) AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet 9 101 1 121 3 14 15 16 32 31 30 29 28 27 26 25 DO DI CPN MOTXP GND GND MOTXP MOTYN POR/WD MOTYP CLK VDD CLR CS DIR NXT SLA AMIS-30522 PC20070309.2 GND GND GND MOTYN MOTXN MOTXN MOTYP VBB TSTO CPP VCP VBB ERR Figure 2: Pin Out AMIS-30522

5.1 Package Thermal Characteristics

The NQFP is designed to provide superior thermal performance, and using an exposed die pad on the bottom surf ace of the p ackage partly contributes to this. In order to take full advantage of this thermal performance, the PCB must have features to conduct heat away from the package. A thermal grounded pad with thermal via’s can achieve this. With a layout as shown in Figure 3: PCB Ground Plane Layout Condition, the thermal resistance junction – to – ambient can be brought down to a level of 30°C/W. Figure 3: PCB Ground Plane Layout Condition NQFP-32 PC20041128.2 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

6.0 Electrical Specification

6.1 Absolute Maximum Ratings

Stresses above those listed in Table 3 may cause immediate and permanent device failure. It is not implied that more that one of these conditions can be applied simultaneously. Table 3: Absolute Maximum Ratings Symbol Parameter Min. Max. Units VBB Analog DC supply voltage (1) -0.3 +40 V Tstrg Storage temperature -55 +160 °C Tamb Ambient temperature under bias -50 +150 °C VESD Electrostatic discharges on component level (2) -2 +2 kV Notes: (1) For limited time <0.5s. (2) Human body model (100pF via 1.5 kΩ, according to JEDEC EIA-JESD22-A114-B).

6.2 Recommend Operation Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability. Table 4: Operating Ranges Symbol Parameter Min. Max. Units VBB Analog DC supply +6 +30 V VDD Logic supply output voltage (1) 4.75 5.25 V Iddd Dynamic current of VDD pin (internal and external loads) (2) 18 mA Ta Ambient temperature VBAT≤+18 -40 +125 °C Ta Ambient temperature VBAT≤+29 -40 +85 °C Tj Junction temperature +160 °C Notes: (1) Voltage output. (2) Dynamic current is with oscillator running, all analog cells active. All outputs unloaded, no floating inputs. AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

6.3 DC Parameters

The DC p arameters ar e g iven for V BB an d temp erature in t heir op erating r anges unless other wise specified. Co nvention: currents flowing in the circuit are defined as positive. Table 5: DC Parameters Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit Supply and Voltage Regulator VBB Nominal operating supply range 6 30 V IBB VBB Total internal current consumption Unloaded outputs 8 mA VDD Regulated output voltage 4.75 5 5.25 V IINT Internal load current Unloaded outputs 6V < VBB < 8V 20 ILOAD Max. output current (external and internal loads) 8V < VBB < 30V 50 IDDLIM Current limitation Pin shorted to ground 150 mA ILOAD_PD VDD Output current in power down 1 Power-on-Reset (POR) VDDH Internal POR comparator threshold VDD rising 4.0 4.25 4.4 V VDDL VDD Internal POR comparator threshold VDD falling 3.68 V Motordriver IMDmax,Peak Max current through motor coil in normal operation 1600 mA IMDmax,RMS Max RMS current through coil in normal operation 800 mA IMDabs Absolute error on coil current -10 10 % IMDrel Error on current ratio Icoilx / Icoily -7 7 % Vbb = 12V, Tj = 27 °C 0.45 0.56 Ω RHS On-resistance high-side driver, Vbb = 12V, Tj = 27 °C 0.45 0.56 Ω RLS3 On-resistance low-side driver, Vbb = 12V, Tj = 27 °C 0.90 1.2 Ω RLS2 On-resistance low-side driver, Vbb = 12V, Tj = 27 °C 1.8 2.3 Ω RLS1 On-resistance low-side driver, Vbb = 12V, Tj = 27 °C 3.6 4.5 Ω RLS0 On-resistance low-side driver, CUR[4:0] = 0...8 Vbb = 12V, Tj = 160 °C 7.5 10 Ω IMpd MOTXP MOTXN MOTYP MOTYN Pull-down current HiZ mode 0.5 mA Logic Inputs Ileak Input leakage (3) Tj = 160 °C 1 µA VinL Logic low threshold 1.5 V VinH DI, CLK NXT, DIR CLR, CSB Logic high threshold 3.5 V Rpd CLR TST0 Internal pull-down resistor 120 300 kΩ Thermal Warning and Shutdown Ttw Thermal warning 138 145 152 °C Ttsd (1) (2) Thermal shutdown Ttw + 20 °C Charge Pump 6V< VBB < 15V 2 * VBB – 2.5 V Vcp Output voltage 15V < VBB < 30V VBB+12.5 VBB+14 VBB+15.5 V Cbuffer VCP External buffer capacitor 180 220 470 nF Cpump CPP CPN External pump capacitor 180 220 470 nF Notes: (1) No more than 100 cumulated hours in life time above Ttw. (2) Thermal shutdown and low temperature warning are derived from thermal warning. (3) Not valid for pins with internal pull-down resistor. AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

6.4 AC Parameters

The AC parameters are given for VBB and temperature in their operating ranges. Table 6: AC Parameters Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit Internal Oscillator fosc Frequency of internal oscillator 3.6 4 4.4 MHz Motordriver PWM frequency 20.8 22.8 24.8 kHz fPWM Double PWM frequency Frequency depends only on internal oscillator 41.6 45.6 49.6 kHz fj PWM jitter frequency tbd Hz fd MOTxx PWM jitter Depth tbd % fPWM EMC[1:0] = 00 150 V/µs EMC[1:0] = 01 100 V/µs EMC[1:0] = 10 50 V/µs Tbrise MOTxx Turn-on voltage slope, 10% to 90% EMC[1:0] = 11 25 V/µs EMC[1:0] = 00 150 V/µs EMC[1:0] = 01 100 V/µs EMC[1:0] = 10 50 V/µs Tbfall MOTxx Turn-off voltage slope, 90% to 10% EMC[1:0] = 11 25 V/µs Digital Outputs TH2L DO ERRB Output fall-time from VinH to VinL Capacitive load 400pF a nd pull- up resistor of 1.5 kΩ 50 ns Charge Pump fCP CPN CPP Charge pump frequency 250 kHz TCPU MOTxx Start-up time of charge pump Spec external components CLR Function TCLR CLR Hard reset duration time 20 90 µs Power-Up tPU Power-up time VBB=12V, ILOAD=50mA, CLOAD=220nF 110 µs tPD Power-down time External conditions tbd ms tPOR Reset duration 100 ms tRF PORB/ WD Reset filter time 1 µs Watchdog tWDTO Watchdog time out interval 32 512 ms tWDPR Prohibited watchdog acknowledge delay 2 ms tWDRD PORB/ WD Watchdog reset delay tbd µs

6.5 SPI Timing

Table 7: SPI Timing Parameters Symbol Parameter Min. Typ. Max. Unit tCLK SPI clock period 1 µs tCLK_HIGH SPI clock high time 100 ns tCLK_LOW SPI clock low time 100 ns tSET_DI DI set up time, valid data before rising edge of CLK 50 ns tHOLD_DI DI hold time, hold data after rising edge of CLK 50 ns tCSB_HIGH CSB high time 2.5 µs tSET_CSB CSB set up time, CSB low before rising edge of CLK 100 ns tSET_CLK CLK set up time, CLK low before rising edge of CSB 100 ns AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet DI VALID CLK tSET_CSB PC20070608.1 CS tCLK tCLK_HI tCLK_LO tSET_DI tHOLD_DI tSET_CLK 0,2 VCC 0,8 VCC 0,2 VCC0,2 VCC 0,2 VCC 0,8 VCC Figure 4: SPI Timing

7.0 Typical Application Schematic

PC20070604.10 VCP CPP CPN CLR GND CLK DI DO NXT DIR MOTXP MOTXN MOTYP MOTYN M 220 nF 100 nF VBAT VDD VBBVBB 100 nF 220 nF 100 µF C2 C3 100 nF100 nF SLA µC POR/WD CS ERR Figure 5: Typical Application Schematic AMIS-30522 Table 8: External Components List and Description Component Function Typ. Value Tolerance Unit C1 VBB buffer capacitor (1) 100 -20 +80% µF C2, C3 VBB decoupling block capacitor 100 -20 +80% nF C4 VDD buffer capacitor 220 +/- 20 % nF C5 VDD buffer capacitor 100 +/- 20% nF C6 Charge-pump buffer capacitor 220 +/- 20% nF C7 Charge-pump pumping capacitor 220 +/- 20% nF C8 Low pass filter SLA 1 +/- 20% nF R1 Low pass filter SLA 5.6 +/- 1% kΩ D1 Optional reverse protection diode e.g. 1N4003 Notes: 1. Low ESR < 1Ohm. AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

8.0 Functional Description

8.1 H-Bridge Drivers

A full H- bridge is inte grated for eac h of the t wo stator windings. Eac h H-bridge c onsists of t wo low-side and t wo high-side N-t ype MOSFET s witches. Writing lo gic ‘0’ in bit <MOTEN> disables a ll driv ers (high- impedance). W riting l ogic ‘1’ in this bit ena bles both bridges and current can flow in the motor stator windings. In order to avoid lar ge currents through th e H-bridge s witches, it is guarantee d that t he top- and bottom-switches of the s ame half- bridge are never conductive simultaneously (interlock delay). A two-stage protection against shorts on m otor lines is im plemented. In a first stage, the current in t he driver is l imited. Secondly, when excessive voltage is sensed across the transistor, the transistor is switched off. In order to re duce the ra diated/conducted emission, voltage slope control is impl emented in the output switches. The output sl ope is defined by the gate-drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for slope control (Table 27: SPI Control Parameter Overview EMC[1:0]). The power transistors are equipped with so-called “active diodes”: when a current is for ced trough the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain-bulk diode of the transistor. Depending on the desired current range and the micro-step position at hand, the Rdson of the low-side transistors will be adapted such that e xcellent current-sense accuracy is m aintained. T he Rdson of th e hi gh-side tra nsistors rem ain u nchanged, see Table 5: DC Parameters for more details.

8.2 PWM Current Control

A PWM comparator compares continuously the actual winding current with the r equested current and feeds back the information to a digital regulation loop. This loop then g enerates a PW M signal, which turns on/off the H-bridg e switches. The switching points of the PWM duty-cycle are synchronized to the on-chip PWM clock. The frequency of the PWM controller can be doubled and an artificial jitter can be added (Table 16: SPI Control Register 1). The PWM frequency will not vary with changes in the supply voltage. Also variations in motor-s peed or l oad-conditions of the motor hav e n o effect. T here are no e xternal c omponents requ ired to ad just the PWM frequency. 8.2.1. Automatic Forward and Slow-Fast Decay The PW M gen eration is in st eady-state usi ng a comb ination of for ward and slo w-decay. T he a bsence of fast-dec ay in this m ode, guarantees the lowest possible current-ripple “by design”. For transients to lower current levels, fast-decay is automatically activated to allow high-speed response. The selection of fast or slow decay is completely transparent for the user and no a dditional parameters are required for operation. Icoil 0 t Forward & Slow Decay Forward & Slow Decay Fast Decay & Forward Actual value Set value TPWM PC20070604.1 Figure 6: Forward and Slow/Fast Decay PWM AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet 8.2.2. Automatic Duty Cycle Adaptation In case the su pply voltage is lower than 2*Bemf, then the duty cycle of the PW M is adapte d automatically to > 50% to maintai n the requested average current in the coils. This process is completely automatic and requires no additional parameters for operation. The over-all current-ripple is divided by two if PWM frequency is doubled (Table 16: SPI Control Register 1). Actual value Duty Cycle < 50% Duty Cycle >50% Duty Cycle < 50% t Icoil Set value TPWM PC20070604.2 Figure 7: Automatic Duty Cycle Adaption

8.3 Step Translator

8.3.1. Step Mode The step translator provi des the control of the motor b y means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL, and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One o ut of s even possible s tepping m odes can be sel ected thr ough SP I-bits SM[2:0] (Table 28: SPI Co ntrol P arameter Overvi ew SM[2:0]) After power-on or hard reset, the coil-current translator is set to the default 1/32 micro-stepping at position ‘0’. Upon changing the step m ode, the transl ator jumps to pos ition 0* of th e corresponding stepping m ode. W hen rema ining in the s ame step mo de, subsequent translator positions are all in the same column and increased or decreased with 1. Table 10 lists the output current vs. the translator position. As shown in Figure 8 the output current-pairs can b e projected approximately on a c ircle in the (I x,Iy) plane. There is, however, one exception: uncompensated half step. In this step m ode the currents are not regulated to a fr action of Imax but are in all intermediate steps regulated at 100 percent. In the (Ix,Iy) plane the current-pairs are projected on a square. Table 9 lists th e output current vs. t he translator position for this case. Table 9: Square Translator Table for Uncompensated Half Step SM[2:0] = 101 Stepmode ( SM[2:0] ) % of Imax 101 Uncompensated Half Step Coil x Coil y 0* 0 100 1 100 100 2 100 0 3 100 -100 4 0 -100 5 -100 -100 6 -100 0 7 -100 100 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet Table 10: Circular Translator Table Stepmode ( SM[2:0] ) % of Imax Stepmode ( SM[2:0] ) % of Imax 000 001 010 011 100 110 000 001 010 011 100 110 1/32 1/16 1/8 1/4 1/2 FS Coil x Coil y 1/32 1/16 1/8 1/4 1/2 FS Coil x Coil y ‘0’ 0* 0* 0* 0* - 0 100 64 32 16 8 4 - 0 -100 4 2 1 - - - 17.4 95.3 68 34 17 - - - -17.4 -95.3 8 4 2 1 - - 34.9 89.5 72 36 18 9 - - -34.9 -89.5 12 6 3 - - - 50 79 76 38 19 - - - -50 -79 16 8 4 2 1 1 65.1 65.1 80 40 20 10 5 3 -65.1 -65.1 20 10 5 - - - 79 50 84 42 21 - - - -79 -50 24 12 6 3 - - 89.5 34.9 88 44 22 11 - - -89.5 -34.9 28 14 7 - - - 95.3 17.4 92 46 23 - - - -95.3 -17.4 32 16 8 4 2 - 100 0 96 48 24 12 6 - -100 0 36 18 9 - - - 95.3 -17.4 100 50 25 - - - -95.3 17.4 40 20 10 5 - - 89.5 -34.9 104 52 26 13 - - -89.5 34.9 44 22 11 - - - 79 -50 108 54 27 - - - -79 50 48 24 12 6 3 2 65.1 -65.1 112 56 28 14 7 0* -65.1 65.1 52 26 13 - - - 50 -79 116 58 29 - - - -50 79 56 28 14 7 - - 34.9 -89.5 120 60 30 15 - - -34.9 89.5 60 30 15 - - - 17.4 -95.3 124 62 31 - - - -17.4 95.3 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

8.4 Programmable Peak-Current

The amplitud e of the current waveform in the motor coil s (coil pe ak c urrent = Imax) is adjuste d by me ans of a n SPI paramet er "CUR[4:0]" (Table 15: SPI Co ntrol Register 0). Whenever this p arameter is changed, the coil-currents will be upd ated immediately at the next PWM period. More information can be found in Table 26: SPI Control Parameter Overview CUR[4:0].

8.5 Speed and Load Angle Output

sampled during every so-called "coil current zero crossings". Per coil, two zero-current positions exist per electrical period, yielding in total four zero-current observation points per electrical period. VBEMF ZOOM t VBB VCOIL Voltage Transient Next Micro-step Previous Micro-step Coil Current Zero Crossing Current Decay Zero Current t t PC20070604.7 ICOIL ICOIL VBEMF Figure 12: Principle of Bemf Measurement Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. As this transient is not al ways desired in application software, two operating modes can be selected by means of the bit <SLAT> (see "SLA-transparency" in Table 17: SPI Control Register 2). The SLA pin shows in "transparent mode" full visibility of the voltage transient behavior. This allows a sanity-check of the speed-setting versus motor operation and characteristics and supply voltage levels. If the bit “SLAT” is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA-pin. Because the by software. In order to bring the sampled Back e.m.f. to a descent output level (0 to 5V), the sampled coil voltage VCOIL is divided by 2 or by 4. This divider is set through an SPI bit <SLAG>. (Table 17: SPI Control Register 2) Table 12: Parameter Table SLA Pin Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit Vout Output voltage range 0.5 4.5 V Voff Output offset the SLA pin 0.2V < Vsla < Vdd – 0.2V -20 20 mV Rout Output resistance SLA pin 1 kΩ Cload Load capacitance SLA pin 50 pF Gsla SLA Gain of SLA pin = VBEMF / VCOIL SLAG=0 SLAG=1 0.5 0.25 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil=0" are internal signals that define together with SLAT the sampling and hold moments of the coil voltage. PWMsh Icoil=0 SLAT SLA-pin SLAT=0 => SLA-pin is not "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated when leaving current-less state. SLAT=1 => SLA-pin is "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated "real-time". last sample is retained retain last sample previous output is kept at SLA pin buf Ssh Sh ChCsh SLAT NOT(Icoil=0) Icoil=0 PWMsh SLA-pinVCOIL div2 div4 VBEMF t t PC20070604.8 VCOIL Figure 13: Timing Diagram of SLA-pin

8.6 Warning, Error Detection and Diagnostics Feedback

8.6.1. Thermal Warning and Shutdown When ju nction temperatur e rises ab ove T TW, the therma l warning b it <TW> is set ( Table 29: SPI Status Reg ister 0 ). If junction temperature i ncreases above thermal shutdown level, the n the c ircuit goes i n “Thermal Sh utdown” mode ( <TSD>) an d al l dr iver transistors are dis abled (hi gh im pedance) ( Table 31: S PI Status R egister 2 ). T he conditions to r eset fla g <TSD> i s t o b e at a temperature lower than TTW and to clear the <TSD> flag by reading it using any SPI read command. 8.6.2. Over-Current Detection The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current detection threshold, then the over-current flag is set and the drivers are s witched off to reduce the power dissipation and to protect the integrated circuit. Ea ch driv er trans istor has an individual detect ion bit in AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet Table 30: SPI Status Register 1 and (Table 31: SPI Status Register 2 (<OVCXij> and <OVCYij>). Error condition is latched and the microcontroller needs to clean the status bits to reactivate the drivers. 8.6.3. Open Coil Detection Open coil detection is based on the observation of 100 percent duty cycle of the PW M regulator. If in a coil 100 percent duty cycle is detected for l onger t han 20 0ms then th e r elated dr iver tr ansistors are disabled (h igh-impedance) a nd an a ppropriate bit i n the SPI status register is set (<OPENX> or <OPENY>). (Table 29: SPI Status Register 0) 8.6.4. Charge Pump Failure The charge pump is an important circuit that guarantees low Rdson for all drivers, especially for low supply voltages. If supply voltage is too low or external components are not properly connected to guarantee Rdson of the drivers, then the bit <CPFAIL> is set in Table 29: SPI Status Register 0. Also after POR the charge pump voltage will need some time to exceed the required threshold. During that time <CPFAIL> will be set to “1”. 8.6.5. Error Output This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL>

8.7 Logic Supply Regulator

AMIS-30522 has an on-chip 5V low-drop regulator with external capacitor to supply the digital part of the chip, some low-voltage analog blocks and external circuitry. The voltage is derived from an internal bandgap reference. To calculate the available drive-current for external circu itry, the sp ecified I load shoul d be re duced with the cons umption of inte rnal circu itry (u nloaded o utputs) and the loads connected to logic outputs. See Table 5.

8.8 Power-On Reset (POR) Function

The open drain output pin PORB/WD provides an “active low” reset for external purposes. At power-up of AMIS-30522, this pin will be kept low for some time to reset for example an external microcontroller. A small analog filter avoids resetting due to spikes or noise on the VDD supply. tPU tPOR tRF PC20070604.8 VBB VDDH VDD VDDL tPD < tRF t t POR/WD pin Figure 14: Power-on-Reset Timing Diagram

8.9 Watchdog Function

The watchdog function is enabled/disabled through <WDEN> bit (Table 14: SPI Control Register WR). Once this bit has been set to “1” (watchdog enable), the microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires. AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet In case the timer is activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then a reset of the micr ocontroller will occur throu gh POR B/WD pin. In add ition, a warm/cold boot b it <WD> is ava ilable in Table 29: SPI Status Register 0 for further processing when the external microcontroller is alive again. tPU POR/WD pin tPOR PC20070604.9 VBB VDDH VDD t t tDSPI Enable WD Acknowledge WD WD timer tPORtWDRD = tWDPR or = tWDTO > tWDPR and < tWDTO t t tWDTO Figure 15: Watchdog Timing Diagram Note: tDSPI is the time needed by the external microcontroller to shift-in the <WDEN> bit after a power-up. The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (Table 14: SPI Control R egister WR). The timing is given in Table 13. Table 13: Watchdog Timeout Interval as Function of WDT[3.0] Index WDT[3:0] tWDTO (ms) 0 0 0 0 0 32 1 0 0 0 1 64 2 0 0 1 0 96 3 0 0 1 1 128 4 0 1 0 0 160 5 0 1 0 1 192 6 0 1 1 0 224 7 0 1 1 1 256 8 1 0 0 0 288 9 1 0 0 1 320 A 1 0 1 0 352 B 1 0 1 1 384 C 1 1 0 0 416 D 1 1 0 1 448 E 1 1 1 0 480 F 1 1 1 1 512 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

8.10 CLR pin (=Hard Reset)

Logic 0 on CLR pin allows normal operation of the c hip. To reset the complete digital inside AMIS-30522, the i nput CLR needs to be pulled to logic 1 during minimum time given by TCLR. (Table 6: AC Parame ters). This reset function clear s all internal registers without the need of a po wer-cycle. The operation of all anal og circuits is depending on the re set state of the digital, charge pump rem ains active. Logic 0 on CLR pin resumes normal operation again. The voltage regulator remains functional during and after the reset and the PORB/WD pin is not activated. Watchdog function is reset completely.

8.11 Sleep Mode

The bit <SLP> in Table 17: SPI Control Register 2 is provided to enter a so-called “sleep mode”. This mode allows reduction of current- consumption when the motor is not in operation. The effect of sleep mode is as follows:

• The drivers are put in HiZ
• All analog circuits are disabled and in low-power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current increase during SPI communication)
• Reset of chip is possible through CLR pin
• Oscillator and digital clocks are silent, except during SPI communication The voltage regulator remains active but with reduced current-output capability (ILOADSLP). The watchdog timer stops running and it’s value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. Normal operation is resume d after writing logic ‘0’ to bit <SLP>. A start-up time is nee ded for the ch arge pump to stabiliz e. After this time, NXT commands can be issued. AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

9.0 SPI Interface

The serial peripheral interface (SPI) is used to allow external microcontroller (MCU) to communicate with the device. The implemented SPI block is fle xible enough to interface directly with numerous microcontrollers from several manufacturers. AMIS-30522 acts always as a sl ave and it can’t initiate any transmission. The operation of the device is co nfigured and controlled by means of SPI reg isters, which are observable for read and/or write from the master.

9.1 SPI Transfer Format and Pin Signals

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). DO s ignal is the output from the slave, and DI signal is the o utput from the mast er. A slave s elect line ( CSB) allows individual selection of a slave SPI device in a multiple- slave system. The CSB line is active lo w. If AMIS-30522 is not selected, DO is in high i mpedance state and it does n ot interfere with SPI bus activities. Since AMI S-30522 always clocks data out on the falling edge and samples data in on rising edge of clock, the MCU SPI port must be configured to match this operation. SPI clock idles low between the transferred bytes. The diagram below is both a master and a slave timing diagram since CLK, DO and DI pins are directly connected between the master and the slave. 8 7 6 5 4 3 2 1 MS B 6 5 4 3 2 1 LSB MS B 6 5 4 3 2 1 LSB CLK (Idles Low) DI (From Master) DO (From Slave) CSB (1) Note (1): MSB of data stored on the new address (see Transfer packet). The internal data-out shift buffer of AMIS-30522 is updated with new content only at the last (every eighth) falling edge of the CLK signal. Figure 16: Timing Diagram of an SPI Transfer

9.2 Transfer Packet

Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more 8-bit characters (bytes). MSB LSB Command and Address MSB LSB Data byte Cmd2 Cmd1 Cmd0 Addr4 Addr3 Addr2 Addr1 Addr0 Data7 - Data0 The first byte contains command and SPI register address and will be sent upfront of the packet to indicate to AMIS-30522 the chosen register and the type of operation. There are two possible commands for the master in normal operation mode of AMIS-30522:

• READ from SPI register: Cmd2 = 0
• WRITE to SPI register: Cmd2 = 1 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

9.3 SPI Control Registers

All SPI control registers have Read/Write Access and default to "0" after power-on or hard reset. Table 14: SPI Control Register WR Control Register (WR) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 00h Data WDEN WDT[3:0] - - - Where: R/W Read and Write access Reset: Status after power-On or hard reset WDEN: Watchdog enable. Writing “1” to this bit will activate the watchdog timer (if not enabled yet) or will clear this timer (if already enabled). Writing “0” to this bit will clear WD bit (Table 29: SPI Status Register 0). WDT[3:0]: Watchdog timeout interval Table 15: SPI Control Register 0 Control Register 0 (CR0) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 01h Data SM[2:0] CUR[4:0] Where: R/W Read and Write access Reset: Status after power-On or hard reset SM[2:0]: Step mode CUR[4:0]: Current amplitude Table 16: SPI Control Register 1 Control Register 1 (CR1) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 02h Data DIRCTRL NXTP - - PWMF PWMJ EMC[1:0] Where: R/W Read and Write access Reset:: Status after power-On or hard reset DIRCTRL Directio n control NXTP NEXT polarity PWMF PWM frequency PWMJ PWM jitter EMC[1:0] EMC slope control Table 17: SPI Control Register 2 Control Register 2 (CR2) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 03h Data MOTEN SLP SLAG SLAT - - - - Where: R/W Read and Write access Reset: Status after power-On or hard reset MOTEN Motor enable SLP Sleep SLAG Speed load angle gain SLAT Speed load angle transparency AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet Table 18: SPI Control Parameter Overview SLAT Symbol Description Status Behavior <SLAT> = 0 SLA is transparent SLAT Speed load angle transparency bit <SLAT> = 1 SLA is NOT transparent Table 19: SPI Control Parameter Overview SLAG Symbol Description Status Value <SLAG> = 0 Gain = 0.5 SLAG Speed load angle gain setting <SLAG> = 1 Gain = 0.25 Table 20: SPI Parameter Overview PWMF Symbol Description Status Value <PWMF> = 0 fPWM = 22.8kHz PWMF Enables doubling of the PWM frequency <PWMF> = 1 fPWM = 45.6kHz Table 21: SPI Control Parameter Overview PWMJ Symbol Description Status Behavior <PWMJ> = 0 Jitter disabled PWMJ Enables jittery PWM <PWMJ> = 1 Jitter enabled Table 22: SPI Control Overview SLP Symbol Description Status Behavior <SLP> = 0 Active mode SLP Enables sleep mode <SLP> = 1 Sleep mode Table 23: SPI Control Parameter Overview MOTEN Symbol Description Status Value <MOTEN> = 0 Drivers disabled MOTEN Activates the motor driver outputs <MOTEN> = 1 Drivers enabled Table 24: SPI Control Parameter Overview DIRCTRL Symbol Description Status Value <DIRCTRL> = 0 CW motion <DIR> = 0 <DIRCTRL> = 1 CCW motion <DIRCTRL> = 0 CCW motion DIRCTRL Controls the direction of rotation (in combination with logic level on input DIR) <DIR> = 1 <DIRCTRL> = 1 CW motion Table 25: SPI Control Parameter Overview NXTP Symbol Description Status Value <NXTP> = 0 Trigger on rising edge NXTP Selects if NXT triggers on rising or falling edge <NXTP> = 1 Trigger on falling edge CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 26: SPI Control Parameter Overview CUR[4:0] Index CUR[4:0] Current (mA) Index CUR[4:0] Current (mA) 0 0 0 0 0 0 30 10 1 0 0 0 0 365 1 0 0 0 0 1 60 11 1 0 0 0 1 400 2 0 0 0 1 0 90 12 1 0 0 1 0 440 3 0 0 0 1 1 100 13 1 0 0 1 1 485 4 0 0 1 0 0 110 14 1 0 1 0 0 535 5 0 0 1 0 1 120 15 1 0 1 0 1 595 6 0 0 1 1 0 135 16 1 0 1 1 0 650 7 0 0 1 1 1 150 17 1 0 1 1 1 725 8 0 1 0 0 0 160 18 1 1 0 0 0 800 9 0 1 0 0 1 180 19 1 1 0 0 1 885 A 0 1 0 1 0 200 1A 1 1 0 1 0 970 B 0 1 0 1 1 220 1B 1 1 0 1 1 1070 C 0 1 1 0 0 240 1C 1 1 1 0 0 1190 D 0 1 1 0 1 270 1D 1 1 1 0 1 1300 E 0 1 1 1 0 300 1E 1 1 1 1 0 1450 F 0 1 1 1 1 325 1F 1 1 1 1 1 1600 AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet EMC[1:0] Adjusts the dV/dt of the PWM voltage slopes on the motor pins. Table 27: SPI Control Parameter Overview EMC[1:0] Index EMC[1:0] Slope (V/µs) Remark 0 0 0 150 Turn-on and turn-off voltage slope 10% to 90% 1 0 1 100 “ 2 1 0 50 “ 3 1 1 25 “ SM[2:0] Selects the micro-stepping mode. Table 28: SPI Control Parameter Overview SM[2:0] Index SM[2:0] Step Mode Remark 0 0 0 0 /32 Micro-step 1 0 0 1 /16 Micro-step 2 0 1 0 /8 Micro-step 3 0 1 1 ¼ Micro-step 4 1 0 0 ½ Uncompensated half-step 5 1 0 1 ½ Compensated half-step 6 1 1 0 Full Full step 7 1 1 1 N/A For future use

9.4 SPI Status Register Description

All four SPI status registers have Read Access and are default to "0" after power-on or hard reset. Table 29: SPI Status Register 0 Status Register 0 (SR0) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 04h Data PAR TW CPfail WD(1) OPENX OPENY - - Where: R Read only mode access Reset Status after power-on or hard reset PAR Parity check TW Thermal warning Cpfail Charge pump failure WD Watchdog event OPENX Open Coil X detected OPENY Open Coil Y detected Remark: WD(1) – This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset, it means that a watchdog reset occ urred (warm boot) instead of POR (cold bo ot). WD bit will be cleared only when the master writes “0” to WDEN bit. Table 14: SPI Control Register WR. Data is not latched AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet Table 30: SPI Status Register 1 Status Register 1 (SR1) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 05h Data PAR OVCXPT OVCXPB OVCXNT OVCXNB - - - Where: R Read only mode access Reset Status after power-on or hard reset PAR Parity check OVXPT Over-current detected on X H-bridge: MOTXP terminal, top transistor OVXPB Over-current detected on X H-bridge: MOTXP terminal, bottom transistor OVXNT Over-current detected on X H-bridge: MOTXN terminal, top transistor OVXNB Over-current detected on X H-bridge: MOTXN terminal, bottom transistor Remark: Data is latched Table 31: SPI Status Register 2 Status Register 2 (SR2) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 06h Data PAR OVCYPT OVCYPB OVCYYNT OVCYNB TSD - - Where: R Read only mode access Reset Status after power-on or hard reset PAR Parity check OVCYPT Over-current detected on Y H-bridge: MOTYP terminal, top transistor OVCYPB Over-current detected on Y H-bridge: MOTYP terminal, bottom transistor OVCYNT Over-current detected on Y H-bridge: MOTYN terminal, top transistor OVCYNB Over-current detected on Y H-bridge: MOTYN terminal, bottom transistor TSD Thermal shutdown Remark: Data is latched Table 32: SPI Status Register 3 Status Register 3 (SR3) Address Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 07h Data PAR MSP[6:0] Where: R Read only mode access Reset Status after power-on or hard reset PAR Parity check MSP[6:0] Translator micro-step position Remark: Data is not latched AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet Table 33: SPI Status Flags Overview Flag Mnemonic Length (bit) Related SPI Register Comment Reset State Charge pump failure CPFail 1 Status Register 0 ‘0’ = no failure ‘1’ = failure: indicates that the charge pump does not reach the required voltage level. Note 1 ‘0’ Micro-step position MSP[6:0] 7 Status Register 3 Translator micro step position ‘0000000’ OPEN Coil X OPENX 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OPEN Coil Y OPENY 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OVer Current on X H-bridge; MOTXN terminal; Bottom tran. OVCXNB 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at bottom transistor XN-terminal ‘0’ OVer Current on X H-bridge; MOTXN terminal; Top transist. OVCXNT 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at top transistor XN-terminal ‘0’ OVer Current on X H-bridge; MOTXP terminal; Bottom tran. OVCXPB 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at bottom transistor XP-terminal ‘0’ OVer Current on X H-bridge; MOTXP terminal; Top transist. OVCXPT 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at top transistor XP-terminal ‘0’ OVer Current on Y H-bridge; MOTYN terminal; Bottom tran. OVCYNB 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at bottom transistor YN-terminal ‘0’ OVer Current on Y H-bridge; MOTYN terminal; Top transist. OVCYNT 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at top transistor YN-terminal ‘0’ OVer Current on Y H-bridge; MOTYP terminal; Bottom tran. OVCYPB 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at bottom transistor YP-terminal ‘0’ OVer Current on Y H-bridge; MOTYP terminal; Top transist. OVCYPT 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that o ver current is detected at top transistor YP-terminal ‘0’ Thermal shutdown TSD 1 Status Register 2 ‘0’ Thermal warning TW 1 Status Register 0 ‘0’ Watchdog event WD 1 Status Register 0 ‘1’ = watchdog reset after time-out ‘0’ AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

10.0 Package Outline

Dimensions: Dim Min Nom Max Unit A 0.8 0.9 mm A1 0 0.02 0.05 mm A2 0.576 0.615 0.654 mm A3 0.203 mm b 0.25 0.3 0.35 mm C 0.24 0.42 0.6 mm D 7 mm D1 6.75 mm E 7 mm E1 6.75 mm e 0.65 mm J 5.37 5.47 5.57 mm K 5.37 5.47 5.57 mm L 0.35 0.4 0.45 mm P 45 Degree R 2.185 2.385 mm Notes : 2 Dimensions apply to plated terminal and are measured between 0.2 and 0.25 mm from terminal tip.

3 The pin #1 indication must be placed on the top surface of the pa ckage

by using indentation mark or other feature of package body.

4 Exact shape and size of this feature is optional

5 Applied for exposed pad and termi nals. Excl ude embe dding part of exposed pad from measuring.

6 Applied only to terminals

7 Exact shape of each corner is optional

Figure 20: NQFP-32: No Lead Quad Flat Pack; 32 Pins; Body Size 7x7mm (AMIS Reference: NQFP-32) AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

11.0 Soldering

11.1 Introduction to Soldering Surface Mount Packages

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surfac e mount ICs, or for printed-circuit boards (PCB) with high population densities. In these situations re-flow soldering is often used.

11.2 Re-flow Soldering

Re-flow soldering re quires s older paste (a s uspension of fine s older p articles, flux and binding a gent) to be a pplied to the P CB b y screen pr inting, stencill ing or pressur e-syringe disp ensing bef ore p ackage p lacement. Several m ethods exist for re-flo wing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on the heating method. Typical re- flow peak temperatures range from 215 to 260°C. The top-surface temperature of the packages should preferably be kept below 230°C.

11.3 Wave Soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or PCBs with a high component density, as solder bridging and non-wetting can present major pr oblems. To overcome these problems, the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
• Larger than or equal to 1.27mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the PCB;
• Smaller than 1.27mm, the footprint lon gitudinal axis must be par allel to the transp ort direction of the PCB. The footprint must incorporate solder thieves at the downstream end.
• For packa ges with l eads on four sid es, th e footprint m ust be p laced at a 45º angle to the trans port direction of th e PCB. T he footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is four seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

11.4 Manual Soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320°C. Table 34: Soldering Process Soldering Method Package Wave Re-flow (1) BGA, SQFP Not suitable Suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS Not suitable (2) Suitable PLCC (3) , SO, SOJ Suitable Suitable LQFP, QFP, TQFP Not recommended (3) (4) Suitable SSOP, TSSOP, VSO Not recommended (5) Suitable Notes: (1) All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.” (2) These packages are not suitable for wave soldering as a solder joint between the PCB and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). (3) If wave soldering is considered, then the package must be pl aced at a 45° angle t o the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. (4) Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm. (5) Wave soldering is only suitable for SSOP and TSSOP packages with a pitc h (e) equal to or l arger than 0.65mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5mm. AMI Semiconductor – June 2007, M-20684-001 www.amis.com

AMIS-30522 Micro-stepping Motor Driver Data Sheet

12.0 Company or Product Inquiries

For more information about AMI Semiconductor’s products or services visit our Web site at http://www.amis.com.

13.0 Document History

Table 35: Revision History Version Date Modification 0.1 18-jan-06 initial draft 0.2 24-jan-06 draft : changed PWM description, added SLA pin description, changed POR and WD paragraphs. 0.4 9-mar-06 updated pin-out & added drawing, CENB->CLR, ERR->ERRB, removed SWP bits, updated SPI bits, added package details 0.5 22-mar-06 Renamed CS -> CSB, Swapped pins CLR and CSB 0.6 24-may-06 Updated pins, AC&DC tables, SLA specs, SM[2:0] decoding 1.0 6-june-07 Final version derived from common 30521/30522 datasheet Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of merchantability or f itness for any purposes. AM IS reserves the right to discontinue production and c hange specifications and p rices at any time and without notice. AM I Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as m ilitary, medical life-support or lif e-sustaining equipment, are speci fically not recommended without additional processing by AM IS for such applications. Copyright ©2007 AMI Semiconductor, Inc. AMI Semiconductor – June 2007, M-20684-001 www.amis.com