AMD27C256

AMD27C256 AMD | Alldatasheet

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Publication# 08007 Rev. H Amendment /0 Issue Date: May 19952-32 Advanced Micro Devices Am27C256

256 Kilobit (32,768 x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS ■ Fast access time — 55 ns ■ Low power consumption — 20 mA typical CMOS standby current ■ JEDEC-approved pinout ■ Single +5 V power supply ■ –10% power supply tolerance available ■ 100% Flashrite programming — Typical programming time of 4 seconds ■ Latch-up protected to 100 mA from –1 V to VCC + 1 V ■ High noise immunity ■ Versatile features for simple interfacing — Both CMOS and TTL input/output compatibility — Two line control functions ■ Standard 28-pin DIP, PDIP, 32-pin TSOP and PLCC packages GENERAL DESCRIPTION The Am27C256 is a 256K-bit ultraviolet erasable pro- grammable read-only memory. It is organized as 32K words by 8 bits per word, operates from a single +5 V supply, has a static standby mode, and features fast sin- gle address location programming. Products are avail- able in windowed ceramic DIP packages as well as plas- tic one time programmable (OTP) PDIP, TSOP, and PLCC packages. Typically, any byte can be accessed in less than 55 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27C256 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 80 mW in active mode, and 100 mW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C256 supports AMD’s Flashrite programming algorithm (100 ms pulses) resulting in typi- cal programming time of 4 seconds. BLOCK DIAGRAM VCC VSS Output Enable Chip Enable and Prog Logic Y Decoder X Decoder CE OE Output Buffers Y Gating 262,144 Bit Cell Matrix A0–A14 Address Inputs Data Outputs DQ0–DQ7 08007H-1 VPP

Family Part No. Am27C256 Ordering Part No: VCC – 5% -255 VCC – 10% -55 -70 -90 -120 -150 -200 Max Access Time (ns) 55 70 90 120 150 200 250 CE (E) Access Time (ns) 55 70 90 120 150 200 250 OE (G) Access Time (ns) 35 40 40 50 50 50 50 CONNECTION DIAGRAMS Top View DIP Notes: 1. JEDEC nomenclature is in parentheses. PLCC VPP VCC A11 A12 A14 DQ7 V SS DQ2 DQ1 DQ0 OE (G) A10 CE (E) DQ6 DQ5 DQ4 DQ3 A13 08007H-2 08007H-3 13 1 3 0234 17 18 19 20161514 NC DQ0 A11 NC OE (G) A10 CE (E) DQ7 A12 VPP DU VCC A14 A13 DQ1 DQ2 VSS DU DQ3 DQ4 DQ5 DQ6

TSOP* 08007H-4 *Contact local AMD sales office for package availability OE (G) A11 A13 NC A14 VCC VPP NC A12 NC A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 VSS DQ1 DQ0 NC Standard Pinout LOGIC SYMBOLPIN DESIGNATIONS A0–A14 CE (E) OE (G) DQ0–DQ7 A0–A14 = Address Inputs CE (E) = Chip Enable DQ0–DQ7 = Data Inputs/Outputs OE (G) = Output Enable Input VCC =V CC Supply Voltage VPP = Program Voltage Input VSS = Ground DU = Don’t Use 08007H-5

ORDERING INFORMATION

256 Kilobit (32,768 x 8-Bit) CMOS UV EPROM

D = 28-Pin Ceramic DIP (CDV028) Valid Combinations AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: BCD-55AM27C256 OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended Commercial (–55°C to +125°C) SPEED OPTION See Product Selector Guide and Valid Combinations AM27C256-55 AM27C256-70 DC, DCB, DI, DIB AM27C256-90 AM27C256-120 AM27C256-150 AM27C256-200 AM27C256-255 DC, DCB, DI, DIB, DE, DEB Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DC, DCB, DI, DIB

256 Kilobit (32,768 x 8-Bit) CMOS OTP EPROM

P = 28-Pin Plastic DIP (PD 028) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin TSOP (TS 032) AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: CP-55AM27C256 OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to + 85°C) SPEED OPTION See Product Selector Guide and Valid Combinations JC, PC, EC, JI, PI, EI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. JC, PC, EC

In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27C256 to an ultraviolet light source. A dosage of 15 W sec/cm 2 is required to completely erase an Am27C256. This dos- age can be obtained by exposure to an ultraviolet amp— wavelength of 2537 A°—with intensity of 12,000 mW/cm for 15 to 20 minutes. The Am27C256 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27C256 and similar devices will erase with light sources having wavelengths shorter than 4000 A°. Although erasure times will be much longer than with UV sources at 2537 A°, exposure to fluorescent light and sunlight will eventually erase the Am27C256 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C256 Upon delivery or after each erasure the Am27C256 has all 262,144 bits in the “ONE” or HIGH state. “ZEROs” are loaded into the Am27C256 through the procedure of programming. The programming mode is entered when 12.75 V – 0.25 V is applied to the V PP pin, OE is at VIH, and CE is at VIL. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 ms programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27C256. This part of the algorithm is done at V CC = 6.25 V to assure that each EPROM bit is pro- grammed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM mem- ory is verified at VCC = VPP = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27C256 in parallel with dif- ferent data is also easily accomplished. Except for CE, all like inputs of the parallel Am27C256 may be com- mon. A TTL low-level program pulse applied to an Am27C256 CE input with V PP = 12.75 V – 0.25 V, and OE High will program that Am27C256. A high-level CE input inhibits the other Am27C256 devices from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at V IL, CE at VIH, and VPP between 12.5 V to 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C – 5°C ambient temperature range that is required when programming the Am27C256. To activate this mode, the programming equipment must force 12.0 V – 0.5 V on address like A9 of the Am27C256. Two identifier bytes may then be se- quenced from the device outputs by toggling address line A0 from V IL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For the Am27C256, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. As- suming that addresses are stable, address access time ACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC–tOE. Standby Mode The Am27C256 has a CMOS standby mode which re- duces the maximum V CC current to 100 mA. It is placed in CMOS-standby when CE is at VCC – 0.3 V. The Am27C256 also has a TTL-standby mode which re- duces the maximum VCC current to 1.0 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.

To accommodate multiple memory connections, a two- line control function is provided to allow for: ■ Low memory power dissipation ■ Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1-mF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between V CC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, a 4.7-mF bulk electrolytic capacitor should be used between V CC and VSS for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE CE OE A0 A9 V PP Outputs Read V IL VIL XX XD OUT Output Disable X V IH X X X High-Z Standby (TTL) V IH X X X X High-Z Standby (CMOS) V CC + 0.3 V X X X X High-Z Program V IL VIH XX V PP D IN Program Verify V IH VIL XX V PP D OUT Program Inhibit V IH VIH XX V PP High-Z Manufacturer Code V IL VIL VIL VH X 01H Device Code V IL VIL VIH VH X 10H Auto Select (Note 3) Mode Pins Notes: 1. VH = 12.0 V + 0.5 V 2. X = Either VIH or VIL 3. A1–A8 = A10–A14 = VIL 4. See DC Programming Characteristics for VPP voltage during programming.

Voltage with Respect To VSS All pins except A9,VPP,VCC Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During transitions, the inputs may overshoot VSS to –2.0 V for peri- ods of up to 20 ns. Maximum DC voltage on input andI/O pins is VCC + 0.5 V which may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. For A9 and VPP the minimum DC input is –0.5 V. During transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. A9 and VPP must not exceed 13.5 V for any period of time. Stresses above those listed under “Absolute Maximum Rat- ings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Industrial (I) Devices Extended Commercial (E) Devices Ambient Temperature (TA) –55 °C to +125°C. . . . Supply Read Voltages Operating ranges define those limits between which the func- tionality of the device is guaranteed.

Symbol Description Conditions Typ Max Typ Max Typ Max Typ Max Unit C IN Input Capacitance V IN = 0 8 12 8 12 6 10 10 12 pF C OUT Output Capacitance VOUT = 0 8 12 8 12 8 10 12 14 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25°C, f = 1 MHz. CDV028 PL 032 PD 028 TS 032 SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) Parameter Test JEDEC Standard Description Conditions -55 -70 -90 -120 -150 -200 -255 Unit tAVQV tACC Address to CE = OE = Min – – – – – – – Output Delay V IL Max 55 70 90 120 150 200 250 ns tELQV tCE Chip Enable to OE = VIL Min – – – – – – – Output Delay Max 55 70 90 120 150 200 250 ns tGLQV tOE Output Enable to CE = VIL Min – – – – – – – Output Delay Max 35 40 40 50 50 50 50 ns tGHQZ (Note 2) Max 25 25 25 30 30 30 30 ns tAXQX tOH Min 0 0 0 0 0 0 0 Parameter Symbols Am27C256 Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is only sampled and not 100% tested. 3. Caution: The Am27C256 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied. 4. For the -55 and -70: Output Load: 1 TTL gate and CL = 30 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0 V to 3 V Timing Measurement Reference Level: 1.5 V for inputs and outputs For all other versions: Output Load: 1 TTL gate and CL = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float Output Hold from Addresses, CE, or OE, whichever occurred first

+5.0 V C L = 100 pF including jig capacitance (30 pF for -55, -70) 6.2 kW 2.7 kW Diodes = IN3064 or Equivalent 08007H-8 SWITCHING TEST WAVEFORM 2.4 V 0.45 V 2.0 V 0.8 V 2.0 V

0.8 VTest Points

1.5 V 1.5 V Input Output Test Points AC Testing: Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are £ 20 ns. 08007H-9 AC Testing: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are £ 20 ns for -55 and -70.

KEY TO SWITCHING TEST WAVEFORMS Must Be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is High Impedence “Off” State WAVEFORM INPUTS OUTPUTS KS000010 SWITCHING WAVEFORMS Addresses CE OE Output 08007H-10 Addresses Valid High Z High Z tCE Valid Output 2.4 0.45 2.0 0.8 2.0 0.8 tACC (Note 1) tOE tDF (Note 2) tOH Notes: 1. OE may be delayed up to tACC–tOE after the falling edge of the addresses without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first.