AMD-X5-133ADW

AM5X86 AMD | Alldatasheet

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Technical content

ed with an industry standard two-pin interface. Table 1. Clocking Options

133 MHz 33 MHz 168-pin PGA

133 MHz 33 MHz 208-pin SQFP

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AAMD-X5 Package Type Family/Core Valid Combinations Valid Combinations list configura- tions planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. A =168-pin PGA S = 208-pin SQFP AMD-X5 Case Temperature D W= 55° C Z = 85° C – 133 Clock Speed 133 = 133 MHz W Operating Voltage D= 3 . 4 5 V F= 3 . 3 V Valid Combinations (Max) AMD-X5-133ADW PGA 3.45 V 55° C AMD-X5-133ADZ PGA 3.45 V 85° C AMD-X5-133SFZ SQFP 3.3 V 85° C AMD-X5-133SDZ SQFP 3.45 V 85° C

4.8.6 Reordering of Write-Backs (AHOLD) with BOFF

4.8.7.2 BOFF

4.10.3 PLOCK

7.3.2 SMI

7.8.3 A20M

10 Am5

Figure 13 Cycle Reordering with BOFF Figure 17 Burst Read with BOFF Figure 22 Basic SMI

1 CONNECTION DIAGRAMS AND PIN DESIGNATIONS

1.1 168-pin PGA (Pin Grid Array) Package ABCDEFGHJKLMNPQRS ABCDEFGHJKLMNPQRS D20 D19 D11 D9 V SS DP1 V SS VSS INC V SS VSS VSS D2 D0 A31 A28 A27 D22 D21 D18 D13 V CC D8 V CC D3 D5 V CC D6 V CC D1 A29 V SS A25 A26 TCK V SS CLK D17 D10 D15 D12 DP2 D16 D14 D7 D4 DP0 A30 A17 V CC A23 D23 V SS VCC A19 V SS VOLDET DP3 V SS VCC D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A21 A18 A14 D24 D25 D27 D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A24 V CC VSS VSS VCC D26 D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A22 A15 A12 D29 D31 D28 D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A20 V CC VSS VSS VCC D30 D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A16 V CC VSS TDI TMS FERR A2 V CC VSS INV SMI SRESET VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A13 V CC VSS VSS VCC UP D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 A9 V CC VSS HITM CACHE SMIACT A5 A11 V SS INC WB/WT INC A7 A8 A10 IGNNE NMI FLUSH A20M HOLD KEN STPCLK BRDY BE2 BE0 PWT D/C LOCK HLDA BREQ A3 A6 INTR TDO RESET BS8 V CC RDY V CC VCC BE1 V CC VCC VCC M/IO V CC PLOCK BLAST A4 AHOLD EADS BS16 BOFF V SS BE3 V SS VSS PCD V SS VSS VSS W/R V SS PCHK CLKMUL ADS PIN SIDE VIEW

1.2 168-pin PGA Designations (Functional Grouping) Address Data Control Test INC Vcc Vss Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin No. Pin No. Pin No. A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Q-14 R-15 S-16 Q-12 S-15 Q-13 R-13 Q-11 S-13 R-12 S-7 Q-10 S-5 R-7 Q-9 Q-3 R-5 Q-4 Q-8 Q-5 Q-7 S-3 Q-6 R-2 S-2 S-1 R-1 P-2 P-3 Q-1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 P-1 N-2 N-1 H-2 M-3 J-2 L-2 L-3 F-2 D-1 E-3 C-1 G-3 D-2 K-3 F-3 J-3 D-3 C-2 B-1 A-1 B-2 A-2 A-4 A-6 B-6 C-7 C-6 C-8 A-8 C-9 B-8 A20M ADS AHOLD BE0 BE1 BE2 BE3 BLAST BOFF BRDY BREQ BS8 BS16 CACHE CLK CLKMUL D/C DP0 DP1 DP2 DP3 EADS FERR FLUSH HITM HLDA HOLD IGNNE INTR INV KEN LOCK M/IO NMI PCD PCHK PLOCK PWT RDY RESET SMI SMIACT SRESET STPCLK UP VOLDET WB/WT W/R D-15 S-17 A-17 K-15 J-16 J-15 F-17 R-16 D-17 H-15 Q-15 D-16 C-17 B-12 C-3 R-17 M-15 N-3 F-1 H-3 A-5 B-17 C-14 C-15 A-12 P-15 E-15 A-15 A-16 A-10 F-15 N-15 N-16 B-15 J-17 Q-17 Q-16 L-15 F-16 C-16 B-10 C-12 C-10 G-15 C-11 S-4 B-13 N-17 TCK TDI TDO TMS A-3 A-14 B-16 B-14 A-13 C-13 J-1 B-7 B-9 B-11 C-4 C-5 E-2 E-16 G-2 G-16 H-16 K-2 K-16 L-16 M-2 M-16 P-16 R-3 R-6 R-8 R-9 R-10 R-11 R-14 A-7 A-9 A-11 B-3 B-4 B-5 E-1 E-17 G-1 G-17 H-1 H-17 K-1 K-17 L-1 L-17 M-1 M-17 P-17 Q-2 R-4 S-6 S-8 S-9 S-10 S-11 S-12 S-14 Notes: 1. VOLDET is connected internally to VSS . 2. INC = Internal No Connect

10 Am5 X86 Microprocessor

1.3 208-pin SQFP (Shrink Quad Flat Pack) Package TOP VIEW

1.4 208-pin SQFP Designations (Functional Grouping) Address Data Control Test INC Vcc Vss Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin No. Pin No. Pin No. A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 161 160 159 158 154 153 152 151 149 148 147 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 A20M ADS AHOLD BE0 BE1 BE2 BE3 BLAST BOFF BRDY BREQ BS8 BS16 CACHE CLK CLKMUL D/C DP0 DP1 DP2 DP3 EADS FERR FLUSH HITM HLDA HOLD IGNNE INTR INV KEN LOCK M/IO NMI PCD PCHK PLOCK PWT RDY RESET SMI SRESET STPCLK SMIACT UP WB/WT W/R 203 204 145 125 109 207 206 194 TCK TDI TDO TMS 168 167 127 102 106 111 114 121 128 131 133 134 136 137 139 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 104 105 107 110 115 120 122 132 135 138 146 156 157 170 175 181 184 189 199 201 208 Note: INC = Internal No Connect

12 Am5 X86 Microprocessor

2 LOGIC SYMBOL

DP3–DP0 A31–A4 CLK A20M M/IO Am5 X86 CPU W/R D/C LOCK

4 BE3 –BE0

A3–A2 BRDY BLAST PWT PCD KEN FLUSH EADS AHOLD Data Parity Data Bus Burst Control Page Cacheability Invalidation Cache Control/ D31–D0 TMS TDI TDO TCK IEEE Test Port Access FERRIGNNE Numeric Error Reporting Bus Arbitration BREQ HOLD HLDA BOFF CACHE CLKMULClock Multiplier Mask HITM INV SMI SMIACT SMM SRESET STPCLKStop Clock UPUpgrade VOLDETVoltage Detect Present WB/WT

3 PIN DESCRIPTIONS

The Am5X86 microprocessor provides the complete in- terface support offered by the Enhanced Am486 micro- processor family products. The CLKMUL pin settings have changed to accommodate the higher operating speed selection. A20M Address Bit 20 Mask (Active Low; Input) A Low signal on the A20M pin causes the microproces- sor to mask address line A20 before performing a lookup to the internal cache, or driving a memory cycle on the bus. Asserting A20M causes the processor to wrap the address at 1 Mbyte, emulating Real mode operation. The signal is asynchronous, but must meet setup and hold times t 20 and t21 for recognition during a specific clock. During normal operation, A20M should be sam- pled High at the falling edge of RESET. A31–A4/A3–A2 Address Lines (Inputs/Outputs)/(Outputs) Pins A31–A2 define a physical area in memory or indi- cate an input/output (I/O) device. Address lines A31–A4 drive addresses into the microprocessor to perform cache line invalidations. Input signals must meet setup and hold times t 22 and t23. A31–A2 are not driven during bus or address hold. ADS Address Status (Active Low; Output) A Low output from this pin indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS is driven active by the same clock as the addresses. ADS is active Low and is not driven during bus hold. AHOLD Address Hold (Active High; Input) The external system may assert AHOLD to perform a cache snoop. In response to the assertion of AHOLD, the microprocessor stops driving the address bus A31– A2 in the next clock. The data bus remains active and data can be transferred for previously issued read or write bus cycles during address hold. AHOLD is recog- nized even during RESET and LOCK . The earliest that AHOLD can be deasserted is two clock cycles after EADS is asserted to start a cache snoop. If HITM is activated due to a cache snoop, the microprocessor completes the current bus activity and then asserts ADS and drives the address bus while AHOLD is active. This starts the write-back of the modified line that was the target of the snoop. BE3 –BE0 Byte Enable (Active Low; Outputs) The byte enable pins indicate which bytes are enabled and active during read or write cycles. During the first cache fill cycle, however, an external system should ignore these signals and assume that all bytes are active. ■ BE3 for D31–D24 ■ BE2 for D23–D16 ■ BE1 for D15–D8 ■ BE0 for D7–D0 BE3 –BE0 are active Low and are not driven during bus hold. BLAST Burst Last (Active Low; Output) Burst Last goes Low to tell the CPU that the next BRDY signal completes the burst bus cycle. BLAST is active for both burst and non-burst cycles. BLAST is active Low and is not driven during a bus hold. BOFF Back Off (Active Low; Input) This input signal forces the microprocessor to float all pins normally floated during hold, but HLDA is not as- serted in response to BOFF . BOFF has higher priority than RDY or BRDY; if both are returned in the same clock, BOFF takes effect. The microprocessor remains in bus hold until BOFF goes High. If a bus cycle is in progress when BOFF is asserted, the cycle restarts. BOFF must meet setup and hold times t18 and t19 for proper operation. BOFF has an internal weak pull-up. BRDY Burst Ready Input (Active Low; Input) The BRDY signal performs the same function during a burst cycle that RDY performs during a non-burst cycle. BRDY indicates that the external system has presented valid data in response to a read, or that the external system has accepted data in response to a write. BRDY is ignored when the bus is idle and at the end of the first clock in a bus cycle. BRDY is sampled in the second and subsequent clocks of a burst cycle. The data pre- sented on the data bus is strobed into the microproces- sor when BRDY is sampled active. If RDY is returned simultaneously with BRDY, BRDY is ignored and the cycle is converted to a non-burst cycle. BRDY is active Low and has a small pull-up resistor, and must satisfy the setup and hold times t 16 and t17. BREQ Internal Cycle Pending (Active High; Output) BREQ indicates that the microprocessor has generated a bus request internally, whether or not the micropro- cessor is driving the bus. BREQ is active High and is floated only during Tri-state Test mode (see FLUSH

14 Am5 X86 Microprocessor

ing copy-back or write-back cycles. in response to a BOFF or HOLD request. at RESET to determine the design operating frequency. SS to ensure correct operation. and subsequent clocks of write cycles. same timing as the data driven by the microprocessor. Table 2. EADS Sample Time

Floating-Point Error (Active Low; Output) Driven active when a floating-point error occurs, FERR is similar to the ERROR pin on a 387 math coprocessor. FERR is included for compatibility with systems using DOS-type floating-point error reporting. FERR is active Low, and is not floated during bus hold, except during Tri-state Test mode (see FLUSH FLUSH Cache Flush (Active Low; Input) In Write-back mode, FLUSH forces the microprocessor to write-back all modified cache lines and invalidate its internal cache. The microprocessor generates two flush acknowledge special bus cycles to indicate completion of the write-back and invalidation. In Write-through mode, FLUSH invalidates the cache without issuing a special bus cycle. FLUSH is an active Low input that needs to be asserted only for one clock. FLUSH is asyn- chronous, but setup and hold times t20 and t21 must be met for recognition in any specific clock. Sampling FLUSH Low in the clock before the falling edge of RESET causes the microprocessor to enter Tri-state Test mode. HITM Hit Modified Line (Active Low; Output) In Write-back mode (WB/WT=1 at RESET), HITM indi- cates that an external snoop cache tag comparison hit a modified line. When a snoop hits a modified line in the internal cache, the microprocessor asserts HITM two clocks after EADS is asserted. The HITM signal stays asserted (Low) until the last BRDY for the corresponding write-back cycle. At all other times, HITM is deasserted (High). During RESET, the HITM signal can be used to detect whether the CPU is operating in Write-back mode. In Write-back mode (WB/WT =1 at RESET), HITM is deasserted (driven High) until the first snoop that hits a modified line. In Write-through mode, HITM floats at all times. HLDA Hold Acknowledge (Active High; Output) The HLDA signal is activated in response to a hold re- quest presented on the HOLD pin. HLDA indicates that the microprocessor has given the bus to another local bus master. HLDA is driven active in the same clock in which the microprocessor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active High and remains driven during bus hold. HLDA is floated only during Tri-state Test mode (see FLUSH HOLD Bus Hold Request (Active High; Input) HOLD gives control of the microprocessor bus to anoth- er bus master. In response to HOLD going active, the microprocessor floats most of its output and input/output pins. HLDA is asserted after completing the current bus cycle, burst cycle, or sequence of locked cycles. The microprocessor remains in this state until HOLD is deas- serted. HOLD is active High and does not have an in- ternal pull-down resistor. HOLD must satisfy setup and hold times t 18 and t19 for proper operation. IGNNE Ignore Numeric Error (Active Low; Input) When this pin is asserted, the Am5X86 microprocessor will ignore a numeric error and continue executing non-control floating-point instructions. When IGNNE is deasserted, the Am5X86 microprocessor will freeze on a non-control floating-point instruction if a previous float- ing-point instruction caused an error. IGNNE has no effect when the NE bit in Control Register 0 is set. IGNNE is active Low and is provided with a small internal pullup resistor. IGNNE is asynchronous but must meet setup and hold times t20 and t21 to ensure recognition in any specific clock. INTR Maskable Interrupt (Active High; Input) When asserted, this signal indicates that an external interrupt has been generated. If the internal interrupt flag is set in EFLAGS, active interrupt processing is ini- tiated. The microprocessor generates two locked inter- rupt acknowledge bus cycles in response to the INTR pin going active. INTR must remain active until the in- terrupt acknowledges have been performed to ensure that the interrupt is recognized. INTR is active High and is not provided with an internal pull-down resistor. INTR is asynchronous, but must meet setup and hold times t 20 and t21 for recognition in any specific clock. INV Invalidate (Active High; Input) The external system asserts INV to invalidate the cache- line state when an external bus master proposes a write. It is sampled together with A31–A4 during the clock in which EADS is active. INV has an internal weak pull-up. INV is ignored in Write-through mode. KEN Cache Enable (Active Low; Input) KEN determines whether the current cycle is cacheable. When the microprocessor generates a cacheable cycle and KEN is active one clock before RDY or BRDY during the first transfer of the cycle, the cycle becomes a cache line fill cycle. Returning KEN active one clock before RDY during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN is active Low and is provided with a small internal pull-up resistor. KEN must satisfy setup and hold times t14 and t15 for proper operation.

16 Am5 X86 Microprocessor

Bus Lock (Active Low; Output) A Low output on this pin indicates that the current bus cycle is locked. The microprocessor ignores HOLD when LOCK is asserted (although it does acknowledge AHOLD and BOFF ). LOCK goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when RDY is returned. LOCK is active Low and is not driven during bus hold. Locked read cycles are not transformed into cache fill cycles if KEN is active. M/IO Memory/Input-Output (Active High/Active Low; Output) A High output indicates a memory cycle. A Low output indicates an I/O cycle. NMI Non-Maskable Interrupt (Active High; Input) A High NMI input signal indicates that an external non- maskable interrupt has occurred. NMI is rising-edge sensitive. NMI must be held Low for at least four CLK periods before this rising edge. The NMI input does not have an internal pull-down resistor. The NMI input is asynchronous, but must meet setup and hold times t and t21 for recognition in any specific clock. PCD Page Cache Disable (Active High; Output) This pin reflects the state of the PCD bit in the page table entry or page directory entry (programmable through the PCD bit in CR3). If paging is disabled, the CPU ignores the PCD bit and drives the PCD output Low. PCD has the same timing as the cycle definition pins (M/IO , D/C, and W/R). PCD is active High and is not driven during bus hold. PCD is masked by the Cache Disable bit (CD) in Control Register 0 (CR0). PCHK Parity Status (Active Low; Output) Parity status is driven on the PCHK pin the clock after RDY for read operations. The parity status reflects data sampled at the end of the previous clock. A Low PCHK indicates a parity error. Parity status is checked only for enabled bytes as is indicated by the byte enable and bus size signals. PCHK is valid only in the clock imme- diately after read data is returned to the microprocessor; at all other times PCHK is inactive High. PCHK is floated only during Tri-state Test mode (see FLUSH). PLOCK Pseudo-Lock (Active Low; Output) In Write-back mode, the processor forces the output High and the signal is always read as inactive. In Write- through mode, PLOCK operates normally. When asserted, PLOCK indicates that the current bus transaction requires more than one bus cycle. Examples of such operations are segment table descriptor reads (8 bytes) and cache line fills (16 bytes). The micropro- cessor drives PLOCK active until the addresses for the last bus cycle of the transaction have been driven, whether or not RDY or BRDY is returned. PLOCK is a function of the BS8, BS16, and KEN inputs. PLOCK should be sampled on the clock when RDY is returned. PLOCK is active Low and is not driven during bus hold. PWT Page Write-Through (Active High; Output) This pin reflects the state of the PWT bit in the page table entry or page directory entry (programmable through the PWT bit in CR3). If paging is disabled, the CPU ignores the PWT bit and drives the PWT output Low. PWT has the same timing as the cycle definition pins (M/IO , D/C, and W/R). PWT is active High and is not driven during bus hold. RESET Reset (Active High; Input) RESET forces the microprocessor to initialize. The mi- croprocessor cannot begin execution of instructions un- til at least 1 ms after V CC and CLK have reached their proper DC and AC specifications. To ensure proper mi- croprocessor operation, the RESET pin should remain active during this time. RESET is active High. RESET is asynchronous but must meet setup and hold times t 20 and t21 to ensure recognition on any specific clock. RDY Non-Burst Ready (Active Low; Input) A Low input on this pin indicates that the current bus cycle is complete, that is, either the external system has presented valid data on the data pins in response to a read, or the external system has accepted data from the microprocessor in response to a write. RDY is ignored when the bus is idle and at the end of the bus cycle’s first clock. RDY is active during address hold. Data can be returned to the processor while AHOLD is active. RDY is active Low and does not have an internal pull- up resistor. RDY must satisfy setup and hold times t16 and t17 for proper chip operation. SMI SMM Interrupt (Active Low; Input) A Low signal on the SMI pin signals the processor to enter System Management mode (SMM). SMI is the highest level processor interrupt. The SMI signal is rec- ognized on an instruction boundary, similar to the NMI and INTR signals. SMI is sampled on every rising clock edge. SMI is a falling-edge sensitive input. The SMI input has an internal pull-up resister. Recognition of SMI is guaranteed in a specific clock if it is asserted synchro- nously and meets the setup and hold times. If SMI is asserted asynchronously, it must go High for a minimum of two clocks before going Low, and it must remain Low

for at least two clocks to guarantee recognition. When the CPU recognizes SMI, it enters SMM before execut- ing the next instruction and saves internal registers in SMM space. SMIACT SMM Interrupt Active (Active Low; Output) SMIACT goes Low in response to SMI. It indicates that the processor is operating under SMM control. SMIACT remains Low until the processor receives a RESET sig- nal or executes the Resume Instruction (RSM) to leave SMM. This signal is always driven. It does not float dur- ing bus HOLD or BOFF Note: Do not use SRESET to exit from SMM. The sys- tem should block SRESET during SMM. SRESET Soft Reset (Active High; Input) The CPU samples SRESET on every rising clock edge. If SRESET is sampled active, the SRESET sequence begins on the next instruction boundary. SRESET resets the processor, but, unlike RESET, does not cause it to sample UP or WB/WT, or affect the FPU, cache, CD and NW bits in CR0, and SMBASE. SRESET is asyn- chronous and must meet the same timing as RESET. The SRESET input has an internal pull-down resistor. STPCLK Stop Clock (Active Low; Input) A Low input signal indicates a request has been made to turn off the CLK input. When the CPU recognizes a STPCLK , the processor: ■ Stops execution on the next instruction boundary (unless superseded by a higher priority interrupt) ■ Empties all internal pipelines and write buffers ■ Generates a Stop Grant acknowledge bus cycle STPCLK is active Low and has an internal pull-up re- sistor. STPCLK is asynchronous, but it must meet setup and hold times t20 and t21 to ensure recognition in any specific clock. STPCLK must remain active until the Stop Clock special bus cycle is issued and the system returns either RDY or BRDY. TCK Test Clock (Input) Test Clock provides the clocking function for the JTAG boundary scan feature. TCK clocks state information and data into the component on the rising edge of TCK on TMS and TDI, respectively. Data is clocked out of the component on the falling edge of TCK on TDO. TDI Test Data Input (Input) TDI is the serial input that shifts JTAG instructions and data into the tested component. TDI is sampled on the rising edge of TCK during the SHIFT-IR and the SHIFT-DR TAP (Test Access Port) controller states. During all other TAP controller states, TDI is ignored. TDI uses an internal weak pull-up. TDO Test Data Output (Active High; Output) TDO is the serial output that shifts JTAG instructions and data out of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR TAP controller states. Otherwise, TDO is tri-stated. TMS Test Mode Select (Active High; Input) TMS is decoded by the JTAG TAP to select the operation of the test logic. TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior of the TAP controller, the TMS pin has an internal pull-up resistor. UP Write/Read (Input) The processor samples the Upgrade Present (UP) pin in the clock before the falling edge of RESET. If it is Low, the processor tri-states its outputs immediately. UP must remain asserted to keep the processor inactive. The pin uses an internal pull-up resistor. VOLDET—(168-pin PGA package only) Voltage Detect (Output) VOLDET provides an external signal to allow the system to determine the CPU input power level (3 V or 5 V). For Am5 X86 processors, the pin ties internally to VSS . WB/WT Write-Back/Write-Through (Input) If the processor samples WB/WT High at RESET, the processor is configured in Write-back mode and all sub- sequent cache line fills sample WB/WT on the same clock edge in which it finds either RDY or the first BRDY of a burst transfer to determine if the cache line is des- ignated as Write-back mode or Write-through. If the sig- nal is Low on the first BRDY or RDY, the cache line is write-through. If the signal is High, the cache line is write- back. If WB/WT is sampled Low at RESET, all cache line fills are write-through. WB/WT has an internal weak pull-down. W/R Write/Read (Output) A High output indicates a write cycle. A Low output in- dicates a read cycle. Note: The Am5 X86 microprocessor does not use the VCC5 pin used by some 3-V, clock-tripled, 486-based processors. The corresponding pin on the Am5X86 mi- croprocessor is an Internal No Connect (INC).

18 Am5 X86 Microprocessor

4.3.3 Protected Mode

Protected mode provides access to the sophisticated memory management paging and privilege capabilities of the processor.

4.3.4 System Management Mode

SMM is a special operating mode described in detail in Section 7.

4.4 Cache Architecture

The Am5X86 microprocessor family supports a superset architecture of the standard 486 cache implementation. This architectural enhancement improves not only CPU performance, but total system performance.

4.4.1 Write-Through Cache

The standard 486DX-type write-through cache architec- ture is characterized by the following: ■ External read accesses are placed in the cache if they meet proper caching requirements. ■ Subsequent reads to the data in the cache are made if the address is stored in the cache tag array. ■ Write operations to a valid address in the cache are updated in the cache and to external memory. This data writing technique is called write-through. The write-through cache implementation forces all writes to flow through to the external bus and back to main memory. Consequently, the write-through cache generates a large amount of bus traffic on the external data bus.

4.4.2 Write-Back Cache

The microprocessor write-back cache architecture is characterized by the following: ■ External read accesses are placed in the cache if they meet proper caching requirements. ■ Subsequent reads to the data in the cache are made if the address is stored in the cache tag array. ■ Write operations to a valid address in the cache that is in the write-through (shared) state is updated in the cache and to external memory. ■ Write operations to a valid address in the cache that is in the write-back (exclusive or modified) state is updated only in the cache. External memory is not updated at the time of the cache update. ■ Modified data is written back to external memory when the modified cache line is being replaced with a new cache line (copy-back operation) or an exter- nal bus master has snooped a modified cache line (write-back). The write-back cache feature significantly reduces the amount of bus traffic on the external bus; however, it also adds complexity to the system design to maintain memory coherency. The write-back cache requires en-

4 FUNCTIONAL DESCRIPTION

4.1 Overview

Am5 X86 microprocessors use a 32-bit architecture with on-chip memory management and cache memory units. The instruction set includes the complete 486 micropro- cessor instruction set along with extensions to serve the new extended applications. All software written for the 486 microprocessor and previous members of the x86 architectural family can run on the Am5 X86 micropro- cessor without modification. The on-chip Memory Management Unit (MMU) is com- pletely compatible with the 486 MMU. The MMU in- cludes a segmentation unit and a paging unit. Segmentation allows management of the logical ad- dress space by providing easy data and code relocati- bility and efficient sharing of global resources. The paging mechanism operates beneath segmentation and is transparent to the segmentation process. Paging is optional and can be disabled by system software. Each segment can be divided into one or more 4-Kbyte seg- ments. To implement a virtual memory system, the Am5 X86 microprocessor supports full restartability for all page and segment faults.

4.2 Memory

Memory is organized into one or more variable length segments, each up to 4 Gbytes (2 32 bytes). A segment can have attributes associated with it, including its lo- cation, size, type (i.e., stack, code, or data), and protec- tion characteristics. Each task on a microprocessor can have a maximum of 16,381 segments, each up to 4 Gbytes. Thus, each task has a maximum of 64 Tbytes of virtual memory. The segmentation unit provides four levels of protection for isolating and protecting applications and the operat- ing system from each other. The hardware-enforced protection allows high-integrity system designs.

4.3 Modes of Operation

The Am5 X86 microprocessor has four modes of opera- tion: Real Address mode (Real mode), Virtual 8086 Ad- dress mode (Virtual mode), Protected Address mode (Protected mode), and System Management mode (SMM).

4.3.1 Real Mode

In Real mode, the Am5 X86 microprocessor operates as a fast 8086. Real mode is required primarily to set up the processor for Protected mode operation.

4.3.2 Virtual Mode

In Virtual mode, the processor appears to be in Real mode, but can use the extended memory accessing of Protected mode.

4.5 Write-Back Cache Protocol

system without a cache can run without modification. system to identify non-cacheable data regions. due to a read miss. Write allocation is not implemented. snoop when a modified line is hit. cess and reads the modified data from memory.

4.5.1 Cache Line Overview

line. Table 3 shows the cache line organization. Table 3. Cache Line Organization

4.5.2 Line Status and Line State

cessor or during snooping from an external bus master.

4.5.2.1 Invalid

ticipate in the cache coherency protocol.

4.5.2.2 Exclusive

the external memory location.

4.5.2.3 Shared

exactly; or the cache line is in Write-through mode.

4.5.2.4 Modified

Table 4. Legal Cache Line States

20 Am5 X86 Microprocessor

4.6 Cache Replacement Description

cache line in the four-way set with the new cache line.

4.7 Memory Configuration

cessor can respond appropriately.

4.7.1 Cacheability

signal, at the time of a burst read access from memory. the four 32-bit doublewords are still placed in the cache.

4.7.2 Write-Through/Write-Back

croprocessor does this on an access-by-access basis. even if the cache line is write protected.

4.8 Cache Functionality in Write-Back

cache functions and snooping actions.

4.8.1 Processor-Initiated Cache Functions and

back buffer for cache line replacement of modified lines. to main memory. Each buffer is four doublewords in size. Table 5. MESI Cache Line Status Figure 1. Processor-Induced Line Transitions in

4.8.2 Snooping Actions and State Transitions

have to be invalidated, which is indicated by INV set to 0.

4.8.2.1 Difference between Snooping

Figure 2. Snooping State Transitions

22 Am5 X86 Microprocessor

4.8.2.2 HOLD Bus Arbitration Implementation

4.8.2.2.1 Processor-Induced Bus Cycles

explains the key to switching waveforms. Figure 3. Typical System Block Diagram

4.8.2.2.2 External Read

by asserting ADS = 0 and W/R = 0. Step 2 WB/WT is sampled in the same cycle as BRDY.

4.8.2.2.3 External Write

by asserting ADS = 0 and W/R = 1.

4.8.2.2.4 HOLD/HLDA External Access TIming

Table 6. Key to Switching Waveforms

24 Am5 X86 Microprocessor

Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line The circled numbers in this figure represent the steps in section 4.8.3.1. The circled numbers in this figure represent the steps in section 4.8.3.2. Figure 7. Snoop of On-Chip Cache That Hits a Non-modified Line

4.8.3 External Bus Master Snooping Actions

4.8.3.1 Snoop Miss

not in the snooping cache, HITM is 1.

4.8.3.2 Snoop Hit to a Non-Modified Line

and the line is not modified (see Figure 7). becomes valid. In this case, HITM is 1.

4.8.4 Write-Back Case

can be performed (see Figure 8). clock cycle before the HLDA response. Figure 8. Snoop That Hits a Modified Line (Write-Back) The circled numbers in this figure represent the steps in section 4.8.4.

26 Am5 X86 Microprocessor

that the microprocessor can access the bus. is asserted for burst cycles. and W/R = 1. The write access is a burst write. cess, the processor drives HITM back to 1. Step 8 HOLD is sampled by the microprocessor. acknowledging the HOLD request. generates EADS Low in the same clock cycle. Step 11 The bus master restarts the aborted access. sor as before. This starts another snoop cycle. (INV = 0) or is changed to invalid (INV = 1).

4.8.5 Write-Back and Pending Access

Figure 9. Write-Back and Pending Access The circled numbers in this figure represent the steps in section 4.8.5.

clock cycle before the HLDA response. the HOLD signal in response to the HITM = 0. and W/R = 1. The write access is a burst write. for the write-back cycles can vary. cess, the processor drives HITM back to 1. Step 8 HOLD is sampled by the microprocessor. acknowledging the HOLD request. generates EADS Low in the same clock cycle. Step 11 The bus master restarts the aborted access. sor as before. This starts another snoop cycle. (INV = 0) or is changed to invalid (INV = 1).

4.8.5.1 HOLD/HLDA Write-Back Design

Figure 10. Valid HOLD Assertion During Write-Back

28 Am5 X86 Microprocessor

later than in the final BRDY of the last write. HOLD until the final write cycle of the write-back.

4.8.5.2 AHOLD Bus Arbitration Implementation

the total system (see Figure 11). Figure 11. Closely Coupled Cache Block Diagram for the AHOLD implementation.

4.8.5.3 Normal Write-Back

snooping access with AHOLD can be done in parallel. first, then the write-back is executed (see Figure 12). cessor-initiated access is not finished. is 1, a write access caused the snooping cycle. is modified; therefore, HITM is 0. still active and the address bus is still an input. onto the address bus by the microprocessor.

Figure 12. Snoop Hit Cycle with Write-Back The circled numbers in this figure represent the steps in section 4.8.5.3. and BRDY both transition to 0. either shared (INV = 0) or is changed to invalid (INV = 1).

4.8.6 Reordering of Write-Backs (AHOLD) with

back receives priority and is executed first. cycle after AHOLD is asserted. completed because BLAST = 1. snooping processor to reorder the access. read is not used. It is reread later.

30 Am5 X86 Microprocessor

Step 13 The previous read is now reread.

4.8.7 Special Scenarios for AHOLD Snooping

processor-initiated operations.

4.8.7.1 Write Cycle Reordering due to Buffering

1. For simplicity, snooping signals that behave in their

ed. No other access is in progress. into the write buffers, assuming they are not full. Figure 13. Cycle Reordering with BOFF (Write-Back) The circled numbers in this figure represent the steps in section 4.8.6.

data B and then data A. The order of writes is changed.

1. Set the PWT bit in the page table entries.

hardware solution, is implemented at the system level. The circled numbers in this figure represent the steps in section 4.8.7.1. Figure 14. Write Cycle Reordering Due to Buffering line, but is detected again as early as in step 10.

32 Am5 X86 Microprocessor

4.8.7.2 BOFF Write-Back Arbitration

The use of BOFF to perform snooping of the on-chip cache is used in systems where more than one cache- able bus master resides on the microprocessor bus. The BOFF signal forces the microprocessor to relinquish the bus in the following clock cycle, regardless of the type of bus cycle it was performing at the time. Consequently, the use of BOFF as a bus arbitrator should be imple- mented with care to avoid system problems.

4.8.8 BOFF Design Considerations

The use of BOFF as a bus arbitration control mechanism is immediate. BOFF forces the microprocessor to abort an access in the following clock cycle after it is asserted. The following design issues must be considered.

4.8.8.1 Cache Line Fills

The microprocessor aborts a cache line fill during a burst read if BOFF is asserted during the access. Upon re- gaining the bus, the read access commences where it left off when BOFF was recognized. External buffers should take this cycle continuation into consideration if BOFF is allowed to abort burst read cycles.

4.8.8.2 Cache Line Copy-Backs

Similar to the burst read, the burst write also can be aborted at any time with the BOFF signal. Upon regain- ing access to the bus, the write continues from where it was aborted. External buffers and control logic should take into consideration the necessary control, if any, for burst write continuations.

4.8.8.3 Locked Accesses

Locked bus cycles occur in various forms. Locked ac- cesses occur during read-modify-write operations, in- terrupt acknowledges, and page table updates. Although asserting BOFF during a locked cycle is per- mitted, extreme care should be taken to ensure data coherency for semaphore updates and proper data or- dering.

4.8.9 BOFF

If BOFF is asserted during a write-back, the processor performing the write-back goes off the bus in the next clock cycle. If BOFF is released, the processor restarts that write-back access from the point at which it was aborted. The behavior is identical to the normal BOFF case that includes the abort and restart behavior.

4.8.10 Snooping Characteristics During a Cache

The microprocessor takes responsibility for responding to snoop cycles for a cache line only during the time that the line is actually in the cache or in a copy-back buffer. There are times during the cache line fill cycle and during the cache replacement cycle when the line is “in transit” and snooping responsibility must be taken by other sys- tem components. The following cases apply if snooping is invoked via AHOLD, and neither HOLD nor BOFF is asserted. ■ System designers should consider the possibility that a snooping cycle may arrive at the same time as a cache line fill or replacement for the same ad- dress. If a snooping cycle arrives at the same time as a cache line fill with the same address, the CPU uses the cache line fill, but does not place it in the cache. ■ If a snooping cycle occurs at the same time as a cache line fill with a different address, the cache line fill is placed into the cache unless EADS is recog- nized before the first BRDY but after ADS is assert- ed, or EADS is recognized on the last BRDY of the cache line fill. In these cases, the line is not placed into the cache.

4.8.11 Snooping Characteristics During a

If a copy-back is occurring because of a cache line re- placement, the address being replaced can be matched by a snoop until assertion of the last BRDY of the copy- back. This is when the modified line resides in the copy- back buffer. An EADS as late as two clocks before the last BRDY can cause HITM to be asserted. Figure 15 illustrates the microprocessor relinquishing responsibility of recognizing snoops for a line that is copied back. It shows the latest EADS assertion that can cause HITM assertion. HITM remains active for only one clock period in that example. HITM remains active through the last BRDY of the corresponding write-back; in that case, the write-back has already completed. This is the latest point where snooping can start, because two clock cycles later, the final BRDY of the write-back is applied. If a snoop cycle hits the copy-back address after the first BRDY of the copy-back and ADS has been issued, the microprocessor asserts HITM. Keep in mind that the write-back was initiated due to a read miss and not due to a snoop to a modified line. In the second case, no snooping is recognized if a modified line is detected.

4.9 Cache Invalidation and Flushing in

the write-back cache adds some complexity.

4.9.1 Cache Invalidation through Software

ferent for use in the write-back environment. internal clocks to search the cache for modified data. Writing back modified data adds to this minimum time. WBINVD can only be stopped by a RESET.

4.9.2 Cache Invalidation through Hardware

8 shows the special flush bus cycle configuration. Table 7. WBINVD/INVD Special Bus Cycles

1. WBINVD generates first write-back, then flush.
2. INVD generates only flush.

Figure 15. Latest Snooping of Copy-Back

34 Am5 X86 Microprocessor

4.9.3 Snooping During Cache Flushing

sor completes the copy-back of modified cache lines.

4.10 Burst Write

and BRDY signals is identical to the burst read. CACHE signal indicates burstable cycles. is asserted (for linefills). Table 8. FLUSH Special Bus Cycles Figure 16. Burst Write Figure 17. Burst Read with BOFF Assertion

Figure 18. Burst Write with BOFF Assertion quence), I/O cycles, special cycles, and write-throughs. floats when HLDA is asserted.

1. The access is started by asserting: ADS
2. In the second clock cycle, BLAST is 1 to indicate

that the burst is not finished.

1. The burst write access is finished when BLAST is

and proceeds with the standard non-burst cycle.

4.10.1 Locked Accesses

tion before reading the data from external memory. either modified or unmodified, does not occur.

4.10.2 Serialization

first locked access is executed.

36 Am5 X86 Microprocessor

4.10.3 PLOCK Operation in Write-Through Mode

As described in Section 3, PLOCK is only used in Write- through mode; the signal is driven inactive in Write-back mode. In Write-through mode, the processor drives PLOCK Low to indicate that the current bus transaction requires more than one bus cycle. The CPU continues to drive the signal Low until the transaction is completed, whether or not RDY or BRDY is returned. Refer to the pin description for additional information.

5 CLOCK CONTROL

5.1 Clock Generation

The Am5 X86 CPU is driven by a 1x clock that relies on phased-lock loop (PLL) to generate the two internal clock phases: phase one and phase two. The rising edge of CLK corresponds to the start of phase one (ph1). All external timing parameters are specified relative to the rising edge of CLK.

5.2 Stop Clock

The Am5 X86 CPU also provides an interrupt mecha- nism, STPCLK, that allows system hardware to control the power consumption of the CPU by stopping the in- ternal clock to the CPU core in a sequenced manner. The first low-power state is called the Stop Grant state. If the CLK input is completely stopped, the CPU enters into the Stop Clock state (the lowest power state). When the CPU recognizes a STPCLK interrupt, the processor: ■ Stops execution on the next instruction boundary (unless superseded by a higher priority interrupt) ■ Waits for completion of cache flush ■ Stops the pre-fetch unit ■ Empties all internal pipelines and write buffers ■ Generates a Stop Grant bus cycle ■ Stops the internal clock At this point the CPU is in the Stop Grant state. The CPU cannot respond to a STPCLK request from an HLDA state because it cannot empty the write buffers and, therefore, cannot generate a Stop Grant cycle. The rising edge of STPCLK signals the CPU to return to program execution at the instruction following the inter- rupted instruction. Unlike the normal interrupts (INTR and NMI), STPCLK does not initiate interrupt acknowl- edge cycles or interrupt table reads.

5.2.1 External Interrupts in Order of Priority

In Write-through mode, the priority order of external in- terrupts is: 1. RESET/SRESET 2. FLUSH 3. SMI 4. NMI 5. INTR 6. STPCLK In Write-back mode, the priority order of external inter- rupts is: 1. RESET 2. FLUSH 3. SRESET 4. SMI 5. NMI 6. INTR 7. STPCLK STPCLK is active Low and has an internal pull-up re- sistor. STPCLK is asynchronous, but setup and hold times must be met to ensure recognition in any specific clock. STPCLK must remain active until the Stop Grant special bus cycle is asserted and the system responds with either RDY or BRDY. When the CPU enters the Stop Grant state, the internal pull-up resistor is disabled, reducing the CPU power consumption. The STPCLK input must be driven High (not floated) to exit the Stop Grant state. STPCLK must be deasserted for a minimum of five clocks after RDY or BRDY is returned active for the Stop Grant bus cycle before being asserted again. There are two regions for the Low-power mode supply current: Low Power: Stop Grant state (fast wake-up, frequency- and voltage-dependent) 2. Lowest Power: Stop Clock state (slow wake-up, volt- age-dependent)

5.3 Stop Grant Bus Cycle

The processor drives a special Stop Grant bus cycle to the bus after recognizing the STPCLK interrupt. This bus cycle is the same as the HALT cycle used by a standard Am486 microprocessor, with the exception that the Stop Grant bus cycle drives the value 0000 0010h on the address pins. ■ M/lO = 0 ■ D/C = 0 ■ W/R =1 ■ Address Bus = 0000 0010h (A4 = 1) ■ BE3 –BE0 = 1011 ■ Data bus = undefined The system hardware must acknowledge this cycle by returning RDY or BRDY , or the processor will not enter the Stop Grant state (see Figure 19). The latency be- tween a STPCLK request and the Stop Grant bus cycle depends on the current instruction, the amount of data in the CPU write buffers, and the system memory per- formance.

5.4 Pin State During Stop Grant

they were before the HOLD/HLDA sequence. consumption during Stop Grant or Stop Clock modes. achieve the lowest possible power consumption.

5.5 Clock Control State Diagram

5.5.1 Normal State

changed within the specified CLK period stability limits.

5.5.2 Stop Grant State

while the CPU is in the Stop Grant state. Table 9. Pin State During Stop Grant Bus State Figure 19. Entering Stop Grant State

38 Am5 X86 Microprocessor

Figure 20. Stop Clock State Machine Figure 21. Recognition of Inputs when Exiting Stop Grant State Note: A = Earliest time at which NMI or SMI is recognized. is deasserted (see Figure 21). deasserted, the corresponding interrupt will be serviced.

The Am5 X86 CPU product family requires INTR to be held active until the CPU issues an interrupt acknowl- edge cycle to guarantee recognition. This condition also applies to the existing Am486 CPUs. In the Stop Grant state, the system can stop or change the CLK input. When the clock stops, the CPU enters the Stop Clock state. The CPU returns to the Stop Grant state immediately when the CLK input is restarted. You must hold the STPCLK input Low until a stabilized fre- quency has been maintained for at least 1 ms to ensure that the PLL has had sufficient time to stabilize. The CPU generates a Stop Grant bus cycle when en- tering the state from the Normal or the Auto HALT Power Down state. When the CPU enters the Stop Grant state from the Stop Clock state or the Stop Clock Snoop state, the CPU does not generate a Stop Grant bus cycle.

5.5.3 Stop Clock State

Stop Clock state is entered from the Stop Grant state by stopping the CLK input (either logic High or logic Low). None of the CPU input signals should change state while the CLK input is stopped. Any transition on an input signal (except INTR) before the CPU has re- turned to the Stop Grant state may result in unpredict- able behavior. If INTR goes active while the CLK input is stopped, and stays active until the CPU issues an interrupt acknowledge bus cycle, it is serviced in the normal manner. System design must ensure the CPU is in the correct state prior to asserting cache invalidation or interrupt signals to the CPU.

5.5.4 Auto Halt Power Down State

A HALT instruction causes the CPU to enter the Auto HALT Power Down state. The CPU issues a normal HALT bus cycle, and only transitions to the Normal state when INTR, NMI, SMI , RESET, or SRESET occurs. The system can generate a STPCLK while the CPU is in the Auto HALT Power Down state. The CPU gener- ates a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state. When the system deas- serts the STPCLK interrupt, the CPU returns execution to the HALT state. The CPU generates a new HALT bus cycle when it reenters the HALT state from the Stop Grant state.

5.5.5 Stop Clock Snoop State

(Cache Invalidations) When the CPU is in the Stop Grant state or the Auto HALT Power Down state, the CPU recognizes HOLD, AHOLD, BOFF , and EADS for cache invalidation. When the system asserts HOLD, AHOLD, or BOFF, the CPU floats the bus accordingly. When the system asserts EADS , the CPU transparently enters Stop Clock Snoop state and powers up for one full clock to perform the required cache snoop cycle. If a modified line is snooped, a cache write-back occurs with HITM transi- tioning active until the completion of the write-back. It then powers down and returns to the previous state. The CPU does not generate a bus cycle when it returns to the previous state.

5.5.6 Cache Flush State

When configured in Write-back mode, the processor recognizes FLUSH for copying back modified cache lines to memory in the Auto Halt Power Down State or Normal State. Upon the completion of the cache flush, the processor returns to its prior state, and regenerates a special bus cycle, if necessary.

6 SRESET FUNCTION

The Am5 X86 microprocessor family supports a soft re- set function through the SRESET pin. SRESET forces the processor to begin execution in a known state. The processor state after SRESET is the same as after RE- SET except that the internal caches, CD and NW in CR0, write buffers, SMBASE registers, and floating-point reg- isters retain the values they had prior to SRESET, and cache snooping is allowed. The processor starts exe- cution at physical address FFFFFFF0h. SRESET can be used to help performance for DOS extenders written for the 80286 processor. SRESET provides a method to switch from Protected to Real mode while maintaining the internal caches, CR0, and the FPU state. SRESET may not be used in place of RESET after power-up. In Write-back mode, once SRESET is sampled active, the SRESET sequence begins on the next instruction boundary (unless FLUSH or RESET occur before that boundary). When started, the SRESET sequence con- tinues to completion and then normal processor execu- tion resumes, independent of the deassertion of SRESET. If a snoop hits a modified line during SRESET, a normal write-back cycle occurs. ADS is asserted to drive the bus cycles even if SRESET is not deasserted.

7 SYSTEM MANAGEMENT MODE

7.1 Overview

The Am5X86 microprocessor supports four modes: Re- al, Virtual, Protected, and System Management mode (SMM). As an operating mode, SMM has a distinct pro- cessor environment, interface, and hardware/software features. SMM lets the system designer add new soft- ware-controlled features to the computer products that always operate transparent to the operating system (OS) and software applications. SMM is intended for use only by system firmware, not by applications soft- ware or general purpose systems software. The SMM architectural extension consists of the follow- ing elements: ■ System Management Interrupt (SMI) hardware in- terface

40 Am5 X86 Microprocessor

fully represent the processor state. internal registers to and from SMRAM.

7.3 System Management Interrupt

by executing the following sequence (see Figure 22).

1. The CPU asserts the SMIACT signal, instructing the
2. The CPU saves its state (internal register) to SM-
3. The CPU switches to the SMM processor environ-

ment (an external pseudo-real mode).

1. The CPU then jumps to the absolute address of
2. The SMI handler then executes the RSM instruction

trol to the previously interrupted program execution. Figure 22. Basic SMI Interrupt Service

7.2 Terminology

when servicing a System Management Interrupt. ■ SMI handler: System Management mode handler. interrupted OS or application process. not have access to this memory space. base address that defines the SMRAM space.

7.3.1 System Management Interrupt Processing

executed and the interrupt service routine is complete.

7.3.2 SMI Active (SMIACT)

SMIACT indicates that the CPU is operating in SMM. Figure 23. Basic SMI Hardware Interface Figure 24. SMI Timing for Servicing an I/O Trap

42 Am5 X86 Microprocessor

Figure 25. SMIACT Timing

7.3.3 SMRAM

designer-specific information. as SMI for systems using overlaid SMRAM. choose to decode a larger area of SMRAM as needed. Figure 26. Redirecting System Memory

7.3.4 SMRAM State Save Map

writes its state to the state save area in the SMRAM. CS Base is also referred to as the SMBASE. Table 10. SMRAM State Save Map *Upper 2 bytes are not modified. register images are read-only, and must not be modified. on values stored in a reserved area. area must be saved to non-volatile memory. registers in the CPU, it must also save and restore them.

44 Am5 X86 Microprocessor

7.4 Entering System Management Mode

of the three modes and then return.

7.5 Exiting System Management Mode

1. Auto HALT Restart. It is possible for the SMI

eration is to restart the HALT instruction.

1. I/O Trap Restart. If the SMI
2. SMBASE Relocation . The system can relocate the

aligned on 32-Kbyte boundaries. A RESET also causes execution to exit from SMM.

7.6 Processor Environment

are not acknowledged while the processor is in SMM. Figure 27. Transition to and from SMM

Interrupts from INT and NMI are disabled on SMM entry.

7.7 Executing System Management

30000h, as shown in Table 12.

1. The segment limit check is 4 Gbytes instead of the usual
2. The Selector value for CS remains at 3000h even if the

loaded into the segment base cache. in the 4-Gbyte logical address space. Table 11. SMM Initial CPU Core Register Settings Table 12. Segment Register Initial States

46 Am5 X86 Microprocessor

7.7.1 Exceptions and Interrupts with System

sure that an SMM-compliant debug handler is available. DR7 must then be initialized with the appropriate values. location as the Real mode vector table. latched and serviced after the processor exits SMM. the next instruction of the interrupted code sequence. manner in which they are handled outside of SMM.

7.7.2 SMM Revisions Identifier

and bit definitions are shown in Table 13 and Table 14. at the time it performs a save state. in unpredictable processor behavior. Table 13. SMM Revision Identifier Table 14. SMM Revision Identifier Bit Definitions

7.7.3 Auto HALT Restart

when the RSM instruction is executed.

7.7.4 I/O Trap Restart

terrupted I/O instruction (see Figure 29). ed, then the CPU does not re-execute the I/O instruction. on an I/O instruction boundary.

7.7.5 I/O Trap Word

was a valid I/O instruction. Table 16 shows the layout. was not a valid I/O instruction, the bit is saved as a 0. Table 15. HALT Auto Restart Configuration Figure 28. Auto HALT Restart Register Offset Table 16. I/O Trap Word Configuration Figure 29. I/O Instruction Restart Register Offset

48 Am5 X86 Microprocessor

dictable and should not be used.

7.7.6 SMM Base Relocation

a state save at the new SMBASE. tor based on the current SMBASE (see Figure 31). is addressed according to the above formula. Figure 30. SMM Base Slot Offset vector location, SMI handler modifies the SMBASE slot. es the CPU to enter the shutdown state.

7.8 SMM System Design Considerations

7.8.1 SMRAM Interface

ization code to open the SMRAM space manually. tial SMRAM address space of 38000h–3FFFFh. or during initialization, to access SMRAM. Figure 31. SRAM Usage

34) to force caching during SMM to be write-through. with SMI (as shown in Figure 35). must restrict SMRAM space access to the CPU only.

7.8.2 Cache Flushes

cache functionality to its pre-SMM state.

7.8.3 A20M Pin

pin on Am5X86 CPUs provides this function. pin is recognized while the CPU is in SMM.

1. If the SMI handler needs to access system memory
2. If SMRAM has been relocated to address space

is deasserted on entry to SMM. Figure 32. SMRAM Location

50 Am5 X86 Microprocessor

Figure 33. SMM Timing in Systems Using Non-Overlaid Memory Space Figure 34. SMM Timing in Systems Using Non-Overlaid Memory Spaces force all caching to be write-through during SMM. Figure 35. SMM Timing in Systems Using Non-Overlaid Memory Spaces

52 Am5 X86 Microprocessor

7.8.4 CPU Reset During SMM

The system designer should take into account the fol- lowing restrictions while implementing the CPU Reset logic: 1. When running software written for the 80286 CPU, a CPU RESET switches the CPU from Protected mode to Real mode. RESET and SRESET have a higher priority than SMI . When the CPU is in SMM, the SRESET to the CPU during SMM should be blocked until the CPU exits SMM. SRESET must be blocked beginning from the time when SMI is driven active. Care should be taken not to block the global system RESET, which may be necessary to recover from a system crash. 2. During execution of the RSM instruction to exit SMM, there is a small time window between the deassertion of SMIACT and the completion of the RSM microcode. If a Protected mode to Real mode SRESET is asserted during this window, it is pos- sible that the SMRAM space will be violated. The system designer must guarantee that SRESET is blocked until at least 20 CPU clock cycles after SMI- ACT has been driven inactive or until the start of a bus cycle. 3. Any request for a CPU RESET for the purpose of switching the CPU from Protected mode to Real mode must be acknowledged after the CPU has exited SMM. To maintain software transparency, the system logic must latch any SRESET signals that are blocked during SMM. For these reasons, the SRESET signal should be used for any soft resets, and the RESET signal should be used for all hard resets.

7.8.5 SMM and Second Level Write Buffers

Before the processor enters SMM, it empties its internal write buffers. This is to ensure that the data in the write buffers is written to normal memory space, not SMM space. When the CPU is ready to begin writing an SMM state save to SMRAM, it asserts SMIACT . SMIACT may be driven active by the CPU before the system memory controller has had an opportunity to empty the second level write buffers. To prevent the data from these second level write buffers from being written to the wrong location, the system memory controller needs to direct the memory write cy- cles to either SMM space or normal memory space. This can be accomplished by saving the status of SMIACT with the address for each word in the write buffers.

7.8.6 Nested SMI and I/O Restart

Special care must be taken when executing an SMI han- dler for the purpose of restarting an l/O instruction. When the CPU executes a Resume (RSM) instruction with the l/O restart slot set, the restored EIP is modified to point to the instruction immediately preceding the SMI re- quest, so that the l/O instruction can be re-executed. If a new SMI request is received while the CPU is execut- ing an SMI handler, the CPU services this SMI request before restarting the original I/O instruction. If the I/O restart slot is set when the CPU executes the RSM in- struction for the second SMI handler, the RSM micro- code decrements the restored EIP again. EIP then points to an address different from the originally inter- rupted instruction, and the CPU begins execution at an incorrect entry point. To prevent this from occurring, the SMI handler routine must not set the I/O restart slot during the second of two consecutive SMI handlers.

7.9 SMM Software Considerations

7.9.1 SMM Code Considerations

The default operand size and the default address size are 16 bits; however, operand-size override and ad- dress-size override prefixes can be used as needed to directly access data anywhere within the 4-Gbyte logical address space. With operand-size override prefixes, the SMI handler can use jumps, calls, and returns to transfer a control to any location within the 4-Gbyte space. Note, however, the following restrictions: 1. Any control transfer that does not have an operand- size override prefix truncates EIP to 16 Low-order bits. 2. Due to the Real mode style of base-address formation, a long jump or call cannot transfer control segment with a base address of more than 20 bits (1 Mbyte).

7.9.2 Exception Handling

Upon entry into SMM, external interrupts that require handlers are disabled (the IF in EFLAGS is cleared). This is necessary because, while the processor is in SMM, it is running in a separate memory space. Con- sequently, the vectors stored in the interrupt descriptor table (IDT) for the prior mode are not applicable. Before allowing exception handling (or software interrupts), the SMM program must initialize new interrupt and excep- tion vectors. The interrupt vector table for SMM has the same format as for Real mode. Until the interrupt vector table is correctly initialized, the SMI handler must not generate an exception (or software interrupt). Even though hardware interrupts are disabled, exceptions and software interrupts can still occur. Only a correctly written SMI handler can prevent internal exceptions. When new exception vectors are initialized, internal ex- ceptions can be serviced. Restrictions are as follows: 1. Due to the Real mode style of base address forma- tion, an interrupt or exception cannot transfer con- trol to a segment with a base address of more than 20 bits. 2. An interrupt or exception cannot transfer control to a segment offset of more than 16 bits. 3. If exceptions or interrupts are allowed to occur, only the Low order 16 bits of the return address are

Table 17. Test Register TR4 Bit Descriptions

1. The values of STn and ST3–ST0 are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.
2. During a cache look-up, bit 11 is read only and always 0. The bit is read/write otherwise.

Table 18. Test Register TR5 Bit Descriptions

1. Bit 19 in TR5 is EXT. If EXT = 0, TR4 has the standard 486 processor definition for write-through cache.
2. The values of Set State are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.
3. The SMBASE Relocation feature affects the way

Non-Maskable Interrupt (NMI) processing.

7.9.3 Halt during SMM

take the CPU out of HALT within SMM.

7.9.4 Relocating SMRAM to an Address above

1 Mbyte

can be updated only by changing the segment register. longer be initialized to point to SMRAM.

8 TEST REGISTERS 4 AND 5

provide a detailed description of the field functions.

8.1 TR4 Definition

are not included in these descriptions.

54 Am5 X86 Microprocessor

■ STn (bits 30–29): Read Only, available only in Write- back mode when Ext=1 in TR5. STn returns the sta- tus of the set (ST3, ST2, ST1, or ST0) specified by the TR5 Set State field (bits 18–17) during cache look-ups. Returned values are: —0 0 = i n v a l i d — 01 = exclusive — 10 = modified — 11 = shared ■ ST3 (bits 27–26): Read Only, available only in Write- back mode when Ext=1 in TR5. ST3 returns the sta- tus of Set 3 during cache look-ups. Returned values are: —0 0 = i n v a l i d — 01 = exclusive — 10 = modified — 11 = shared ■ ST2 (bits 25–24): Read Only, available only in Write- back mode when Ext=1 in TR5. ST2 returns the sta- tus of Set 2 during cache look-ups. Returned values are: —0 0 = i n v a l i d — 01 = exclusive — 10 = modified — 11 = shared ■ ST1 (bits 23–22): Read Only, available only in Write- back mode when Ext=1 in TR5. ST1 returns the sta- tus of Set 1 during cache look-ups. Returned values are: —0 0 = i n v a l i d — 01 = exclusive — 10 = modified — 11 = shared ■ ST0 (bits 21–20): Read Only, available only in Write- back mode when Ext=1 in TR5. ST0 returns the sta- tus of Set 0 during cache look-ups. Returned values are: —0 0 = i n v a l i d — 01 = exclusive — 10 = modified — 11 = shared ■ Valid (bit 10): Read/Write, independent of the Ext bit in TR5. This is the Valid bit for the accessed entry. On a cache look-up, Valid is a copy of one of the bits reported in bits 6–3. On a cache write in Write- through mode, Valid becomes the new Valid bit for the selected entry and set. In Write-back mode, writ- ing to the Valid bit has no effect and is ignored; the Set State bit locations in TR5 are used to set the Valid bit for the selected entry and set. ■ LRU (bits 9–7): Read Only, independent of the Ext bit in TR5. On a cache look-up, these are the three LRU bits of the accessed set. On a cache write, these bits are ignored; the LRU bits in the cache are updated by the pseudo-LRU cache replacement al- gorithm. Write operations to these locations have no effect on the device. ■ Valid (bits 6–3): Read Only, independent of the Ext bit in TR5. On a cache look-up, these are the four Valid bits of the accessed set. In Write-back mode, these valid bits are set if a cache set is in the exclu- sive, modified, or shared state. Write operations to these locations have no effect on the device.

8.2 TR5 Definition

This section includes a detailed description of the bit fields in the TR5. Note: Bits listed in Table 18 as Reserved or Not Used are not included in the descriptions. ■ Ext (bit 19): Read/Write, available only in Write-back mode. Ext, or extension, determines which bit fields are defined for TR4: the address TAG field, or the STn and ST3–ST0 status bit fields. In Write-through mode, the Ext bit is not accessible. The following describes the two states of Ext: — Ext = 0, bits 31–11 of TR4 contain the TAG ad- dress — Ext = 1, bits 30–29 of TR4 contain STn, bits 27– 20 contain ST3–ST0 ■ Set State (bits 18–17): Read/Write, available only in Write-back mode. The Set State field is used to change the MESI state of the set specified by the Index and Entry bits. The state is set by writing one of the following combinations to this field: — 00 = invalid — 01 = exclusive — 10 = modified — 11 = shared ■ Index (bits 11–4): Read/Write, independent of write- through or Write-back mode. Index selects one of the 256 cache lines. ■ Entry (bits 3–2): Read/Write, independent of write- through or Write-back mode. Entry selects between one of the four entries in the set addressed by the Set Select during a cache read or write. During cache fill buffer writes or cache read buffer reads, the value in the Entry field selects one of the four doublewords in a cache line.

■ Control (bits 1–0): Read/Write, independent of Write- through or Write-back mode. The control bits deter- mine which operation to perform. The following is a definition of the control operations: — 00 = Write to cache fill buffer, or read from cache read buffer — 01 = Perform cache write — 10 = Perform cache read — 11 = Flush the cache (mark all entries invalid)

8.3 Using TR4 and TR5 for Cache Testing

The following paragraphs provide examples of testing the cache using TR4 and TR5.

8.3.1 Example 1: Reading The Cache (Write-back

Mode Only) 1. Disable caching by setting the CD bit in the CR0 register. 2. In TR5, load 0 into the Ext field (bit 19), the required index into the Index field (bits 10–4), the required entry value into the Entry field (bits 3–2), and 10 into the Control field (bits 1–0). Loading the values into TR5 triggers the cache read. The cache read loads the TR4 register with the TAG for the read entry, and the LRU and Valid bits for the entire set that was read. The cache read loads 128 data bits into the cache read buffer. The entire buffer can be read by placing each of the four binary combinations in the Entry field and setting the Control field in TR5 to 00 (binary). Read each doubleword from the cache read buffer through TR3. 3. Reading the Set State fields in TR4 during Write- back mode is accomplished by setting the Ext field in TR5 to 1 and rereading TR4.

8.3.2 Example 2: Writing The Cache

1) Disable the cache by setting the CD bit in the CR0 register. 2. In TR5, load 0 into the Ext field (bit 19), the required entry value into the Entry field (bits 3–2), and 00 into the Control field (bits 1–0). 3. Load the TR3 register with the data to write to the cache fill buffer. The cache fill buffer write is trig- gered by loading TR3. 4. Repeat steps 2 and 3 for the remaining three dou- blewords in the cache fill buffer. 5. In TR4, load the required values into TAG field (bits 31–11) and the Valid field (bit 10). In Write-back mode, the Valid bit is ignored since the Set State field in TR5 is used in place of the TR4 Valid bit. The other bits in TR4 (9:0) have no effect on the cache write. 6. In TR5, load 0 into the Ext field (bit 19), the required value into the Set State field (bits 18–17) (Write- back mode only), the required index into the Index field (bits 10–4), the required entry value into the Entry field (bits 3–2), and 01 into the Control field (bits 1–0). Loading the values into TR5 triggers the cache write. In Write-through mode, the Set State field is ignored, and the Valid bit (bit 10) in TR4 is used instead to define the state of the specified set.

8.3.3 Example 3: Flushing The Cache

The cache flush mechanism functions in the same way in Write-back and Write-through modes. Load 11 into the Control field (bits 1–0) of TR5. All other fields are ignored, except for Ext in Write-back mode. The cache flush is triggered by loading the value into TR5. All of the LRU bits, Valid bits, and Set State bits are cleared. 9A m 5 X86 CPU Functional Differences Several important differences exist between Am5X86 microprocessors and standard Am486DX microproces- sors: ■ The ID register contains a different version signa- ture. ■ The EADS function performs cache line write-backs of modified lines to memory in Write-back mode. ■ A burst write feature is available for copy-backs. The FLUSH pin and WBINVD instruction copy back all modified data to external memory prior to issuing the special bus cycle or reset. The Am5 X86 processor is functionally identical to the Enhanced Am486 processor except for the function of the CLKMUL pin (see Section 9.3) and the redefinition of TR4 and TR5 to access the 16-Kbyte cache (see Section 8).

9.1 Status after Reset

The RESET state is invoked either after power up or after the RESET signal is applied according to the stan- dard Am486DX microprocessor specification.

9.2 Cache Status

After reset, the STATUS bits of all lines are set to 0. The LRU bits of each set are placed in a starting state.

9.3 CLKMUL Pin

For the standard Am486 processor, the Enhanced Am486 processor, and the Am5 X86 processor, if the CLKMUL pin is driven High at RESET, the processor uses a Clock-tripled mode. To ensure correct operation of the 133-MHz Am5 X86 processor, always connect the CLKMUL input to VSS .

56 Am5 X86 Microprocessor

10 Am5 X86 CPU IDENTIFICATION

The Am5 X86 microprocessor supports two standard methods for identifying the CPU in a system. The re- ported values are assigned based on the RESET status of the WB/WT pin input (Low = write-through; High = write-back).

10.1 DX Register at RESET

The DX register always contains a component identifier at the conclusion of RESET. The upper byte of DX (DH) contains 04 and the lower byte of DX (DL) contains a CPU type/stepping identifier (see Table 19).

10.2 CPUID Instruction

The Am5 X86 microprocessor family implements the CPUID instruction that makes information available to software about the family, model and stepping of the microprocessor on which it is executing. Support of this instruction is indicated by the presence of a user-mod- ifiable bit in position EFLAGS.21, referred to as the EFLAGS.ID bit. This bit is reset to zero at device reset (RESET or SRESET) for compatibility with existing pro- cessor designs.

10.2.1 CPUID Timing

CPUID execution timing depends on the selected EAX parameter values (see Table 20).

10.2.2 CPUID Operation

The CPUID instruction requires the user to pass an input parameter to the CPU in the EAX register. The CPU response is returned to the user in registers EAX, EBX, ECX, and EDX. When the parameter passed in EAX is zero, the register values returned upon instruction execution are: The values in EBX, ECX, and EDX indicate an AMD microprocessor. When taken in the proper order: ■ EBX (least significant bit to most significant bit) ■ EDX (least significant bit to most significant bit) ■ ECX (least significant bit to most significant bit) they decode to AuthenticAMD When the parameter passed in EAX is 1, the register values returned are: The value returned in EAX after CPUID instruction ex- ecution is identical to the value loaded into EDX upon device reset. Software must avoid any dependency upon the state of reserved processor bits. When the parameter passed in EAX is greater than one, register values returned upon instruction execution are: Table 19. CPU ID Codes Table 20. CPUID Instruction Description

Description

EAX[31:0] 00000001h EBX[31:0] 68747541h ECX[31:0] 444D4163h EDX[31:0] 69746E65h EAX[3:0] Stepping ID* EAX[7:4] model: Am5 X86 CPU: Write-through mode = Eh Write-back mode = Fh EAX[11:8] Family

486 Instruction Set = 4h

EAX[15:12] 0000 EAX[31:16] RESERVED EBX[31:0] 00000000h ECX[31:0] 00000000h EDX[31:0] 00000001h = all versions The 1 in bit 0 indicates that the FPU is present Note: *Please contact AMD at (800) 222-9323 for stepping ID details. EAX[31:0] 00000000h EBX[31:0] 00000000h ECX[31:0] 00000000h EDX[31:0] 00000000h Flags affected: No flags are affected. Exceptions: None

The following sections describe recommended electri- cal connections for the Am5X86 microprocessors and electrical specifications.

11.1 Power and Grounding

11.1.1 Power Connections

Am5 X86 microprocessors with 16 Kbytes of cache have modest power requirements. However, the high clock frequency output buffers can cause power surges as multiple output buffers drive new signal levels simulta- neously. For clean, on-chip power distribution at high frequency, 23 V CC pins and 28 VSS pins feed the micro- processor in the 168-pin PGA package. The 208-pin SQFP package includes 53 V CC pins and 38 VSS pins. Power and ground connections must be made to all external VCC and VSS pins of the microprocessors. On a circuit board, all VCC pins must connect to a VCC plane. Likewise, all VSS pins must connect to a common GND plane. The Am5X86 microprocessor family requires only 3.3 V as input power. Unlike other 3-V processors, the Am5 X86 microprocessor family does not require a VCC5 input of 5 V to indicate the presence of 5-V I/O devices on the system motherboard. For socket com- patibility, this pin is INC, allowing the Am5 X86 CPU to operate in 3-V sockets in systems that use 5-V I/O.

11.1.2 Power Decoupling Recommendations

Liberal decoupling capacitance should be placed near the microprocessor. The microprocessor, driving its 32- bit parallel address and data buses at high frequencies, can cause transient power surges, particularly when driving large capacitive loads. Low inductance capacitors and interconnects are rec- ommended for best high-frequency electrical perfor- mance. Inductance can be reduced by shortening circuit board traces between the microprocessor and the de- coupling capacitors. Capacitors designed specifically for use with PGA packages are commercially available.

11.1.3 Other Connection Recommendations

For reliable operation, always connect unused inputs to an appropriate signal level. Active Low inputs should be connected to V CC through a pull-up resistor. Pull-ups in the range of 20 KΩ are recommended. Active High in- puts should be connected to GND.

58 Am5 X86 Microprocessor

Case Temperature under Bias . . . – 65°C to +110°C Voltage on any pin Supply voltage with Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Operating Ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges VCC = 3.3 V ± 0.3 V; TCASE = 0°C to + 85°C Preliminary Info Symbol Parameter Min Max Notes VIL Input Low Voltage – 0.3 V +0.8 V VIH Input High Voltage 2.0 V VCC + 2.4 V VOL Output Low Voltage 0.45 V Note 1 VOH Output High Voltage 2.4 V Note 2 ICC Power Supply Current: 133 MHz 931 mA Typical supply current: 825 mA @ 133 MHz. Inputs at rails, outputs unloaded. ICCSTOPGRANT or ICCAUTOHALT Input Current in Stop Grant or Auto Halt mode:

133 MHz 93 mA

Typical supply current for Stop Grant or Auto Halt mode: 50 mA @ 133 MHz. ICCSTPCLK Input Current in Stop Clock mode 5 mA Typical supply current in Stop Clock mode is 600 µA. ILI Input Leakage Current ±15 µA Note 3 IIH Input Leakage Current 200 µA Note 4 IIL Input Leakage Current – 400 µA Note 5 ILO Output Leakage Current ±15 µA C IN Input Capacitance 10 pF FC = 1 MHz (Note 6) C O I/O or Output Capacitance 14 pF FC = 1 MHz (Note 6) C CLK CLK Capacitance 12 pF FC = 1 MHz (Note 6) Notes: 1. This parameter is measured at: Address, Data, BE3–BE0 = 4.0 mA; Definition, Control = 5.0 mA 2. This parameter is measured at: Address, Data, BE3–BE0 = –1.0 mA; Definition, Control = –0.9 mA 3. This parameter is for inputs without internal pull-ups or pull-downs and 0 ≤ VIN ≤ VCC . 4. This parameter is for inputs with internal pull-downs and VIH = 2.4 V. 5. This parameter is for inputs with internal pull-ups and VIL = 0.45 V. 6. Not 100% tested.

The AC specifications, provided in the AC characteris- tics table, consist of output delays, input setup require- ments, and input hold requirements. All AC specifica- tions are relative to the rising edge of the CLK signal. AC specifications measurement is defined by Figure 39. All timings are referenced to 1.5 V unless otherwise specified. Am5 X86 microprocessor output delays are specified with minimum and maximum limits, measured as shown. The minimum microprocessor delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sam- pling window, a synchronous input signal must be stable for correct microprocessor operation. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges 33-MHz bus (133-MHz operating frequency) VCC = 3.3 V ±0.3 V; TCASE = 0°C to + 85°C; CL = 50 pF unless otherwise specified Preliminary Info Symbol Parameter Min Max Unit Figure Notes Frequency 8 33 MHz Note 2 t1 CLK Period 30 125 ns 39 t1a CLK Period Stability 0.1% Δ Adjacent Clocks Notes 3 and 4 t2 CLK High Time at 2 V 11 ns 39 Note 3 t3 CLK Low Time at 0.8 V 11 ns 39 Note 3 t4 CLK Fall Time (2 V–0.8 V) 3 ns 39 Note 3 t5 CLK Rise Time (0.8 V–2 V) 3 ns 39 Note 3 A31–A2, PWT, PCD, BE3–BE0 , M/IO, D/C, CACHE , W/R , ADS, LOCK, FERR, BREQ, HLDA, SMIACT , HITM Valid Delay 3 14 ns 40 Note 5 t7 A31–A2, PWT, PCD, BE3–BE0 , M/IO, D/C, CACHE , W/R , ADS, LOCK Float Delay 3 20 ns 41 Note 3 t8 PCHK Valid Delay 3 14 ns 42 t8a BLAST , PLOCK, Valid Delay 3 14 ns 40 t9 BLAST , PLOCK, Float Delay 3 20 ns 41 Note 3 t10 D31–D0, DP3–DP0 Write Data Valid Delay 3 14 ns 40 t11 D31–D0, DP3–DP0 Write Data Float Delay 3 20 ns 41 Note 3 t12 EADS , INV, WB/WT Setup Time 5 ns 43 t13 EADS , INV, WB/WT Hold Time 3 ns 43 t14 KEN , BS16, BS8 Setup Time 5 ns 43 t15 KEN , BS16, BS8 Hold Time 3 ns 43 t16 RDY , BRDY Setup Time 5 ns 44 t17 RDY , BRDY Hold Time 3 ns 44 t18 HOLD, AHOLD Setup Time 6 ns 43 t18a BOFF Setup Time 7 ns 43 t19 HOLD, AHOLD, BOFF Hold Time 3 ns 43 t20 RESET, FLUSH , A20M, NMI, INTR, IGNNE, STPCLK , SRESET, SMI Setup Time 5 ns 43 Note 5 t21 RESET, FLUSH , A20M, NMI, INTR, IGNNE, STPCLK , SRESET, SMI Hold Time 3 ns 43 Note 5 t22 D31–D0, DP3–DP0, A31–A4 Read Setup Time 5 ns 43, 44 t23 D32–D0, DP3–DP0, A31–A4 Read Hold Time 3 ns 43, 44 Notes: 1. Specifications assume CL = 50 pF. I/O Buffer model must be used to determine delays due to loading (trace and component). First Order I/O buffer models for the processor are available. 2. 0-MHz operation guaranteed during stop clock operation. 3. Not 100% tested. Guaranteed by design characterization. 4. For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency. 5. All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.

60 Am5 X86 Microprocessor

Am5 X86 Microprocessor AC Characteristics for Boundary Scan Test Signals at 25 MHz VCC = 3.3 V ±0.3 V; TCASE = 0°C to +85°C; CL = 50 pF unless otherwise specified Preliminary Info Symbol Parameter Min Max Unit Figure Notes t24 TCK Frequency 25 MHz 1x Clock t25 TCK Period 40 ns 45, 46 Note 1 t26 TCK High Time at 2 V 10 ns 45 t27 TCK Low Time at 0.8 V 10 ns 45 t28 TCK Rise Time (0.8 V–2 V) 4 ns 45 Note 2 t29 TCK Fall Time (2 V–0.8 V) 4 ns 45 Note 2 t30 TDI, TMS Setup Time 8 ns 46 Note 3 t31 TDI, TMS Hold Time 7 ns 46 Note 3 t32 TDO Valid Delay 3 25 ns 46 Note 3 t33 TDO Float Delay 36 ns 46 Note 3 t34 All Outputs (Non-Test) Valid Delay 3 25 ns 46 Note 3 t35 All Outputs (Non-Test) Float Delay 30 ns 46 Note 3 t36 All Inputs (Non-Test) Setup Delay 8 ns 46 Note 3 t37 All Inputs (Non-Test) Hold Time 7 ns 46 Note 3 Notes: 1. TCK period ≥ CLK period. 2. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK period. 3. Parameter measured from TCK.

62 Am5 X86 Microprocessor

Figure 41. Maximum Float Delay Timing Figure 42. PCHK Valid Delay Timing

64 Am5 X86 Microprocessor

Figure 45. TCK Waveforms Figure 46. Test Signal Timing Diagram

12 PACKAGE THERMAL

the top surface opposite the pins. a maximum ICC value of 931 mA at 3.3 V. Table 21. Thermal Resistance (°C/W) θJC and θJA for the Am5X86 CPU in 168-Pin PGA Package Table 22. Maximum TA at Various Airflows in °C Table 23. Maximum TA for SQFP Package by Clock Frequency

66 Am5 X86 Microprocessor

13 PHYSICAL DIMENSIONS

1.735 1.765 1.735 1.765 Bottom View (Pins Facing Up) Base Plane Seating Plane 0.140 0.180 0.110 0.140 0.105 0.125 0.017 0.020 Side View 168-Pin PGA 0.025 0.045 1.595 1.6051.595 1.605 Index Corner 0.090 0.110 Notes: 1. All measurements are in inches. 2. Not to scale. For reference only. 3. BSC is an ANSI standard for Basic Space Centering.

Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only. 30.40 30.80 27.90 28.10 25.50 REF Pin 156 Pin 208 Pin 52 Pin 104 Pin 1 I.D. 27.90 28.10 Seating Plane 0.50 BASIC 0.05 Min 3.25 3.45 3.70 Max. Top View Side View 25.50 REF 30.40 30.80 208-Pin SQFP Trademarks AMD, Am386, and Am486 are registered trademarks and Am5X86 is a trademark of Advanced Micro Devices, Inc. FusionPC is a service mark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 0.50 0.75