AM95C75

AM95C75 AMD | Alldatasheet

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Raster Printer Controller (RPC) Devices ee DISTINCTIVE CHARACTERISTICS ® 20 Mb/s printing of combined text and graphics ™ Supports two band buffers with automatic virtual = Triple-bus architecture for independent host, font — to reduce memory memory and page buffer interfaces and direct connection to print engines ® On-board programmable DRAM controlier with ® Supports any combination of transparent, opaque rotrest and textured images at pixel addressable ® Synchronous or asynchronous interface to print positioning engines with a broad range of page size and © 24-bit addressing provides for page buffers up to marine 16K x 16K pixels and 16M words of font memory ™ Operating modes for direct interface to Am95C76 space Orthogonal Rotation Processor (ORP) BLOCK DIAGRAM FAD; FAD 15 PX VRAS VWE y L\\ FALE2 VA Controller FRD Video VAD, VAD. >< Address ><] 2.- D ° 8 Generator o 8 PSYNC ‘Sean AQ A, rome te Transaction Central cPU ae VeLK Control onto Interface RDY sters Mode we bra CLK INTR DRO 09931-001A Puricatoné 09031 Rev A Amendment 0 tesue Date: December 1998 Am95C75 5-83

The Am95C75 Raster Printer Controller (RPC) is a high- nals provided by the print engine. Pixel data is serialized performance CMOS processor for controlling the real- at a rate controlled by the Video clock (VCLK). Page time requirements of a raster printing system. It is de- Size and Margins are determined by the values pro- signed to assemble text and graphical images into a par- grammed in the RPC control registers. In systems tial or full page buffer from either of two memory spaces where two band buffers are used, one band may be as- or from the host and serially transmit that image infor- sembied while the other band is being scanned out. The mation to an asynchronous print engine. A high degree RPC manages all address conversion so that the host of programmable options assures simple interfacing toa need only provide a destination address for each image broad range of host, memory, and printer contigura- block that corresponds to the virtual position of that tions. block on the full page. Band control logic in the RPC in- TheRPC anddest address intor- Sures that the bands alternate properly according to the receives source ination scanning requirements of the printer. image blocks or mation (or image data) from the host CPU or DMA con- fonts that are sliced by a band boundary cause inter- troller, and performs block transfers of data to rectangu- Tupts that allow the remaining portion to be transferred lar areas at the destination address in the butter. The im- into the next band age blocks are of arbitrary size and pixel alignment and ° may be combined with background information using The system bus interface of the RPC allows the control the overlay options. Characters may be textured using fegisters to reside in host VO or memory space and op- the additional source address of a texture word or array. erations are initiated automatically when the address in- In addition to the buffer assembly operations, the RPC formation for the transfer is provided. An internal ad- can transfer font or graphic information with the host to dress pointer sequences through the control registers or from the static RAM or ROM Font memory or the required to setup a block transfer so that the host may DRAM Video memory of the buffer. Two other modes write them to a single port address if that is desired. The Support reading and writing of the Am95C76 Orthogonal RPC will interrupt the CPU or request a DMA when the Rotation Processor (ORP) which resides in Font mem- transfer is complete. Interrupt options allow the host to ory space. be updated on transfer, printing, and error conditions by Printing can begi a page or band is completely reading status information. assembled and is controlled by Page and Line Sync sig- — SSSSeeeeeeSeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSssssssssssseseseseF 5-84 Am95C75

a CONNECTION DIAGRAM PLCC alalalaNalalalalalalalalslaleleletelalala wre Cie TAP FAD vr 3 732) FAD, we a pas vers Chis noa, Was Cis np a, Vsp 17 eof] Ac psync C18 eof) TR usync C19 67) bro Ves [20 66—) RADY veux C2 651) Vs voo Chee isk vao,, G2? eft van,, 424 62— RD van. Ges 619 0, van, G26 60f 0, vao,, G27 sof 0, van, C28 ssf 0, van, (429 s7p) & vaDs [30 56 0, Ves (31 cS a van, 432 54 Vi 7 33 34.35 36 37 3839 40 41 4243 4445 46 47 48 49 50 51 52 53 COCCUUUUU COU ooo 5 | 3994 i232"5 5 edaddacake tf onzat-c0ah a ‘Am95C75 5-85

Se ad 2-85 VAD (VAD 45 cpu ——*IRD VCRS Video Interface —__p lian, A interface —+|cs We ROY VAFE NTR DRQ ——?PI cK ——+| sync FALE2 imtorlace ——>| tsync FALE intritce — FI] veLK FRD vo FWR Noo. omaat-co4n eee 5-86 Am95C75

ORDERING INFORMATION

‘AMD standard products are available in several packages and operating ranges. The ordering number (Valié Combination is formed by a combination of: 8. Device Number olleab . Option (It applicable) ¢. Package Type . Temperature Range ¢. Optional Processing AM95C75 J c TL. oprionat processina Blank = Standard Processing d. TEMPERATURE RANGE C= Commercial (Te = 0 to 85°C) ¢. PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrior (PL 084) b. SPEED OPTION Not Applicable 2. DEVICE NUMBER/DESCRIPTION ‘Am95C75 Raser Printer Controller (RPC) Valid Combinations Valld Combinations Valid Combinations list configurations planned to bbe supported in volume for this device. Consult the local AMD sales office to confirm availabilty of specific valid combinations, to check on newly re- leased combinations, and to obtain additional data on AMD's standard military grade products. Am95C75 5-87

Interface Signal Description The RPC has four independent groups of pins to inter- Am95C76 ORP. The Video Memory Interface connects face to the other resources of the printing system. The _to standard Dynamic RAMSs for the page buffer or for CPU Interface connects to the host to provide controlof _storage of downloaded fonts or other data. This latter all operations. The Font Memory Interface connects to case permits a system with a single memory architec- anoptional static memory of RAMor ROM{orstorage of _ture. The Printer Interface accepts timing information character fonts, textures and other blocks of data. The _from the print engine and supplies serial pixel data for Font Memory interface also interfaces directly to the the rasterized page. CPU Interface Signals Ac-As INTR Address Bus (Input) Thterrupt (Output; Active LOW) The 4-bit Address Bus is used to select one of sixteen The interrupt output is driven LOW whenever the RPC internal registers for reading or writing. it must be held detects a condition that requires the attention of the valid while the access is taking place. CPU and the Interrupt Enable bit is set. Interrupt is cLK driven HIGH when status is read by the CPU to identity the cause of the interrupt. All interrupt status bits are Clock (Input) cleared after the register is read. The Clock input provides the timing reference forallop- __ erations controlled by the RPC except printing. Allmem- RD ‘ory operations on the Font or Video Interfaces willoccur Fead (Input; Active LOW) felative to Clock edges. Accesses onthe CPU Interface The active-LOW Read input determines when the con- ‘may be asynchronous to the Clock. tents of the selected internal register are driven onto the Ss Data Bus. Thip Select (Input; Actve LOW) RDY Chip Select must be held LOW to qualify areadorwrite Ready (Output) access by the host. Chip Select may be held LOW for The Ready outputis driven LOW at the start of a Reador multiple accesses. Write access when the data is not immediately available De-Dis ‘or cannot be accepted. The host must insert wait states . and hold Read or Write active unti! Ready goes HIGH to Data Bus (Input/Output; Three-State) complete the access successfully. If Read or Write go The 16-bit bidirectional Data Bus is used for all read and HIGH while Ready is being driven LOW, the access is write accesses by the host system. The bus is anoutput aborted and Ready will go HIGH. In this abort case, wheneverCS and AD are active and is an input when- —_there is no guarantee that the access was accepted or everCS and WR are active. ignored. DRG RESET ‘DMA Request (Output; Active LOW) Reset (Input; Actve LOW) The Data Request output is driven LOW when the RPC. The active-LOW RESET input causes the RPC totermi- is ready to accept the address information required to _nate any operation in progress and enter the idle state. transfer an image block and is driven HIGH when the RESET must be held LOW for a minimum of four CLK last word of address informations received. Five words —_—_ cycles. After Reset, all bidirectional buses will be in a are required for a normal Dispatch operation and eight ~—_ high impedance state and all internal registers must be words are required for a textured Dispatch operation. _ programmed to begin operation. Data Request will only be driven LOW when the RPCis = |_* in Dispatch, ORP Load or ORP Read Mode. It is in- WA tended for direct connection to a DMA controller. Write (Input; Active Low) The active-LOW Write input determines when the con- tents of the Data Bus are loaded into the selected inter- nal register. 5-88 Am95C75

Font Memory Interface Signals FAD:-FADis be latched on the HIGH-to-LOW transition of FALE2. Font Address/Data Bus (Input/Output; Three-State) ime upper address cycle, containing FALE2, is some: The 16-bit bidirectional Font Address/Data Bus carries _imes Skipped when the upper address is unchang all address and data information for Font Memory ac- "the previous memory cycle, cesses. The presence of information on this bus is a- = FRD ways controlled by the signals described below. Font Head (Output; Active LOW) FALE1 ‘The active-LOW Font Read outputis driven LOW during Font Address Latch Enable 1 (Output) a Font Memory access when data is to be driven onto The FALE: outputs driven HIGH when the least signif _the FAD,-FAD,.bus by the memory. FRDstays lowfor 1 cant 16bils of the 24-bit Font Memory address are being: t08 CLK cycles depending on the number of Font Mem- driven onto FADe-FAD's. This addressinformationmust ory Wait states programmed. be latched on the HIGH-o-LOW transition of FALE’. Ea The lower address cycle, containing FALE1, occurs on gvery memory cycle "9 Font Write (Output; Active LOW)

2 The active-LOW Font Write output is driven LOW when

FALE: valid data is being driven onto the FAD.-FADus bus by Font Address Latch Enable 2 (Output) the RPC to be strobed into the Font Memory. FWA stays The FALE2 outputs driven HIGH when the most signifi low for 1 to 8 CLK cycles depending on the number of cant 8 bits of the 24-bit Font Memory address are being Font Memory Wait states programmed. The FAD data driven onto FAD»-FAD;. This address information must _out is valid for the duration of FWA. Griven onto FAD. FAD;. This aces ———r—Eeeereereoeerrrrerree—— Video Memory Interface Signals VAD.-VAD:s Video Memory address being driven out and the mem- Video Address/Data Bus (Input/Output; Three- ory data being received by the RPC. mete bil bidirectional Video Address/Data Bus carries VBA -raaraae STOBS - 4 7 7 all address and data information for Video Memory ac- leo Row Address (Output; Active LOW) cesses. The presence of information on this bus is al- The VRAS output is driven LOW to indicate that a valid ways controlled by the signals described below. row address is being output on the VAD,-VAD,; bus. YRS The HIGH-to-LOW transition of VRAS is normally used VCA‘ to strobe the row address into dynamic RAMs. Video Column Address Strobe (Output; Active Low) VRFE The VCAS output is driven LOW indicate that a valid Video Refresh Enable (Output; Active LOW) El column address is beingoutputonthe VAD.-VAD,,bus. The VAFE output is driven LOW for the duration of a The HIGH-to-LOW transition of VCAS is normally used Video Memory Refresh operation. This signal can be to strobe the column address into dynamic RAMs. The —_used to control the bank select decoder so that all mem- column address cycle follows a row address cycle ex- _ory chips receive RAS onthe refresh row address cycle. cept during memory refresh operations. = va VWE Video Write Enable (Output; Active LOW) Video Read (Output; Active LOW) The VWE output is driven LOW to indicate that valid The VA output is driven LOW to indicate that external_—_gatais being output onthe VAD.—VADis bus. The HIGH- VAD bus transceivers should drive Video Memory data —_to-LOW transition of VWE is normally used to strobe onto the VADe-VAD,; bus to be input by the RPC. This gata into dynamic RAMs. signal canbe used to avoid bus contention between the a Am95C75 5-89

Line Syne (Input) Video Clock (Input) The LOW-to-HIGH transition of the LSYNC input is used The VCLK input determines the data rate for serializa- tostartascanline sequence that may consistof adecre- _tion of pixel data on the VDO output during scan out. If ment of the Y-Margin count or the start of the X-Margin the Printer Interface is being operated in Synchronous control process prior to the scan out of serial pixel data Mode, the serial data rate equals the VCLK rate. In for a line. LSYNC will only be recognized if the condi- Asynchronous Mode the data rate equals the VCLK rate tions for a PSYNC have been met. divided by four. The mode determines whether LSYNC. must be synchronous to VCLK in addition to the VCLK PSYNC division control. PSYNC has no timing requirement re- Page Sync (Input) lated to VCLK in either mode. The LOW-to-HIGH transition of the PSYNC input is vDo used to start the Y-Margin control process if the RPC has been initialized to scan out the serial pixel informa- Video Data Out (Output) tion of a page on the VDO output. PSYNC will be recog- The VDO output provides the serial pixel data that is nized if the RC bit in the Mode Register is set and the used by the print engine to scan out the page. When the beginning of the first scan line has been loadedin the the Printer Interface is inactive or during the X or Y Margin RPC shift register. Otherwise PSYNC will be ignored. time, the VDO output remains HIGH. VDO may toggle at the pixel rate during the active page area and the output polarity is selected by the VP bit in the Mode Register. 5-90 Am95C75,

has a unique location as selected by the A.A, address. nation Address Registers according to Table 1. Table 1. RPC Registers

0 Temporary Register (Temp)

2 Margin Register (XMGR, YMGR)

3 Page X Size Register (PXSR)

4 Page Y Size Register (PYSR)

5 Video Band Boundary Register (VBBR)

6 Video Memory Refresh Rate Register (VMRR)

7 Memory Timing Register (MTR)

9 Source Address Register 2 (SAR2)

10 Source Address Register 3 (SAR3)

12 Texture Address Register 2 (TAR2)

13 Texture Address Register 3 (TAR3)

15 Destination Address Register 2 (DAR2)

For Dispatch operations, the address registers may be active until the internal operation is complete. vided by the RPC. This allows all words to be written to used for writing values to the SAR, TAR and DAR words. for each non-textured Dispatch. port addresses.

Table 2. Mode Control Field cycle is used to allow the same page to be scanned out ‘ fais ready to be serialized onto the VDO pin, the RPC. continuously as subsequent pages are printed and then are ignored. is printed to controlthe limit of physical memory spacein _*"Toneously starting a new page. Video Data Out (VDO) pin indicates a blackimage anda UPI condition that was pending. Bit 10 of the Mode Registeris the interrupt Enable bit. In. C@US€S an interrupt and clears RO.

lispatch any partial characters to the nex! first. hi in, A full 16-bit i . second Dispatch operation (of the same or different “USING the Y Margin. A full 16-bit value is supported. tion completed transferring the entire image block. This beginning of the second band in Video Memory space. Dispatch Incomplete is indicated by bit 0 of the Status _the page. Margin Register used and the frequency of the CLK input. Page X Size Register signments of this register. including the X Margin. A full 16-bit value is supported. Figure 3. Memory Timing Register

ofthe MTR withbit 10 being the most significant bit. This. 39 MHz may be used in this Asynchronous mode. The options, 64K, 256K and 1M, result indifferences in _ precharge time. This may be required for some RAMS. Table 3. VMS Control Field dress is held valid on the VAD bus and the falling edge of 0 1 256K VADis-VADs — VADe-VADo Refresh cycles. operations. If this VCK bitis a zero, Synchronous mode Out by one CLK. This may be required for some RAMS. ‘An important feature of the RPC relates to Asynchro- "© the number of waits desired.

Figure 4. Source Address Register Source Address Registers zero, the character is loaded from the Font Memory. Dispatch operations. This information is assumedtobe Memory. correct when the Dispatch is initiated by loading DAR2. —_ git 14 of SARB is the Address Hold bit. When this bit is. The upper 8 bits of this 24-bit address are heldinthe low _‘fixed location like the ORP. an operation progresses, reads of SAR1 or SAR2 may pit is set, a Textured Dispatch operation is performed. Bit 15 of SAR@ is the Bus Select bit forthe source ofthe grammed.

nificant bits hold the Destination Offset field of DAR1, Load mode. Video Operations Table for details. n Font Load, Font Read and ORP modes, DAR holds , . four most-significant bits of DAR2 hold control informa- must be zero and the OQ bit must be a one. the BS bit is ignored. The destination for Dispatch and _ “white” pixels until the correct Page Y Size is reached. Table 4. Video Operations

The RPC performs six operating modes to support the Write cycles are performed onthe Video Memory words, transfer of pixel data among the memory resources of a the new image data is shifted as needed and any partial printing system. These modes may be used to obtain words outside the sides of an image block are masked capabilities and performance beyond the range of a ‘so they remain unchanged. Dispatching progresses general purpose processor executing the same tasks. trom left to right and top to bottom. The width must be Working jointly with a host processor, the RPC frees the specified in words and the image block must fit in the host from the heavy data transfer burden, and allows it available Page X Size rounded up to a multiple of 16 pix- to perform higher level tasks for which itis bettersuited. _els. (The block can’t extend beyond the right side of the Together, the RPC and host CPU can implement the page.) post sophisticated features of an advanced printing — 14 gata options for a Dispatch are controlled by the TX . bit in SAR3 and the Color (CL) and Opaque (OQ) bits in The fundamentat operation for which the RPC is opti: | DAR2. When TXis set, the RPC reads the first word of mized is the transferring of stored rectangular image the Source image followed by the first word of the Tex- blocks to the page buffer. This is Dispatch mode anda __ture. Then the first RMW cycle is performed at the Desti- number of options are available to augment it. In addi- nation. This may modify a full word or partial word de- tion, three modes are providedto allowtransfersof data __ pending on the offset. This sequence allows the image, between system memory space and the two memory in- texture and any background information in the Video terfaces controlled by the RPC. Graphics Loadmode al _buffer to be combined. When the BS bits in SAR3 and lows rectangular image blocks to be written to the page. TAR3 are both zero, indicating Font Memory, the read buffer with the same overlay options as Dispatch. Font accesses after the first can occur in parallel with the Load and Font Read modes allow data to be transferred Video Memory cycles to achieve higher performance. If for storage and retrieval in a sequential word manner. _the Font is stored in Video Memory, accesses can not ORP Load and ORP Read modes allow the RPC toeffi- occur in parallel. If only the Texture is stored in Video ciently work with the Am95C76 ORP to rotate image Memory, Font accesses can still be in parallel. Without blocks in the process of assembling the page buffer. texturing, the highest performance is obtained since one Dispatch access is eliminated. Dispatch is selected by writing 011 to the Mode Control. + When a Dispatch operation completes, the Dispatch field. Then inorderto milate a Dispatch, the CPU must Complete (DC) bitin the Statusis set andthe DRO pinis load the Source Address Registers (SAR1-3) andDesti- activated to request the next Dispatch. (DRO can only nation Address Registers (DAR1-2) and optionally the be activated when the RPC is in Dispatch or ORP Texture Address Registers (TAR1-3) if texturing is de- odes.) In cases where a Dispatch cannot complete sired. Loading these address registers may be done by normally, the INTR pin is activated. These interrupt con- writing to the explicit port location foreachone orby writ _ ditions may be used for systems where the Video buffer ing them in sequence to Port 0. The sequence is SAR- _s divided into two bands. DAR (tive words) or SAR-TAR-DAR (eight words) for@ video Bands 5 | textured Dispatch. The TAR words must be inserted if the Textured Font bit (TX) in SAR3 is set. The DAR The RPC provides full support for systems having a words must be written last to deactivate the DRG pin Video Memory space that iS much ‘vetemn ful page. i ° ‘These features can also be used in s; iaving | and trigger the start of the Dispatch operation. full page buffer areas since the total memory space is ‘The Source image and texture may be stored in either —_fimited only by the 28-bit address of the DAR. When the Font or Video Memory independently, as selected by —_Video buffer is divided into two bands, Dispatching can their respective Bus Select (BS) bits. They willbe read _be in progress in one band while printing is supported from consecutive word locations unless Address Hold from the other band that has already been Dispatched. (AH) is selected for either. AH is useful for areafillorfor The bands alternate function in this manner until a page, one-word textures. The texture addressing will not al- —_or multiple pages are complete. This approach allows ways be for consecutive memory locations if the Texture printer performance that may be limited only by the pixel Image Widthis greater than the Source Image Width. In __rate of the print engine. this case, a new line of texture will be started with each " " new line of the Source image so that it will be consis Since printing canbe enabled by setting the Raster Con- tently applied to images of varying size. Bit 15 of each _—‘{7Ol bit (RC) in the Mode register as soon as the first image data word is assumed to be the left-most pixel band ts Dispaiched, tna cre completely Di sone parla

2 Gata wore Peston Cl rs

and Bi Qi is the right-most as they arereadtromthe stor. Peneetine and is begun. Each subsequent band of the page must be fully Dispatched in the time it The destination for Dispatch is aways Video Memory. A takes to print the previous band, and Dispatching cannot Dispatch operation does not needtobe wordaligned,as progress into the next band until the printing of its previ- the DAR provides a 28-bit address where the fourleast = —_ous contents is complete. The band control logic of the significant bits of DAR 1 are an offset to indicate the posi- RPC will ensure that the printer is supplied with a con- tion of the starting pixel in each word. Read-Modity- een eect Am95C75 5-99

tinuous flow of pixels and that Dispatching is held off if _ Ina system with a single full-page bail an £00 se- necessary. quence is not required. Instead, printing can be enabled , . after the last Dispatch of the page. After printing is com- The fst band will aways start at cation 0000000Hex Anis ne nacatca by ine Eroiey Page iertuny a Sott in Video Memory, which corresponds to the upper left ware Reset must be written to the Mode Register. This corner. The size of the two bands is determined by the Causes internal registers to be adjusted so that the next value programmed in the Video Band Boundary (VBB). —_ age will begin at the top of Video Memory space. Then This value must be the address of the first word of the Dispatch mode can be reselected and the next page can second band. During Dispatch of the firstband,theRPC be etarted, compares the current destination address to the VBB. If itis greater than or equal to the VBB, the Dispatch is Graphics Load Mode Sopped the Dispatch Incomplete (Dl) flag is set and Graphics load is selected by writing 110 to the Mode INTR is activated. control field. Then SAR1 must be loaded with the correct i Image Width in words, and the DAR must be loaded with ‘The DI interrupt must be processed by the Host CPU lo the 2e-bit address of the upper lelt-hand comer of the andie the cases of characters that were sliced by the Ne 28-6 4 ind boundary. This requires reading the contents of tination. A Graphics Load block does not have to be Ke 4 A Ad saving this i word aligned. The four least significant bits of DAR1 are the SAR, TAR (fused) and DAR, and saving this infor ic ot to indicate the position of the starting pixel in mation in a sliced character table in system memory. h rd, Each Je to the ‘ination in ‘These partial characters can be Dispatched into the Video Me . Ea i ‘gered ecPU any des a date next band after the current band is complete. In the DI net lemory is' psy ty aor t wr ee ene, case, the DRO pinis activated orthe next Dispatch af- __to'e Femboraly Register a a ai ee oace ter DAR2is read. The remaining full orpartial characters eae psa " ihe es som a Sennund nae are Dispatched to the current band and DI is activated rat ne ing tothe Cla oad OCT ks of DAR, inthe whenever a sliced character is detected. cane oe ae anach. " When the starting address for a Dispatch equals or ex- ceeds the current band boundary, the operation is not Graphics Fad progresses eth ince Width have initiated, the Band Dispatched (BD) flag SnTa the cur Seen writen, Then the RPC calculates the start of the vated “This provces the oop arty to Dispatch 8 acl next horizontal line of the block according to the Image rates Y Width and the Page X Size Register, and continues with tries in the siced character table to the new band. The ha sscuence of page words bei tecelved trom the 8D interrupt wil be delayed i the previous data in th@_ C5) ‘Ling will continue from the top down until the new band has not been completely scanned out to the C5) stops writing to Port 0. the DAR offset is not zero, brite. Aiter BD fs set the second atlemptto Dispatch ast worguriten bythe CPU should complete a hor into the new band will be accepted. there arenosliced ora line. Ita partial line is desired, the last portion of ae eee re codibeccntaecontine (ke, the last word writen mid-tine will not be transferred to ferof the newband shouldbe sentasecondtime.(Ac- —h , tually only the DAR words need to be rewritten to trigger ee wom unless ore gee word is written by the the Dispatch.) . This extra word st blank. The RPC calculates the current band boundary fromthe Graphics Load is effectively terminated when the CPU VB and automatically converts the DAR provided into oeenelght regu eo the staring DARI asgumadiobe the correct physical memory address for the current 4 physical memory location desired and no address band. Characters need only be sorted according to the conversion is performed to adjust for the current Video Virtual address on the fullpage. Each horizontalline of a Porversion is Performed 0 ach oe rae eed characteris maintained in the correct position according among Dispat ch operations e Yong as the image to the Image Width and the Page X Size Register. al ne image block fits in the current band and the DAR provided is the cor- Atter the last Dispatch of the band that has the last char- rect physical memory address. This should always be acters on a page, one final set of DAR words must be __the case in a full-page butfer system. written to the RPC with the End-of-Dispatch (EOD) flag i i ‘ti Video Data Operations set. This may be accomplished by writing to Ports 14 and 15 explicitly, or by sending a dummy Dispatch se- _n Dispatch yan Graphics Load the GL and herd options quence to Port 0. When EOD is detected, the rest of the determine how the image is combine the back- registers are ignored and an internal operation is exe- ground. when CLis 2970, tne acive area ofa character cuted. This marks the bandas the last of apage and al- _is printed. as ones, or black. When CL is aone, the char- lows the next Dispatch to begin a new page without acter is printed as zeros, or white. When OQ is zero, the causing any interrupts. The current page may contain _inactive pixels of an image block willbe transparent and multiple blank bands after the one marked by EOD. The allow any background information to show through. RPC will automatically scan out “white” until the Page Y © When OQis a one, the inactive pixels will white-out any Size Register indicates that the page is complete. Dis-_ background information. both CL and OQ are set, the patching of the first band of the next page does not have normal resultant pixels (i.e., when CL equals zero and to be delayed to accomplish this. 00 equals one) get reversed. The active pixels of a 5-100 Am95C75

a character will become zeros unless they are tobe tex: _readitout. Each access of Port 0 by the CPU causes the tured and the texture pixel is a zero, then they will be DAR to be incremented and another word to be read ones. The inactive pixels of the block will become ones —_fromFont or Video Memory. The CPUcan read as many and effectively black-out any background. Table 4 words as desired, change the DAR or program a new shows the result for all combinations of data and op- —_ operation as needed. tons. ORP Load Mode Font Load Mode ORP Load Mode allows the RPC to load data from the Font Load Mode is used for storing information fromthe FontMemory tothe Am95C76 for character rotation. Itis CPU to Font Memory or Video Memory. It is selected by selected by writing 010 to the Mode Control field. SAR1 writing 100 to the Mode Control field. The DAR must be must be programmed with a word count that is the exact programmed with a 24-bit address and the Bus Select _ number of words to be loaded into the ORP. The DAR bit must be zeroto indicate Video Memory oroneto indi must be loaded with the 24-bit address for the first word cate Font Memory. Since Font Load performs word to be loaded. When DAR2 is loaded, the RPC executes aligned write oycles to the destination, the OQ bit must. _a continuous stream of Font Memory read cycles until be aone and the CL bit and the offset field must be ze-___ the word count reaches zero. BS, CL, OO, andthe offset ros. inthe DAR are ignored. The data can be strobed intothe , ; ORP and is of no consequence to the RPC. When the Font Memory write cycles are triggered each time the word count in SARI has been decremented to zero, the CPU writes to the Temporary Register at Po Oy, RPC willset the DC bit and activate the DRG pinto re: eo ress is incremented alter each wie CY” quest the next operation. The CPU can altemate ORP cle. The operation ends when the CPU stops wriling Load and Dispatch operations in order to transfer ro- data to Port 0, or a new operation is programmed. The —_tseq characters to the Video butler. DAR may be changed as needed for multiple Font Load : operations. ORP Read Mode rom| jo be stored i lemory. Iti fe Font Read Mode allows the CPU to access storedintor- by writing 001 tothe Mode Control field. SAR1 must pro- mation in either the Font Memory or the Video Memory. grammed with the word count and the DAR must be INis selected by writing 101 fo the Mode Corto! felG” loaded withthe 24-bit address ofthe destination of the 1@ DAR must be programmed with a 24-bit address for first word. Loading DAR@ triggers a continuous stream the first word to be read and the Bus Select bit must bef Font Memory write cycles until the word count zero t0 indicate Video Memory or one to indicate Font Teaches zero. The RPC does not drive any data onto the Memory. The CL, OQ, and offset field are ignored FADo-FADis bus during the FWA strobe. This is pro- Assoonas DAR2is loaded, the RPC readsthefirstword vided by the ORP in the proper sequence. The DC bit into the Temporary Register and waits for the CPU to and the DRQppin are activated as in ORP Load. ee Am95C75 5-101

The RPC provides a number of programmable options The polarity of the VDO output is selected by the Video in order to easily interface to a variety of print engines Polarity (VP) bit in the Mode Register. When VP is a and accommodate a broad range of page sizes. This in- zero, VDO outputs a HIGH level to indicate a black (ac- formation must be programmedinto the appropriate Op- _ tive) pixel and aLOW level to indicate white. When VP is eration Control Registers (OCR) before printing is init- aoe, VDO outputs aLOW for black and HIGH forwhite. ated. Some of the OCR words are required to execute _Inanycase, VDOiis driven HIGH when printing is idle or memory operations and it is recommended that the en- printing is outside the active page area defined by the tire OCR be loaded after the power-up and Reset. This page size. Feancornihhat por Mier andthe paced Minka Printing cannot be initiated until the Video butter has scending order to the Mode at Port 1. This insures that been prepared with the first page or band using Dis- the Refresh Rate willbe setup before Refreshis enabled Patch or Graphics Load. Once this has been done, the and that all other options are correctly initialized. Page ‘Raster Complete (RC) bitin the Mode Register may be Size and Margin valies may be altered as needed for _setandthe RPC willloadthe internal shift register forthe different pages but this must be done before any Dis- __VDO output with the first word from Video Memory loca- patching or Graphics Load operation is started. tion 000 0000 hex. Normally Read-Modify-Write cycles Im most systems an Opaque Dispatch operation should _tenwithzeros as scanning progresses in preparation for be used to initially clear the entire Video Memory butter. the next band or page. If he MPC bit is set in the Mode The SAR canbe held pointingto an all zero word. Since Register, read cycles are used for scan-out so that the the maximum size of a Dispatched block is 4096x4096 same full page can be printed more than once. MPC pixels, several operations may be required. Once this is shouldbe set in advance of RC, or itcanbe set with RCit done after power-up, The RPC will automatically clear there is no memory operation in progress. Maple Page aaon Gach page is printed, unless the 116 PG provides two interrupts to simplify the control " of pring. The End-of-Page flag in the ModerStats The Printer Interface may be operated in either Syn- Register is set and the INTR pin is activated when a chronous or Asynchronous Mode, depending on how —_ number of lines equal to the Page Y Size Register have the print engine timing generates LSYNC relative to. been shifted out on VDO. The RC bit is automatically VCLK. Ifthe rising edge of LSYNC occurs synchronous —_cleared at this time. This interrupt canbe used to control to VCLK and meets the setup time required, SYNC when the next page is started or when the Muttiple Print Mode can be used and the pixel rate onthe VDO pinwill Control bit (MPC) should be cleared before the last equal the VCLK rate. If LSYNC has no fixed timing rela- printing of a single page that was printed muttiple times. tionship to VCLK, ASYNC Mode shouldbe used andthe RC cannot be set if EOP is active. ixel rate will be the VCLK rate divided by four. PSYNC — heeds no fixed timing relationship to velK, but the ris- The Raster Incomplete (Ri) flag indicates an error condi- ing edge of PSYNG must precede LSYNG by a mini. tion during printing that cannot be recovered from. Rlis mum of one VCLK so the Y Margin may be evaluated. Set when an LSYNC is detected in the middle of an ac- The printer mode is selected by the VCK bit inthe Mem- _ tive scan line. LSYNC cannot be accepted until a num- ory Timing Register at Port 7. ber of pixels equalto the programmed Page X Size have beenscannedout. RC is cleared i Rlis set andthe RPC must be programmed to start over on a page after the cause of Rl has been determined. 5-102 Am95C75

a System Interface The System Interface of the RPC can be operated com- polled to determine when each Dispatch is complete by pletely asynchronously to the CLK input. Accesses by _ testing the DC flag. Status flags are only cleared after the host CPU or external DMA controller may be made —_ Status is read, so DC can stay active through multiple at any time and will be intemally synchronized by the Dispatches. The RDY output may be used to extend RPC. The RDY output will be driven inactive if the ac- CPU accesses until the RPC is able to accept new infor- cess cannot be immediately completed. mation, but this may be a long time during a large Dis- ch and care must be t to modify essenti During Dispatch or ORP modes, the DAGoutputcanbe Pach and care. taken rot ity al values in the middle of an operation. The Mode/Status used to contro! when the RPC is ready for the next op- Re " ” tegister is always accessible to the CPU but some eration to be programmed. DRQwill be driven active a- changes to control bits may not take effect immediately ter each operation is completed orwhena Dior BD inter- if an operation is in progress. Software Reset and rupt has been handled. Alternatively, Status may be changes to RC are always recognized. Font Interface Font Memory cycles may be programmedior automatic © Whenthe Am95C76 ORP is used, it must reside in Font insertion of wait states by the FMW field of the MTR. Memory space. The ORP may be programmed or ac- During Dispatch, Font cycles may skip the upper ad- cessed by using Font Load and Font Read modes to the dress cycle and FALE2 if it does not needtobe updated. _locations reserved for it. ORP Loads and Dispatch op- This is done to improve performance. erations may be alternated so that rotated characters may be assembled into the page buffer as desired. Video Interface The timing for Video Memory cycles may be pro- creases the Row address hold time by one CLK to allow grammed by several ields inthe MTR register at Port7. for bank decoding if needed by the memory system. ‘The Video Memory Size (VMS) field selects the type of 14 video Write Wait State (VWW) bit and the Video Dynamic RAM that is used in the Video butter in order to ° i ‘nat ; Read Wait State (VRW) field allow wait states to be provide the correct combination of Row and Column ad ‘eal dresses and bank select bits, The Video Precharge Ex- automatically inserted to extend Video Memory cycles . a to match the performance of the Dynamic RAMs used. tension (VPX) bit increases the precharge time when . VRAS and VCAS are inactive by one CLK itneeded by ‘FoF details on wait states see the MTR register descrip- the RAMs. The Video Timing Extension (VTX) bit in- "and the Video Memory cycle timing diagrams. RESET The RESET pin must be activated by the system after A Software Reset operation may be executed by chang- power-up. This causes an internal operation that initial. __ing the Mode Control field to 000 from any other value. izes scratch registers that are used for calculation of __Thiswillterminate an operation in progress andinitialize 5 | memory addresses. In addition, the Mode Register is _intemnal scratch registers to begin a new Dispatch in cleared. All other user-accessible registers must be Band 0, and begin printing at the top of Video Memory property initialized before any RPC operations are space. Software Reset will not alter the setting of the started. The Video buffer must be cleared by programe VP, VRE or IE bits in the Mode/Status Register and dy- ming appropriate Dispatch operations. will al- namic memory Refresh will not be interrupted. ways terminate any operations in progress including Refresh of the Video Memory. a Am95C75 5-103

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature -65 to +150°C Commercial (C) Devices Ambient Operating Temperature — -55 to +125°C Ambient Temperature (Ty 0 to +70°C Maximum Ve Relative to Vue 0.310 47.0V ‘Supply Voltage (Vee) +4.75 10 45.25 V OC Voltage Applied to Any : ; . Operating ranges define those limits between which the func- Pin Relative to Vee 0.5 to Vec+0.3V of the ‘ guaranteed. ‘Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reli- 5-104 Am95C75

DC CHARACTERISTICS over operating ranges Parameter Parameter Symbol Descriptions Test Conditions Min. Max. Unit Ve Input LOW Voltage 03 » v Vu Input HIGH Voltage CLK Input only 2 v All other, +0) v Vou Output LOW Vottage 0 v Vou Output HIGH Voltage 2 v u Input Le: 0! £10 HA loz Output Les Mw <Voo 210 HA lee Power Suppiygpétrel 70 mA CAPACITANCE* Parameter Parameter Symbol__Descriptions______Test Conditions Min. Max, Unt Cu Input Capacitance 25 pF Co VO Pin Capacitance 25 pF Cour Output Pin Capacitance 25 pF * Parameters are not “Tested”. —_—— eee Am95C75 5-105

SWITCHING CHARACTERISTICS over operating ranges Parameter Parameter Parameter Number Symbol Description Min. Max. Unt 1 tox CLK Cycle Time 80 1000 ns 2 tw CLK HIGH Pulse Width 35 ns 3 tw CLK LOW Pulse Width 35 ns 4 tro CLK Edge to Output Valid Delay 45 ns 5 tro CLK Edge to Output Float Delay (Note 1) 55 ns CPU INTERFACE 6 te Ac~Ay Valid to RD or WA FE Setup 10 ns 7 th RO or WA RE to A.A; Valid Hold 10 ns 8 te CS Valid to RD or WR FE Setup 0 ns 9 ty RD or WR RE to CS RE Hold 10 ns 10 tro RD or WR FE to RDY Delay 40 ns 10a tro WA FE to DRORE Delay 40 ns 1 tro Data Out Valid to RDY RE Delay CLK HIGH -10 ns 12 te RDY RE to or WR RE Hold 25 ns 13 tw RD RE to Data Out Valid Hold 0 ns 14 to RD RE to Data Out Float Delay (Note 1) 55 ns 15 ts Data In Valid to WA RE Setup 20 ns 16 tw WA RE to Data In Valid Hold 20 ns 7 tw ‘WR LOW Width (Note 2) 60 ns 18 tw WR Recovery 1CLK+20 ns 19 tw RD Recovery 05 CLK FONT INTERFACE 20 tu FALE1 or FALE2 FE t Hold 10 ns 2 ts Data In Valid to Cl 10 ns 22 tw FRO RE to Data In 0 ns 23 tu FWR RE to Dat@put id 10 ns 23a tw FALE1 or F, jh CLK LOW-10 ns VIDEO INTERFACE 24 te Oy Vall to CLK RE Setup 20 ns 25 th VR Data In Valid Hold 0 ns PRINTER INTERFACE (Notes 3, 4) 26 teu VCLK Cycle Time (Synchronous Mode) 50 2000 ons 27 tw VCLK HIGH Pulse Width (Synchronous Mode) 20 ns 28 tw VCLK LOW Pulse Width (Synchronous Mode) 20 ns 29 teu VCLK Cycle Time (Asynchronous Mode) 31 2000 ons. 30 tw VCLK HIGH Pulse Width (Asynchronous Mode) 10 ns 31 tw VCLK LOW Pulse Width (Asynchronous Mode) 10 ns 32 tw PSYNC Pulse Width 1 VeLK 33 to PSYNC RE to LSYNC RE Delay 50 ns 34 tw LSYNC Pulse Width 1 VCLK 35 te LSYNC RE to VCLK RE Setup (Synchronous Mode) 15 ns 36 to VCLK RE to VDO Valid Delay (Synchronous Mode) 40 ns 37 to VCLK Edge to VDO Valid Delay (Asynchronous Mode) 1.5 VCLK + 45, ns Notes: 1) Parameter #5 and #14-Float times indicate that the RPC is no longer driving bus outputs and are measured by determining when outputs that were driven LOW have risen above a level of 0.8 V. 5-106 ‘Am95C75

2) Parameter #17-WA Width (LOW)-applies only when RDY does not go LOW. When the RPC is not ready to accept a write, specs #10 and #12 will apply and determine the necessary write width. Notes (continued): 3) PSYNC will not be recognized immediately after the Raster Scan Control bit (RC) is set by the CPU. Two words must be prefetched from the Video Memory before printing of a new page can begin. This requires two Read-Modify-Write cycles plus completion of any memory cycle in progress (approximately 25 CLKs minimum). A PSYNC that occurs before the data for VDO is ready will be ignored. 4) LSYNC for anew line cannot occur immediately after the last pixel of the previous line has been clocked out by VCLK. Atleast 10 VCLKs must occur between the last valid pixel on VDO and tha next LSYNC in order for the X Margin and X Size values to be processed correctly. Output-to-Output Timing Relationships Parameter #4 CLK Edge to Output Valid Delay-can be used for all clocked outputs as indicated in the timing diagrams. All ‘outputs are clocked in the same manner and the delay for any two unrelated outputs will track within 10 ns. Out- put-to-output relationships can be determined by the number of fullor half CLKs between them according to the formula: TD = (n CLKs x Cycle Timo)-10 ns. oe Am95C75 5-107

<+— CLK iS) smn Clock Cycle Timing Ao AoE regteraacress a ee —~ cs = ok Lo © a 2) RDY ye ; ©) INTR__ 22.2... cwast-cotan CPU Read Access Timing 5-108 Am95C75,

a SWITCHING WAVEFORMS (continued) CLK AoAg ES Ceaistraciross OK On a cae? — cs +O ko | wr —_ @ f ir I, 9 ° RDY @ ©) (8) Ps et smovoos CPU Write Access Timing mere ccnse ming TO T1 T2 T2orTW T3 5 | ox oftsy g sac FALE2 @ ! FALEt ea] ha Pek o FAD = ¥ | |__ FAD. © @ © FADS, ho (({ oxen (0) © orst01k Font Memory Read Access Timing ee Ramimomery Res scess iming Am95C75 5-109

SWITCHING WAVEFORMS (continued) To " 12 Tw 13 1 CLK FALE2 = pe — © ) Fab I na ay yl te FAD 9— FA, FA, _— Hy FD5- FD. K FADS LFA FAzs| HPAP Mo FOorFOs oaaow eel KI @ 1) 10) novos Font Memory Write Access Timing TOsTx i TasTrw 13 P cLK rm Le | VAD = VAD eee VEAS cnoat-co1sa Video I/F Read Access Timing 5-110 Am95C75

SWITCHING WAVEFORMS (continued) T0+Tx mal T2 T3+Tww TP CLK Say | fay 2 | VADg- VAD a [Serer [Sour 4 [oats | —o | 2 Veas On" (0) VR — eee Video UF Write Access Timing TO+Tx 1 T2+Trw 3 14 T5+Tww TP al al tel eh oar” Ko VWE © 0) VA Video VF Read-Modify-Write Access Timing i ir intel Am95C75 S111

SWITCHING WAVEFORMS (continued) To 1 T2 73 ™ TP or TO CuK \\ a Oe VRAS = | to VCAS VWE VR —__ © 10) VAFE onsa1-o010 Video VF Retresh Timing SSS To ™ 1 T2 CLK ae i E Ht VRAS. wes ~~ (9003-00204 Video Extension Timing 5-112 Am95C75

SWITCHING WAVEFORMS (continued) VeLK © ST UM A @ voo . R}+- >Re} G5) LBP Timing (SYNC Mode) <- @s) VCLK © im ® | @ ELH LSYNC i<fy ® S) Sl © 5 | vo tj © (00091-00224 LBP Timing (ASYNC Mode) YENI VI NIN INI NVI NS \\+—G2)—> PSYNC Sb 3) @)->} LSYNC PSYNC Timing Am95C75 5-113

| ‘ou From Output Under Test Vy I 100 pF vy; = Vout You 09331-00244 SWITCHING TEST WAVEFORM (Input) 24V 20V 20V test Points < 04s V O.8V ogy 10487-030A 5-114 Am95C75