AM9519A-1PC

AM9519A AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Universal Interrupt Controller FINAL DISTINCTIVE CHARACTERISTICS © Eight individually maskable interrupt inputs reduce CPU. ® ~Common vector and polled mode options overhead ® Automatic hardware clear of in-service interrupts re- © Unlimited interrupt channel expansion with no extra duces software overhead hardware © Polarity contro! of interrupt inputs and outputs © Programmable 1-byte to 4-byte response provides vec- @ Reset minimizes software initialization by automatically tor address and message protocol for 8-bit CPUs generating CALL to location zero © Rotating and fixed priority resolution logic SMD/DESC qualified © Software interrupt request capability GENERAL DESCRIPTION The Am9519A Universal Interrupt Controller is a processor range of digital systems, including most popular 8-bit support circuit that provides a powerful interrupt structure to microprocessors. Since the response bytes are fully pro- increase the efficiency and versatility of microcomputer- _grammable, any instruction or vectoning protocol appropri- based systems. A single Am9519A manages up to eight _ate for the host processor may be used. maskable interrupt request inputs, resolves priorities and supplies up to four bytes of fully programmable response = When the Am9519A controller receives an unmasked for each interrupt. It uses a simple expansion structure that interrupt request, it issues a Group Interrupt output to the allows many units to be cascaded for control of large CPU. When the interrupt is acknowledged, the controller numbers of interrupts. Several programmable control —_gutputs the one-to-four byte response associated with the features are provided to enhance system flexibility and highest priority unmasked interrupt request. The ability of optimization. the CPU to set interrupt requests under software control The Universal Interrupt Controller is designed with a Permits hardware prioritization of software tasks and aids general purpose interface to facilitate its use with a wide S¥Stem diagnostic and maintenance procedures. BLOCK DIAGRAM woo ete “ o “er *O o axe RESPONSE a | tus MEMORY “ conTROL az, mm " ame A acn mrennury a “neonsten necrsren bald OF nreanuer CONTROL e Pai0RITY £0 CONTROL aN (an ye) s KTERRUS Reavers. aeosren omnt BD003280 Publication # Rev. Amendment 00147 oD 10 2-212 Am9519A issue Date 1989 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

; Pipi foro | m—e]2 »j-—e ° "0 = “Th mR ose [ ]5 25 [ | wear on ==] « = [-— incor

006 Cs co a meas cas L] 6 24 [| Recs

“ Cy bd me O84 C 7 23 [ | (REQS 0B C7 2 IREOe es cle af mea, oss [Ja 22 [ ] eos ov ==] > 20 [+ near ose []° af] recs oe! <=] 0 9 [= mmeot os =f] te —— ineoo os: [ J 10 207] ece ie mn a: ont ao [] 11 19] | wear " cy “Ee 0 2 13 4 1% 6 7 4B (ono) vss ——{] 14 er Coo cD005101 a o 3 & re oe z z cpo107e3 Note: Pin 1 is marked for orientation. 2 | Lec (Military only) geeews 2 88h e | HUM UH nelgre Ft Te BRU OY, nc Os set) ne 67 bas aX near

08 F510 set iReO6

ves S11 ast) eos oe S12 mcd neoe oe 3 st! ineas vse Sate sce mec oo Fis ae inear

090 S16 20) inece

ie 19 20 21 2 29 24 25 28 27 78 ARARARARARAARR SEeBe SHEE Be ge =e z22 CD010880 Am9519A 2-213 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) . Package Type d. Temperature Range . Optional Processing AM9519A, at aD & B Le, OPTIONAL PROCESSING Blank = Standard processing B = Burn-in d. TEMPERATURE RANGE" C= Commercial (0 to +70°C) 1 = industrial (-40 to +85°C) ¢. PACKAGE TYPE P = 28-Pin Plastic DIP (PD 026) D = 28-Pin Ceramic DIP (CD 028) J = 26-Pin Plastic Leaded Chip Carrier (PL 028) b. SPEED OPTION -1= Faster Response Time (see Switching Characteristics) a. DEVICE NUMBER/DESCRIPTION Am9519A, Universal Interrupt Controtler Valid Combinations Valid Combinations Valid Combinations list configurations planned to be ‘AM9519A, PC, DC, DCB, DIB, JC ‘supported in volume for this device. Consult the local AMD _——. ~ - sales office to confirm availability of specific valid AM9519A-1 PC, DC, DCB, JC combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade *This device is also available in Military temperature range. products. 2-214 Am9519A www.chipdocs.com Be sure to visit ChipDocs web site for more information.

ORDERING INFORMATION (continued) Standard Military Drawing (SMD)/DESC Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Miltary Drawing (SMD)/DESC products are fully compliant with MIL-STO-883C requirements. The order number (Valid Combination) for SMD/DESC products is formed by a combination of: a. Military Drawing Part Number b. Device Type ©. Case Outline d. Lead Finish 6962-87597 oo x x { d. LEAD FINISH X= Any Lead Finish Acceptable ©. CASE OUTLINE X = 28-Pin Ceramic DIP (CD 028) Y = 44-Pin Ceramic Leadiess Chip Carrier (CL 044) b. MILITARY DEVICE TYPE 01 = 2 MHz (9519A) a. MILITARY DRAWING NO./DESCRIPTION 5962-87597 Universal Interrupt Controller Valid Combinations [Vala Combinations] Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device, Consult the local AMD 5962-8759701 XX, YX sales office to confirm availability of specific valid combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups Am9519A 2-215 www.chipdocs.com _Be sure to visit ChipDocs web site for more information.

ORDERING INFORMATION (continued) APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-B83C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) ©. Device Class d. Package Type @. Lead Finish AM9519A Bx A |, LEAD FINISH A= Hot Solder Dip d. PACKAGE TYPE X= 26-Pin Ceramic DIP (CD 028) U = 44-Pin Leadiess Chip Carrier (CL 044) ¢. DEVICE CLASS /B = Class B b. SPEED OPTION Not Applicable a. DEVICE NUMBER/DESCRIPTION Am9519A Universal Interrupt Controller Valid Combinations [Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the focal AMD sales office to confirm availability of specific valid combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups 2-216 Am9519A www.chipdocs.com Be sure to visit ChipDocs web site for more information.

[rim no. [name | 0 [Description [ze voc TTS Volt Power Supt 14 DB0-DB7 vo (Data Bus). The eight bidirectional data bus signals are used to transter information between the ‘Am9519A and the system data bus. The direction of transfer is controlled by the [ACK, WR and FD input signals. Programming and contro) information are written into the device: status and response data are output by it. (Chip Select). The active low Chip Select input enables read and _write operations on the data bus. Interrupt acknowledge responses are not conditioned by CS. (Read). The active low Read signal is conditioned by TS and indicates that information is to be transferred from the Am9519A to the data bus. WR (Write), The active low Write signal is conditioned by CS and indicates that data bus information is to be transterred trom the data bus to a location within the Am9519A, Pa oD (Control/Data). The C/5 control signal selects source and destination locations for data bus read and write operations. Data read or write transfers are made to or from preselected internal registers or memory locations. Contro! write operations load the command register and control ead operations output the status register. 18-25 TREQO-IREQ? (interrupt Request). The Interrupt Request signals are used by external devices to indicate that service by the host CPU is desired. REC inputs are accepted asynchronously and they may be programmed for either a HIGH-to-LOW or LOW-to-HIGH edge transition. Active inputs are latched internally in the Interrupt Request Register. After the IRR bit is cleared, an IREQ {transition of the programmed polarity must occur to initiate another request. 7) (Response In Process). Response In Process 's a bidirectional signal used when two or more Am9519A circuits are cascaded. It pormits multibyte response transfers to be completed without interference trom higher priority interrupts. An Am9519A that is responding to an acknowledged interrupt will treat FP as an output and hold it LOW until the acknowledge response is finished. ‘An Am9519A without _an acknowledged interrupt will treat FIP as an input and will ignore [ACK pulses as long as RIP is LOW. The AlP output is open drain and requires an external pull-up resistor to VCC. Tack (interrupt Acknowledge), The active-low Interrupt Acknowledge line indicates that the external ‘system is asking for interrupt response information. Depending on the programmed state of the Am9519A, it will accept 1, 2, 3 or 4 TACK pulses; one response byte is transferred per pulse. The first IACK pulse causes selection of the highest priority unmasked pending interrupt request and generates a RIP output signal 15 (Pause). The active-low Pause signal is used to coordinate interrupt responses with dala bus and control timing. Pause goes LOW when the first ACK is received and remains LOW until FIP goes LOW. The external system can use Pause to streich the acknowledge cycle and allow the control timing to automatically adjust to the actual priority resolution delays in the interrupt ‘system. Second, third and fourth response bytes do not cause Pause to go LOW. Pause is an ‘open drain output and requires an external pull-up resistor to VCC. 16 £0 (Enable Out). The active-high EO signal is used to implement daisy-chained cascading of several {Am@519A cxcuits. EO is connected to the El input of the next lower priority chip. On recerpt of ant interrupt acknowledge, each EO will go inactive until it has been determined that no valid interrupt request is panding on that chip. If an active request is present, EO remains LOW. EO is ‘also held LOW when the master mask bit is active, thus disabling all lower priority chips. 13 (Enable in). The active-tigh El signal is used to implement daisy-chained cascading of several |Am9519A circuits, E) is connected to EO of the next higher prionty chip. It may also be used as a hardware disable input for the jnterreptsyster ‘When El is LOW, K inputs will not affect ISR; however, PAUSE will go LOW until HIP goes LOW. E! is internally pulled up to VCC so that no external pull-up is needed when El is not used. 7 GINT (Group Interrupt). The Group Interrupt output signal indicates that at least one unmasked interrupt request is pending. It may be programmed for active-high or active-low polarity. When lactive-low, the output is open drain and requires an external pull-up resistor to VCC. Since a glitch on GINT occurs approximately 100nsec after the last IACK pulse, this pin should not be connected to edge sensitive devices. PRODUCT OVERVIEW ISR bit must be cleared by the CPU under program control - when it is desired to permit interrupts from lower priority Register Description devices. When the interrupt is programmed for automatic Interrupt Request Register (IRR): The 8-bit IRR is used to _—_—“"2aring, the ISR a is automaticaly reset gunna ine acknowl store pending interrupt requests. A bit in the IRR is set &49® Sequence. All ISR bits are cleared by a reset function. henever the corresponding IREQ input goes active. Bits may tse be set under oar cont ‘oom ae epU. tna, Interrupt Mask Register (IMR): The 8-bit IMR is used to permitting software generated interrupts. IRR bits may be enable od ea REO toe and al ight mi 7 oe londed, cleared under program control. An IRR bit is automatically SoTespand’ fo the IED pul, Ane Gl oy in addition, cleared when its interrupt is acknowledged. All IRR bits are -S°t_ "Cleared in parallel under progr : 4 Cleared by a reset function, individual IMR bits may be set or cleared by the CPU. Care ~ must be taken therefore when disabling a specific channel by Interrupt Service Register (ISR): The 8-bit ISR contains one _setting its IMR bit. If that bit is causing the GINT pin to be bit for each IREQ input. It is used to indicate that a pending —_active, a lock-up condition can occur if the CPU recognizes the interrupt has been acknowledged and to mask all lower priority —_interrupt and then the Am9519A removes the request. During interrupts. When a bit is set by the acknowledge logic in the the TACK cycle, PAUSE will go LOW and stay LOW. The ISR, the corresponding IRA bit is cleared. If an acknowledged —_— solution is to disable CPU interrupts prior to writing to the IMR interrupt is not programmed to be automatically cleared, its and then re-enable them. A reset function will set all eight Am9519A 2-217 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Response Memory: An 6 x 32 read/write response memory _—S#ected (C/D = 1). hardware by the rising edge of the last acknowledge pulse. A contro! location selected (C/D = 1), as shown in Figure 3. status register read operation. It is recommended to read the —count is satisfied.

1 Chip armed 0 Interrupt

4 Poti © Active tow

0 Fixes

0 Chip disabled

1 Chip ensbled 00 laterrupt service register

Figure 1. Status Register Bit Assignments Figure 2. Mode Register Bit Assignments www.chipdocs.com Be sure to visit ChipDocs web site for more information.

‘options and operating modes that permit the design of For reading, the Status register is selected directly by the C/D sophisticated interrupt systems. control input. Other internal registers are read by preselecting Reset the desired register with mode bits 5 and 6, and then executing a data read. The response memory can be read ony The reset function is accomplished by software command or with TACK pulses. For writing, the Command register is automatically during power-up. The reset command may be _selected directly by the C/D control input. The Mask and Auto issued by the CPU af any time. Internal power-up circuitry is Clear registers are loaded following specific commands to that triggered when VCC reaches a predetermined threshold, effect. To load each level of the response memory, the causing a brief internal reset pulse. in both cases, the resulting response preselect command is issued to select the desired internal state of the machine is that all registers are cleared level. An appropriate number of data write operations are then except the Mask register which is set. Thus, no Group executed to load that level. Interrupt will be generated, and no interrupt requests will be recognized, The response memory and Byte Count registers are not affected by reset. Their contents after power-up are [rack | unpredictable and must be established by the host CPU during C3 | c/b | Fo | wr] DATA BUS OPERATION initialization. Transfer contents of prese- SEP caer | Operating Sequence bus Transter contents of data bus A twit description of a typical sequence of events in an [| 2 | + | o | + [rspmeceaamt ct can | operating interrupt system will illustrate the general interac- Transfer contents of status ce rine now CPU, ho miempt comroner anoime «| ° | + | ot | lemercams | “ee eT | Basra ‘to command register 1, The Am9519A controller is initialized by the CPU to custom- Tancior contents ot 3slesied ize its configuration and operation for the application at bef fe | oper Sor | hand. Both the controller and the CPU are then enabled to data bus accept interrupts, LPT TT Jie intormation transferred | 2.One (or more) of the interrupt request inputs to the controller becomes active indicating that peripheral equip- Figure 3. Summary of Data Bus Transfers ment is asking for service. The controller asynchronously accepts and latches the request(s). The Pause output may be used by the host CPU to ensure that propertiming relationships are maintained with the Am9519A 3. If the request is masked, no further action takes place. Ifthe when IACK is active. The IACK pulse width required depends request is not masked, a Group Interrupt output is generat- —_on several variables, including: operating temperature, internal ed by the controller. logic delays, number of interrupt controllers chained together, 4. The GINT signal is recognized by the CPU which normally and the priority tevel of the interrupt being acknowledged. will complete the execution of the current instruction, insert When delays in these variables combine to delay selection of an interrupt acknowledge sequence into its instruction __@ fequest following the falling edge of the first |ACK, the Pause execution stream, and disable its internal interrupt structure Output may be used to extend the TACK pulse, if necessary. The controller expects to receive one or more CR signals Pause will remain LOW until a request has been selected, as from the CPU during the acknowledge sequence. indicated by the falling edge of RiP. Typically, the internal interrupt selection process is quite fast, especially for systems 5.When the controller receives the TACK signal, it brings with a single Am9519A, and Pause will consequently remain PRUSE tow and selects the highest priority unmasked LOW for only a very brief interval and will not cause extension pending request. When selection is complete, the RiP of the TACK timing. output is brought low and the first byte in the response fi . memory associated with the selected request is output on Operating Options the data bus. PAUSE stays low until RIP goes low. RIP stays The Mode register specifies the various combinations of low until the last byte of the response has been transferred. gperating options that may be selected by the CPU. It is 6. During the acknowledge sequence, the IRR bit correspond. cleared by power-up or by a reset command. Mode bit 0 ing to the selected request is automatically cleared, and the specifies the rotating/fixed priority mode (see Figure 2). In the corresponding ISR bit is set by the falling edge of TACK. _ fixed mode, priority is assigned to the request inputs based When the ISR bit is set, the Group Interrupt output is upon their physical location at the chip interface, with |REQO disabled until a higher priority request arrives or the ISR bit the highest and IREQ7 the lowest. In the rotating mode, is cleared. The ISR bit will be cleared by either hardware or _‘‘@lalive priority is the same as for the fixed mode and the most software. recently serviced request is assigned the lowest priority. In the fixed mode, a lower priority request might never receive 7. if a higher priority request arrives while the current request _service if enough higher priority requests are active. In the is being serviced, GINT will be output by the controller, but rotating mode, any request will receive service within a will be recognized and acknowledged only if the CPU has its maximum of seven other service cycles no matter what interrupt input enabled. If acknowledged, the corresponding —_—pattern the request inputs follow. higher priority ISR bit will be set and the requests nested, 44 wt 4 selects the individual/common vector option. Information Transfers Individual vectoring provides a unique location in the response Figure 3 shows the control signal configurations for all TATU for each ere request. The soon aeOo ne information transfer operations between the Am9519A andthe “WAYS poles 'e response associal ro data bus. The following conventions are assumed: AD and —‘Tatter_ which request is being acknowledged: WA active are mutually exclusive; RD, WR and C/D have no Mode bit 2 specifies interrupt or polled operation. in the polled meaning unless CS is LOW; active [ACK pulses occur only mode, the Group Interrupt output is disabled. The CPU may when CS is HIGH. read the Status register to determine if a request is pending, Am9519A 2-219 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Since TACK pulses are not normally supplied in polled mode, least one of the IMR bits should be enabled. If vectoring is to the IRR bit is not automatically cleared, but may be cleared by be used, the response memory must be loaded; if not, the command. With no TACK input, the ISR and the response © mode must be changed to a non-vectored configuration. memory are not used. An Am9519A in the polled mode has EI Normally, the first step will be to modify the Mode register and connected to EO so that in multichip interrupt systems the _the Auto clear register to establish the configuration desired polled chip is functionally removed from the priority hierarchy, _for the application. Then the response memory and byte count , , will be loaded for those request levels that will be in use. The Mode bit 3 specifies the sense of the GINT output When rassonse memory for every channel must be written even if active high polarity is selected, the output is a two-state the channel is not used. Every byte need not be written, configuration. For active low polarity, the output is open drain those every only , s : specified by the byte count. Finally, the master mask bit and requires an external pultup resistor to provide the high ang at least portions of the IMA will be enabled to allow logic level. The open drain output allows wired-or contigura- tions with other similar output signals. interrupt processing to proceed. Mode bit 4 specifies the sense of the IREQ inputs. When Commands active low polarity is selected, the IRA responds to falling The host CPU configures, changes and inspects the internal edges on the request inputs. When active high is selected, the condition of the ane 9A using the set of commands shown IRR responds to rising edges. in Figure 4. An "X" entry in the table indicates a "don't care" Mode bits 5 and 6 specify the register that will read on __ state. All commands are entered by directly loading the subsequent data read operations (C/D = 0, AD = 0). This Command register as shown in Figure 3 (C/D = 1, WR = 0). preselection remains valid until changed by a reset or a Figure 5 shows the coding assignments for the Byte Count command. registers. (A detailed description of each command is con- Mode bit 7 is the master mask bit that disables all request “#704 in the Am95194 Application Note AMPUB-071.) inputs. It is used to disable all interrupts without modifying the IMR so that the previous IMR contents are valid when interrupts are re-enabled. When the master mask bit is LOW, it | svi | sro | cour | causes the EO line to remain disabled (LOW). Thus, for muliple-cip interrupt systems, one master mask bit can a ee disable the whole interrupt structure. Alternatively, portions of ee ee the structure may be disabled. The state of the master mask bit is available as bit S3 of the Status register. ; 1 | o | 3 | Programming a ee After reset, the Am9519A must be initialized by the CPU to perform useful work. At a minimum, the master mask bit and at Figure 5. Byte Count Coding per tet s fs fs [2 [is | 6 |commano cescrprion A [oo foo Po Pe foo Tx Tx Tx Jotear at RA and an iA pits [oo fo Po a a [be 8tT 80 [clear AR and IMA bit spocified by 82, 81,80 | po Poo oT Tetear at Rts poo fo fs To [i | s2 Tbr | 80 [clear IMA bit specitied by G2 61,80 po fo Tet aw bts poo foo Poa Ta [a [2 [61 [80 [set IMA bit specitied by 82.81.80 poo Toe fo Po Po Px x [x [oleae at ae bits poo fot fo fo ft [ee [at] 80 [clear ini ‘bit speciied by 82.81.80 poo fi foe Pa Po Tx [x 7 x [seta ina pits poo fo Pe Tea Tar [80 [Set 1A bit specttod by 82, 81,80 poo fo ft Po Te Tetear highest priority ISR bit poo Pap Po Po Pe PT x Tetear att 8 bits poo fs Pa Tee Tat [60 tear ish bit species by 62,8180 pos fo fT oT mae Twa [m2 [Mi | Mo [Load Mode register bits 0-4 with specited pattern | pot fo Po Te Ts [0 [0 [toad Mode rogistor bits 5,6 with specified pattern | [oi fo Pos [oT we Tus [0 [1 [toad Mode register bits 6. 6 and set mode bit? | f+ fo fos To [we [ws [1 [0 [toad Mode register bits 5, 6 and cloar mode bt 7 [os To TTT PPreselected IMR for subsequent loading from data bus | [oi [1 foo To [x [x Tx] x [Preselected Auio Ciear register for subsequent loading from data bus | Pos fe is Pov Pave Pie [es | to Jina earths as Sons nas | level specified by L2, L1, LO for subsequent loading from data bus 2-220 Am9519A www.chipdocs.com Be sure to visit ChipDocs web site for more information.

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES ° 5 Commercial (C) Devices All Signal Voltages ‘ Supply Voltage (VCO) essere 5 Vt 10% Stresses above those listed under ABSOLUTE MAXIMUM Military (M) Devices RATINGS may cause permanent device failure. Functionality Temperature (To)... @55 tO + 125°C at or above these limits is not implied. Exposure to absolute Supply Voltage (VCC) ..2---ceesscrcsesseneee SV # 10% maximum ratings for extended periods may affect device Wing ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified (for APL and SMD/DESC Products; Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) | Parameters | __ Description | Test Conditions [Min [Mex [units | [_10H=-200u4 eae “ Ouest ah votage (wer ® | 1oH==1004A 2 omy) ae [ tov=s2mq oe [vik mput High Vottage oT voor vot [vit TT input Low Vottago 0 08 vote] 1% \\nput Load Current vescvin<vec Peimew _ f -e0 [7 io [Other inputs | -10 [10 eo ee |_ Commercial te 'ec Xx Supply Current | ingustriah 85m [Miltary 200 [co | Output Capacitance | t= 10 aH re | Ta= 28°C re All pins at OV re “Guaranteed by design — not tested SWITCHING TEST CIRCUIT tou Q is x t i 4 is + qe Q 70004200 This test circuit is the dynamic load of a Teradyne J941. 2-222 Am9519A www.chipdocs.com Be sure to visit ChipDocs web site for more information.

SWITCHING TEST INPUT/OUTPUT WAVEFORM as 0.8 = POINTS ~~ 08 WF007820 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Notes 1, 2) femal ommpen fafa | | [tant [oS vaw od lowe Raton SSCS rd [avn —| 675 vate ana C8 LOW we Wite tows od [totpH [FIP LOW to PAUSE HIGH oie) —SSSSSSCSSd es |_| [Tetav [FF Low to Data On vais Woe SSCS RG [“Tenct [Enable in HIGH to AP LOW Weis) ———SSSCSCSCSC~sC a wos [ev —Tinterast Request Vato Grow inienost vata | 100 | eo J} 60s pe te (REQ Pulse Duration) [eH | ACK HIGH Io FP GH Wee | os [rec [ACR HIGH to HER LOW (ROK Reco Sd | [etiwt “ TROK HIGH EO HIGH Wows Cid ms [“Tenex | TROR HIGH to ata Gut vad me [cima [TACK Lowe RP cow Wows 5 SSCSCS~C~SC Yas [atk TREK Low to TACK HIGH (ret RO) Wore) ids oe 2 | [Taine | AER LOW to £0 LOW oles G7.) SS oe [Tet | RGR LOW Te PAUSE LOW aes) Se es [retav [THER LOW to Date Out vas oles |] S~dYCs | ao esa0 os [“Tecavi | tat HOR COW to Date Gut Vas owe oy see a a [ aHox | Rees HGH fo Osta Outing SSS [“yatov —[ Rea tow Osa On vans aoe [Triax | Reed LOW t Baia Out Urine SSCs | | “taunt | Read Low to Read HIGH (AD Pulse Dwabo) Ss] moots [Twaax | Wite HIGH © Cand CB Dont Care SS | [twHox—[ wite HIGH © Osan DontcweSSSC~d ws [Twin wirte AIGH To Rea or Wile LOW (ite Recover] [soo || wo [|__| [Twi] Wire LOW to Wee HIGH (HF Puse Owaton «dao td of [Teun [ACK HIGH to GNT mace oc 00s Notes: 1. Transition abbreviations used for the switching parameter symbols include: H = HIGH, L = LOW, V = Valid, X= unknown or don't care, Z = high-impedance. 2, Signal abbreviations used for the switching parameter symbols include: R = Read, W = Write, Q = Data Out, D = Data In, A= Address {CS and C/D), K = Interrupt Acknowledge, N= Enable Out, E = Enable In, P = Pause, C= RIP. 4, TKLOV appiies only to second, third and fourth JACK pulses while FIP is LOW. During the first [ACK pulse, Data Out will be valid following the falling edge of AIP (TCLOV) 5. RIP is pulled LOW to indicate that an interrupt request has been selected. AIP cannot be pulled LOW until El is HIGH following an internal delay. TKLCL will govern the falling edge of RIP when El is always HIGH or is HIGH early in the acknowledge cycle. The TEHCL will govern when El goes HIGH later in the cycle. The rising edge of El will be determined by the length of the preceding iority resolution chain. iid remains LOW until after the rising edge of the [ACK pulse that transfers the last response byte for the selected (REQ. 6. Tost conditions for the EO line assume an output loading of OL = 1.0 mA and [OH = -100 uA. Since EO normally only drives El of another Am9519A, higher speed operations can be specified with this more realistic test condition. 7. The arrival of IACK will cause EO to go LOW, disabling additional circuits that may be connected to EO. If no valid iraatrupt is ponding, EO will return HIGH when El is HIGH. lf @ pending request is selected, EO will stay LOW until after the last pulse for that interrupt is complete and RIP goes HIGH. 8. VOH specifications do not apply to RiP, PAUSE, or to GINT when active-low. These outputs are open drain, and VOH levels will be determined by external circuitry 9. TS must be HIGH for at least 100ns prior to IACK going LOW. Am9519A, 2-223 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

SWITCHING CHARACTERISTICS over MILITARY operating ranges (for SMD/DESC and APL Products, Group A, Subgroups 9, 10, +1 are tested untess otherwise noted). (Notes 1, 2) - Symbol Description | win | wax_| [1 [rane [CS veld ond SLOW Rees tow SSCS i TAVWL C/D Valid and TS LOW to Write LOW es ee | __3 | TcLPH | AIP LOW to PAUSE HIGH (Note 5) ee ee [ «| ret [FIP Low to Gata Out vas owe Qe [2s Prove oat vase Wate HGH a8] [5 [rence | erabie n niGH to RIF Low Woe) 00 | ae J | 7 [vey [inert oqust Vai 1 Group ieragt Vaid) 100 | ane Fr (IREQ Pulse Duration) THAGHfIAGK HIGH fo AP HGH aie) Sd ee ed Vr VV [resist [AR GH Te FO HIGH Wows SCS [12 [nox [TRE HIGH Bata Out vans Sd ae ee ee VV [ie [tee | RGR LOW to ROR HIGH ist AD WET [15 [ 9INE | RER LOW 9 £0 LOW Woes 679i [16 | "TKLBL—[iAGK LOW te PAUSE LOW (ote) as [17 [rcv] TAR LOW to Date Cut vale oles Sa 1 | THLOV | tot PRE LOW to Data Out Vai Wate 9) Ys a] re | 9 [TM PASE WGH® ROCHA oe “BH — Rot 0 a 8 Dar cae} 3} ai [TRHOK | eas HIGH 10 Dera Out mand S| fe ee oe [21 | Tauri | Read LOW To end FIGH Pulse Buaion) iY a [| Twinn [Wie WH w G/B and CS Dont care oe [a5 two | Wite HIGH te Baten Dont Gwe as fe TWH | Weta HIGH to Read of Wie LOW (Wile Resven) Jeo id i [29 fF TkHi | TACCHIGH to GINT Inactive ee | Notes: 1. Transition abbreviations used for the switching parameter symbols include: H = HIGH, L = LOW, V = Valid, X = unknown or don't care, j Z = high-impedance. \\ 2, Signal abbreviations used for the switching parameter symbols include: R= Read. W ~ Write, Q = Data Out, D= Data In, A= Address | (ES and C/B), K = Interrupt Acknowledge, N= Enable Out, E = Enable In, P = Pause, C= RIP. i 9. Dunn the fra TACK pulse, PAUSE will be LOW long enough to allow for priority resolution and will not go HIGH until after RIP goes 4, TKLOV applies only to second, third and fourth TACK pulses while RIP is LOW. During the first TACK pulse, Data Out will be valid following the falling edge of RIP (TCLQV). 5. RIP is pulled LOW to indicate that an interrupt request _has been selected. FIP cannot be pulled LOW until El is HIGH following an internal delay. TKLCL will govern the falling edge of RIP when El is always HIGH or is HIGH early in the acknowledge cycle. The TEHCL will govern when El goes HIGH laler in the cycle. The rising edge of El will be determined by the length of the preceding phorty resolution chain iP remains LOW until after the rising edge of the TACK pulse that transters the last response byte for the selected IREQ. 6 Test conditions for the EO line assume an output loading of !OL = 1.0 mA and IOH=-100 uA. Since EO normally only drives El of anothor Am9519A, higher speed operations can be specified with this more realistic test condition, | 7. The arrival of [ACK will cause EO to go LOW, disabling additional circuits that may be connected to EO. if no valid lnterrunt is pending, EO will return HIGH when El is HIGH. If a pending request ss selected, EO will stay LOW until after the last [ACK pulse for i that interrupt is complete and RIP goes HIGH. { 8. VoH specifications do not apply to FIP, PAUSE, or to GINT when active-LOW. These outputs are open drain, and Voy levels will be | determined by external circutry 9. CS must be HIGH for at least 100 ns prior to [ACK going LOW. OS 2-224 Am9519A www.chipdocs.com Be sure to visit ChipDocs web site for more information.

“5 a= —_ wmeo _ — ivy toe owt x —t THHKL. m= On RR 1 e | a, | | | a 7 © / _ - Lome | | | map p- Tum | | j fe ee . 001 ny menos T ov menor t 7 WFO03551 Interrupt Operations TY Oy “SSISSSITRY \\ARKRR) = ON AD a | i 06000 OC * Ns etal! BYR, avn mux TaN ae Le rene oe ve | — rRov reW0K Xe ‘max 7 Tovwn WOK WG, CC EER eee ” a. raraiitatatele's errata’ WFO03560 Data Bus Transfers | Am9519A 2-225 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.