AM9513A AMD | Alldatasheet
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DISTINCTIVE CHARACTERISTICS © Five independent 16-bit counters ‘© Complex duty cycle outputs @ High speed counting rates © One-shot or continuous outputs © Up/down and binary/BCD counting © Programmable count/gate source selection © Internal oscillator frequency source © Programmable input and output polarities © Tapped frequency scaler © Programmable gating functions ‘© Programmable frequency output © Retriggering capability © 8-bit or 16-bit bus interface ‘© +5 volt power supply © Time-of-day option ® Standard 40-pin package © Alarm comparators on counters 1 and 2 @ SMD/DESC qualified GENERAL DESCRIPTION The Am9513A System Timing Controller is an LSI circuit The STC includes five general-purpose 16-bit counters. A designed to service many types of counting, sequencing variety of internal frequency sources and external pins may and timing applications. It provides the capability for pro- be selected as inputs for individual counters with software grammabie frequency synthesis, high resolution program- selectable active-high or active-low input polarity. Both mable duty cycle waveforms, retriggerabie digital one- hardware and software gating of each counter is available. ‘shots, time-of-day clocking, coincidence alarms, complex Three-state outputs for each counter provide pulses or Pulse generation, high resolution baud rate generation, —_levels and can be active-high or active-low. The counters frequency shift keying, stop-watching timing, event count —_can be programmed to count up or down in either binary or accumulation, waveform analysis, etc. A variety of program- BCD. The host processor may read an accumulated count mable operating modes and control features allows the at any time without disturbing the counting process. Any of Am9513A to be personalized for particular applications as the counters may be internally concatenated to form any well as dynamically reconfigured under program control. _ effective counter length up to 80 bits. BLOCK DIAGRAM SOURCE NS s cores Z . Ley. * 4 in 6 LOGIE GROUP =| a} Gs} LH counren 3 Locke oxour mn [ 2 | ee ” el (= et A og xc se ee Gece} on ° a] ~ Py vee ve 10000081 7 a a 2-116 ‘Am9513A taave Date: 1909
wswvec —cft ours 235e5885585 our <2 0 f-— aare? Beh eopossos ours J 3 [-— ours Gesisiiaaana) ares —=L]+ 7 [— ours wqf7 ° 90 Pi aares x —cfs 6 aares rour]s oe fl aves 2 35 gare nce 37 Bl sources ofan — i xB ites cq 10 36 fl souncez mc» 2 = sources wag 3 fl sounces ae 31 —— source s aye ‘& Bi sounces cn 20 = sounces fogs 53D) sounces 080 =] 12 1 sounces wo se ine pat a 2 ons eof] 1s 31 fl oes pea tu er perf] 16 sf os oss =O] 6 2» pers ae] 17 zo fi oes pennene— 25 — cerwaare sa 18 10 20 21 22 23 24 25 28 27 28 oes 7 26 oervaare ax socororeao oe Bo chews SSG8RS 25008 or 0 m2 F)—— oewaare 24 emt we =p-= omen ie ‘cpo0set2 co0ose12 Note: Pin 1 is marked for orientation. ORDERING INFORMATION | 2 Standard Products ‘AND standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) ¢. Package Type d. Temperature Range ©. Optional Processing Blank = Standard processing B= Burin 4. TEMPERATURE RANGE* C= Commercial (0 to +70°C)
1 Industral (-40 to +85°C)
©. PACKAGE TYPE P= 40-Pin Plastic DIP (PD 040) D= 40-Pin Ceramic DIP (CO 040) J = 44-Pin Plastic Leaded Chip Carior (PL 044) b. SPEED OPTION Not Applicable ‘4. DEVICE NUMBER/DESCRIPTION AmO519A ‘System Timing Controller Valid Combinations Valid Combinations list configurations planned to be supported in Valid Combinations volume for this device. Consult the local AMD sales office to [canestan Po, 00, 008 be] Confirm availabilty of specific valid combinations, to check on a5 3 ‘newly released combinations, and to obtain additional data on ‘This device is also available in Military temperature ‘AMD's standard miltary grade products. range. ‘Am9513A, 2417
ORDERING INFORMATION (continued) ‘Standard Military Drawing (SMD)/DESC Products ‘AMD products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Military Drawing (SMD)/DESC products are fully compliant with MIL-STD-B83C requirements. The order number (Valid Combination) for ‘SMD/DESC products is formed by a combination of: a, Military Drawing Part Number b, Device Type ¢, Case Outline d. Lead Finish Q x X-= Any Lead Finish Acceptable ‘©. CASE OUTLINE Q=40-Pin Ceramic DIP (CD 040) X= 44Pin Coramic LOC (CL 044) . MILITARY DEVICE TYPE O1=7 Metz (95184) ‘2, MILITARY DRAWING NO./DESCRIPTION 5962-85523 System Timing Controller Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid [_ssezassasoy Tox xx combinations or to check for newly released valid ‘combinations. Group A Tests Group A tests consist of Subgroups 2-118 Am9513A
ORDERING INFORMATION (continued) APL Products [AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (it applicable) ©. Device Class d. Package Type @. Lead Finish AMag19A iB A Ls = Hot Solder OP 4. PACKAGE TYPE Q'= 40-Pin Ceramic DIP (CD 040) 02 4ePin Cerame Loudiess Chip Carer (lousy €. DEVICE CLASS 78 = Gass 8 . SPEED OPTION Not Applicable 1. DEVICE NUMBER/DESCRIPTION Amost9k System Timing Controior Valid Combinations 2 | Valid Combinations list configurations planned to be [was conseos ——) gon Set Nalid Combinations sales office to confirm availability of specific valid [Tawesi3aq T1804, eua | combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 8, 10, 11. Am9513A, 2-119
Leino. [name [vo | oescrpton a 5 ES a (Crystal). X1 and X2 are the connections for an external crystal used to determine the frequency of the (rms cais, ihe cyeal pons pec reeresonan Kraul tease the Rane tater {aachve nome maybe tad meteed of ees Feroving tom on ocr eteeneysoue: Xs Irion open and Snell be ormasad a TTC tues ar © tevap seaee 7 (Fequerey Out, The FOUT ouput Seed Fam & 2 cootr a may be poqrarined Wo Gide We Fre ieee eae ron tucn Ne ae ee cess a ee caer ave Bs ih reed nema scales seeateheavonses FOUT ey Sealed onan nitions ra ender al ontnta iow eseneee peoel Conmalate Me eacee PORT Sree toes in the Master Mode register. After power-up, FOUT provides a frequency that is 1/16 that of the oscillator, at ae tran GATE GATS {Gato The Gas inputs ray be vedio contol re apuratan onda couriers by Storing whan Counting may proceed. The same Gate input may contro! up to three counters. Gate pins may also be Seiad coer surces forty othe sere an tore ROUT Sue Te acaveponety ork ‘selected Gate input is programmed at each counter. Gating function options allow level-sensitive gating or Sancta (oe ee Sean ses ae esas ee ne eee eee en eos Sedo eerie earies Al gana unesone mney sce be Saab. The seme Snes echoed iy a ees ipa whan he tec wih ar onaroa Pnt on har bas Bao eanebon Saat Cty oe CATE ea aes von Waneion teak Se ses {Souce) The Source puis prove elena! signals tal maybe counted by any ole comers. Ay See ae ney ve rona to any or Oke the umiers a he FUT aoe Tha nbs soy Tork Selon SRC rout rower auch cour ry dy cle waver lbs ace at Herrin coe werk eos hae pared of Be racine spoked soure wegen tore Fan” Setm er Seu on he $A rout slows so warn unas be unad oa OTS (Goutieh Each ate OUT tgrl creciy-anvnicnd wan « covespondh rehire Sepondiesniheceuter corngutsion ve OUT aga’ meybe's fuse ¢ suse move ora comsior ay Dee erm Gur puss eames re SaSeay Belpamreane: Tae aooek Same aeeee eG Loner nate a oad ene Sear at are ihe bene Tana Ta Papelera bp relicte cag ang elaloel pelo toe alee ty ‘normal output mode and provides a true OUT signal when the counter contents match the contents of an Kae cote DBO DBT] VO] (Osa Bus) To 1s aeocbonl Dia Busnes ae used or formation exSanges wit the how prosmanor Bee = Bev oer Sot cea don tne coven a ona anh OW serena ere tne next npaa hon WR ang CS are active and as outputs when AD and CS are active. When CS is inactive, these pins are paved a8 hgvanpedance sate tet powe'p or rev bm da wi be configs fr 8 wih and wl ue ct 080 rough O87 O80 Be aka gunn au bay ene st Sear t poston The aa bas aye oohneed Pees recast emer potion fre te atte oceania! i cormans ns he Bibarse BO ince ue nalane he PO OSS nae arb ige Maer Ph cetner tees conse oben WAN DON oe aa rine ane DENS Ha re pete Whar operaing inthe Gi dla bus envonment O88 - DB1S wil never be sven sve Dy the ‘Am9513A. 088 through 0812 may optionally be used as additional Gate inputs (see Figure 2). If unused, they should be held HIGH. When pulled LOW, a GATENA signal will sable the action of the corresponding ‘counter N gating. OB13 - DB15 should be held HIGH in 8-bit bus mode whenever CS and re Sate Save (Chip Select. The actve-ow Chip Select input enablos Road and Write operations on the data bus. When Sie Ses mesh be Boas ana tte Poets me gorse the to Cop Glee sal er poe opes oe tear povetonraea rest. Sap aes Sl See Da ae Srey mey nl reson insect cosaguasen. ne sotare rat caren mk Be eed hen ey rn (Read). The active-low Read signal is conditioned by Chip Select and indicates that internal information is. [She trtoad on ab Tn soon rb ancy ag org asseneg aC Port reads, by the contents of the Data Pointer register. WR and should be mutually exclusive. {(Wte). The active-low Write signal is conditioned by Chip Select and indicates that data bus information is {rbrstoas tn a cesar Sostaoy te srg ty pr Say ost nd, for Data Port wines, by the contents of the Deta Pointer register. WR and RD should be mutually cS (Control/Data). The Control/Data signal selects source and destination locations for Read and Write ‘Operations on the data bus. Control Write operations ioad the Command register and the Data Pointer. Lor Ren oparstons stp ie Sat ropa ata as and Soa Wee eanersconmancte wa all other internal registers. indirect addressing at the data port is contyolied internally by the Data Pointer mae 2-120 Am9513A
Cun select bla vat tion networks themselves are not overstressed. Figure 1. Interface Signal Summary circuit.
15 DB3 pB3 acme” IN i
16 DB4 DBs eam i NLL
20 BB GATE 1A ”
27 B14 (Vi) =
Figure 3. Input Circuitry Figure 2. Data Bus Assignments ‘specified with logic levels compatible with those of standard resistor is a modestly high value of more than 100kohms. enough to break down the oxides and destroy the transistor. _will suffice.
timing operations. It provides the capability for programmable . watching timing, event count accumulation, waveform analysis @aisters. and control features allow the Am9513A tobe personalizedfor is independently controlled by its Counter Mode register. variety of internal frequency sources and extemal pins may be ‘put and output polarities. ‘outputs for each counter provide either pulses or levels. The predefined value, thus controlling the etfective count period. up to 80 bits. complex output waveforms. the internal 16-bit information is multiplexed to the low order 60Hz or 100Hz input frequencies. ou on a fe input and a single gate pin to contro! more than one counter. locations: a Control port and a Data port. The Control port the same time, the count source for another. Figure 4. Counter Logic Groups 1 and 2 Figure 5. Counter Logic Groups 3, 4 and 5
Element Cycle Data port Transfers. Gaim a] free | FOR Ba Counter 1 Hold Rg. Counter 1 Mode Reg.
1 All codes are in hex 3
- Whan usod with an bit bus, only the two tow order hex . Counter 2 Mode Reg
Figure 8. Load Data Pointer Commands } initial Data Pointer value entered by command. . the three values 00, 01 and 10 starting with the value entered. allow the least and most significant bytes to be transtorred ‘eutomatically cause a new prefetch to ocour. before the Element or Group fields are incremented.
- Operating modes N, O, Q, Rand X allow the user to save
following this update, the new register data is transferred to @ reads will access the recently saved Hold register data. the read operation, its access time is transparent to the user.
Oort become transparent by filing the Load register with all zeros. For Counters 1 and 2, the OUT pin will reflect the comparator —_ some operating modes or by software commands at any time. ‘The Status register is normally accessed by reading the {°F the Counter Mode registers. contro! bits to individually enable/disable the comparators. ours oura. sour is truo, that is, until the next input causes the count to change. and active-low if the Output Control field is 101. Figure 10. Status Register Bit Assignments host CPU has both read and write access to all registers in the writing directly to the Master Mode register.
Figure 11. Master Mode Register Bit Assignments which causes their decades to tum over at the counts that FOUT divider following reset. Bits MM2 and MM3 control the Comparators associated with power-on or reset, the FOUT divider is set to divide-by-16. operating mode. One special case occurs when the Time-of- 77m? Stn . . ‘Alarm 1 and Counter 1. considered when using FOUT as a system clock source.
2126 Am9513A
source between Load and Hold registers.
- Mode X is avaiable for AmaS13A only.
Figure 14. Counter Mode Operating Summary (CMS = 0) are shown with the WR plus entering the required between signals.
To keep the following mode descriptions concise and to the Mode A, shown in Figure 18a, is one of the simplest operating point, the phrase "source edges" is used to reter to active- modes. The counter will be available for counting source ‘going source edges only, not to inactive-going edges. Simi- edges when it is issued an ARM command. On each TC, the larly, the phrase ‘gate edges” refers only to active-going gate counter will reload from the Load register and automatically ‘edges. Also, again to avoid verbosity and euphuism, the disarm itself, inhibiting further counting. Counting will resume descriptions of some modes state that a counter is stopped or when a new ARM command is issued. disarmed "on a TC, inhibiting further counting.” As is fully ODE B explained in the TC section of this document, for these modes the counter is actually stopped or disarmed following the Software-Triggered Strobe with Level Gating active-going source edge which drives the counter out of TC. in other words, since a counter in the TC state always counts, [ CM15] G14] om13 | oMt2| cm11 |cmt0| cma | CMe | irespectve of its gating or arming status, the stopping or [—tever__| Gsarmng of the count sequence is delayed unt TC is veve [x Tx Tx Tx] x) terminated. [ox [ ome [ows Towa Toms | owe | ow | cwo | MODE A Lo Te To Tx Tx Tx Tx Tx | Software-Triggered Strobe with No Hardware Mode 8, shown in Figure 15b, is identical to Mode A except Gating that source edges are counted only when the assigned Gate is active. The counter must be armed before counting can occur. [emis [cia [ota [omt2|omt1|cMr0] cma | cma | Once armed, the counter will count all source edges which [x] ‘occur while the Gate is active and disregard those edges [re Po To Tx Tx Tx Tx [| Sich accu wie the Gato is inactive. This permis the Gate to tum the count process on and off. On each TC the counter [cum [ons [ows [cme [ons [ove [ow [Owo ] wil lon rom te toed roger and automaticaly dam rotetelxi[xilx{x x] itself, inhibiting further counting unit! a new ARM command is issued source LS L\\LIVIVLIVLIVSININ. ‘COMMAND ‘count i output Te TOGGLED ‘ourPuT wF004590 Figure 15a. Mode A Waveforms Am9513A 2-129
Non-Retriggerable One-Shot Software-Triggered Delayed Pulse One-Shot [cms [owra[cwrs]omi2[cwrs[omio] cma [owe] [cwrs]omis [owrs [owi2 [ows [euro] ome [ owe |] Lecce x Tx Tx Tx Tx] Foto fo lx fxtx[xfx] [om Tome Toms Tows [ows [owe [ows Tomo] [cur [ows [ows | ow | one [ove [om [owe | Leto} s [x TxTx Tx Tx] Pots totxfx[xfxfx ] Mode F, shown in Figure 15, provides a non-retriggerable In Mode G, the Gate does not affect the counter's operation. ‘one-shot timing function. The counter must be armed before it Once armed, the counter will count to TC twice snd then will function. Application of a Gate edge to the armed counter automatically disarm itself. For most applications, the counter will enable counting. When the counter reaches TC, it will will initially be loaded from the Load register either by a LOAD. reload itself from the Load register. The counter will then stop command or by the last TC of an earlier timing cycle. Upon counting, awaiting a new Gate edge. Note that unlike Mode C, counting to the first TC, the counter will reload itself from the anew ARM command is not needed after TC, only anew Gate Hold register. Counting wil proceed until the second TC, when ‘edge. After application of a triggering Gate edge, the Gate the counter will reload itself from the Load register and input is disregarded until TC. automatically disarm itself, inhibiting further counting. Counting can be resumed by issuing a new ARM command. A software- triggered delayed pulse one-shot may be generated by speci- fying the TC Toggled output mode in the Counter Mode register. The initial counter contents control the delay from the ‘ARM command unti the output pulse starts. The Hold register contents control the pulse duration. Mode G is shown in Fig- ure 159. = INK]. I.\\J\\ DDI YYVVYYVVVVVVY Ran NNNNW A004 120000000 ANNANANQNNNNI ourput Te ToccLeo ~ — ourpur X Wroo4640 Figure 15t. Mode F Waveforms 2-132 Am9513A
a AV AUAUAVAVAUAUAVAVAUAUAUAS ote KXAAMAA CAAAAXAXAAXAXAXXAXAAXX AA KLKARERRRRK RK cont —___., ve 1990499 eee X X J aa [oo cola weone7e Figure 15i. Mode | Waveforms MODE J MODE K Variable Duty Cycle Rate Generator with No Varlable Duty Cycle Rate Generator with Level Hardware Gating Gating Lo [io fotx TxTxTxTx] LEVEL Lx [x [x [xT x] [_ow? | ome [ ows Toma [oma Tome Tomi Towo ] [cur [owe [ows | owe [oma | owe | om | ono | Lo [i Ps Tx Px Pex) Fo Tr x Te Px Tx Te] Mode J, shown in Figure 15), will find the greatest usage in Mode K, shown in Figure 18k, is identical to Mode J, except frequency generation applications with variable duty cycle that source edges are only counted when the Gate is active. requirements. Once armed, the counter will count continuously The counter must be armed for counting to occur. Once until it is issued a DISARM command. On the first TC, the armed, the counter will count all source edges which occur counter will be reloaded from the Hold register. Counting will while Gate is active and disregard those source edges which then proceed until the second TC at which time the counter ‘occur while the Gate is inactive. This permits the Gate to turn will be reloaded from the Load register. Counting will continue, the count process on and off. As with Mode J, the reload . with the reload source alternating on each TC, until a DISARM. ‘source used will alternate on each TC, starting with the Hold ‘command is issued to the counter. (The third TC reloads from register on the first TC after any ARM command. When the TC the Hold register, the fourth TC reloads from the Load register, Toggled output is used, this mode allows the Gate to modulate etc.) A variable duty cycle output can be generated by the duty cycle of the output waveform. It can affect both the ‘specifying the TC Toggled output in the Counter Mode HIGH and LOW portions of the output waveform. register. The Load and Hold values then directly control the output duty cycle, with high resolution available when relatively hhigh count values are used.
24134 Am95134
Figure 150. Mode O Waveforms counter must first be issued an ARM command before count, Gate edges are used to start the counting operation. qualified source edge after the retriggering Gate edge. Quali- Gate edge.
nae AC ACACACAUAUACAUAUAUAUACACAUAUAG att QC OOO Tee qe ourpur / \\ Te Tosatep TT ourpur X neat? X c 7 aa N XY wr004773 Figure 15x. Mode X Waveforms MODE X After power-on reset or a Master Reset command, the ‘Counter Mode registers are initialized to a preset condition. Hardware Save (available in Am9513A only) ‘The value entered is OB00 hex and resufts in the tollowing [cms [owre Towra] owre| ours [omio] ome [oma] onvol contiguation: [ewe Tx Tx | Outpt omimoaience to ground [x] x] ouput low ‘Count binai [car [ows [ous [om [ows [owe Tou [owe] om tan Load register selected a Mode X, as shown in Figure 15x, provides a hardware F1 input source selected sampling of the counter contents without interrupting the Positive-true input polarity count. A LOAD AND ARM command or a LOAD command No gating followed by an ARM command is required to initialize the counter. Once armed, a Gate edge starts the counting Output Control operation; Gate edges applied to @ disarmed counter are Counter mode bits CMO through CM2 specify the output disregarded, After application ofthe Triggering Gate edge, the control configuration. Figure 17 shows a schematic reprosen- Counter will count all qualified source edges until the frst TC, tation of the output control logic. The OUT pin may be off (a irrespective of the gate level. All gato edges applied during the highimpedance state), or it may be inactive with a low. agston bet ey sal nt rt hin frogioieh ceebearhiy-e impedance to ground. The three remaining valid combinations. J interrupt resent active-high, active-low or TC Tc each TC, the counter will be reloaded from the Load register emer ng Nah. a © TC Toggle output and stopped. Subsequent counting requires a new triggering Gate edge; counting resumes on the first source edge One output form available is called Terminal Count (TC) and following the triggering Gate edge. represents the period in time that the counter reaches an is i ‘equivalent value of zero. TC will occur on the next count when Note: Mode X is only available in tho Am9513A devices. fhe counter a at 000! tor dows cowry 1 000 BOD) fee COUNTER MODE CONTROL OPTIONS BCD up counting or at FFFF (hex) for binary up counting. - Figure 18 shows a Terminal Count pulse and an example Each Counter Logic Group includes a 16-bit Counter Mode context that generated it. Tho TC width is determined by the (CM) register used to control all of the individual options period of the counting source. Regardless of any gating input available with its associated general counter. These options or whether the counter is Armed or Disarmed, the terminal include output configuration, count control, count source and count will go active for only one clock cycle. Figure 18 gating control. Figure 16 shows the bit assignments for the assumes active-high source polarity, counter armed, counter Counter Mode registers. This section describes the control —_decremmenting and an external reload value of K. ‘options in detail. Note that generally each counter is indepen dently configured and does not depend on information outside The counter will always be loaded from an external location its Counter Logic Group. The Counter Mode register shouldbe when TC occurs; the user can choose the source location and loaded only when the counter is Disarmed. Attempts to load —_the value. If a non-zero value is picked, the counter will never the Counter Mode register when the counter is armed may _really attain a zero state, and TC will indicate the counter state result in erratic counter operation. that would have been zero had no parallel transfer occurred. 2-140 Am9513A
Figure 18. Counter Output Waveforms duty-cyole square waves in Operating Modes G through K. _ valu, irrespective of the operating mode used. clearly be active-high or active-low, the TC Toggled output 2 TC Toggled output to toggle. cycle. This can be controlled by the Set and Clear Output —_— options available for direct control of the counting process. reload occurred. Some special conditions apply to counter _proceed in the specified mode until the counter is disarmed. ‘driving the counter to TC can be caused by the application Which generates the trailing ioe.
- fa LOAD or LOAD AND ARM command is executed during into the counter at every occurrence of TC. When CM6 = 1,
- When TC is active, the counter will always count the next sources and with the TC Toggled output selected, the duty
longer than one count period and it may, in fact, be shorterif may be achieved.
‘on the status of the Gating Control field and bits CMS and counter will proceed unconditionally as long as itis armed. For M6. any other gating mode, the count process is conditioned by Hardware Retriggering the specified gating configuration. For a code of 100 in this field, counting can proceed only when Whenever hardw one mall sea eta Sages witate verges ‘none the pin labeled GATEN associated with Counter N is at a logic tions. Gn application of the Gate edge, the counter contents "9 level. When it goes LOW, counting is simply suspended will bo transferred to the Hold register. On the first qualified ‘Until the Gate goes HIGH again. A code of 10) performs the Source edge after application of the retnggenng Gale edge, _S2”e function with an opposite acve polarity. Codes 010 and the Load register contonts willbe transferred into the counter. 0" offer the samme lunction as 100, bul epecily allele mow (Qualified source edges aro edges which occur while the Pins 3s Gating Sourcos, This aliows any of three interface pins Sounter is gated on and Armed) e used as gales for a given counter. On Counter 4, for | ‘example, pin 34, pin 35 or pin 36 may be used to perform the This means that, if level gating is used, the edge occurring on —_gating function. This also allows a single Gate pin to simulta- r active-going gate transitions will initiate a retrigger. Similarly, neously control up to three counters. Counters 1 and 5 are when edge gating is enabled, an edge used to start the considered adjacent when using TCN-1 (001), Gate N+1 counter will also initiate a retrigger. The first count source (010) and Gate N-1 (011) controls. ‘edge applied after the Gate edge will not increment/decre- mont the counter but retrigger it. For codes of 110 or 111 in this field, counting proceeds after the specified active Gate edge until one or two TC events Ita LOAD, LOAD AND ARM, or a STEP Command occurs occur. Within this interval, the Gato input is ignored, except for Betwoon the retiggering Gato edge and the fest qualtied the retiggering option, When repetitions selected, a cycle wil source edge, it will be interpreted as a source edge a be repeated as soon as another Gate edge occurs. With transfer the Load register contents into the counter. There- repetition selected, any Gate edge applied after TC goes after, the counter will count all qualified source edges. active will start a new count cycle. Edge gating is useful when When some form of Gating is specified, CM7 controls hard- _™lementing a digital single-shot since the gate can serve as ware retriggering. In this case, when CM7=0, hardware @ convenient firing trigger. retriggering does not occur; when CM7 = 1, the counter is ‘A001 code in this field selects the TC (not TOGGLE) output retriggered any time an active-going Gate edge occurs. from the adjacent lower-numbered counter as the gate. This is Retriggering causes the counter valve to be saved in the Hold useful for synchronous counting when adjacent counters are register and the Load register contents to be transferred into concatenated. the counter. JAND DE: When No Gating is speciied, the definition of CM7 changes. in. COMMAND SCRIPTIONS this case, when CM7 = 0, the Gate input has no effect on the The command set for the Am9513A allows the host processor counting: when CM7 = 1, the Gate input specities the source to customize and manage the operating modes and features (selecting either the Load or Hold register) used to reload the _for particular applications, to initialize and update both the counter when TC occurs. Figure 14 shows the various internal data _and control information, and to manipulate available control combinations for these interrelated bits. operating bits during operation. Commands are entered direct- nt Source Selection ly ite the @-bt Command register by writing into the Control Count Sour port (see Figure Counter Mode bits CM8 through CM12 specify the source All available commands are described in the following text used as input to the counter and the active edge that is Figure 19 summarizes the command codes and includes a Counted. Bit CM12 controls the polarity for all the sources: brief description of each function. Figure 20 shows all the logic zero counts rising edges and logic one counts falling a unused code combinations; unused codes should not be edges. Bits CM8 through CM11 select 1 of 16 counting entered into the Command register since undefined activities sources to route to the counter input. Five of the available thay occur. inputs are internal frequencies derived from the internal Y oscillator (see Figure 13 for frequency assignments). Ten of Six of the command types are used for direct software control the available inputs are interface pins; five are labeled SRC of the counting process and they each contain a S-bit S field, and five are labeled GATE. Ina linear-select fashion, each bit in the S field corresponds to The 16th available input is the TC output trom the adjacent 0" of five general counter (S1 = Counter 1, S2 = Counter 2 ‘etc.). When an S bit is a one, the specified operation is lower-numbered counter. (The Counter 5 TC wraps around to the Counter 1 input) This option allows internal concatenating Performed on he counter so designated, when an § bisa that permits very long counts to be accumulated. Since all five , No operation occur: corresponding counter. This counters may be concatenated, tis possible to configure a _7P8 of command format has three basic advantages. t saves Counter that is 80-bits long on one Am9519A chip. When TCN- __NOst software by allowing any combination of counters 10 be acted on by a single command. It allows simultaneous action 1 is the source, the count ripples between the connected — Oo tibia counters whore. synchronization of commands counters. External connections can also be made, and can On Mlle, couniers wltove synerwonsation © Cemanaln use the toggle bit for even longer counts. This is easily i Sa ee eevee ol the vidoe ty coloetingns TC neggied cutput mode ang individual counters without neodng to be aware of the Wainy OUT te ona of te SAC Ines operating context of other counters, Three of the commands use a 3-bit binary code (N4, N2, N1) Gating Control to identity the affected counter (a 001 programs counter 1, Counter Mode bits CM15, CM14, CM13 specify the hardware etc.). Unlike the previously mentioned commands, these gating options. When “'no gating” is selected (000), the commands allow you to program only one counter at a time, Am9513A 2-143
Special considerations apply when modes with alternating Description: Any combination of counters, as specified by the reload sources are used (Modes G-L). If a LOAD command _§ field, will be disarmed, and the contents of the counter will drives the counter to TC in these modes, the reload source for _be transferred into the associated Hold registers. This com- the next TC will be from the opposite reload location, In other mands identical to issuing a DISARM command followed by a words, the LOAD-generated TC will cause the reload sources SAVE command. to alternate just as a TC generated by a source edge would. Note that if a second LOAD command is issued during the Set TC Toggle Output LOAD-generated TC (or during any other TC, for that matter), (Towa ee ae] the second LOAD command wil terminate the TC and cause & Cag: See ne reload trom the source designated for use with the next TC. L1_t_1_o_ 1 Mw ve | The second LOAD will not alter the reload source for the next (001 <N< 101) TC since the second LOAD does not generate @ TC; reload Description: The initial output level for TC Toggle mode is set sources aftemate on TCs only, not on LOAD commends. (HIGH) for counter N selected by N4, N2, N1 = 001 (Counter Load and Arm Counters* 1) thru 104 (Counter §) respectively. This command conditions the TC Toggle flip-top (see Figure 17) but does not appear at Coding: the counter output unless TC Toggle mode (CM2, CMi, [oi 1 ss sa $3 ses | CMO = 010) Is selected. Description: Any combination of counters, as specified intheS Clear TC Toggle Output field, wil be first loaded and then armed. This command is fquivalent to issuing a LOAD command and then an ARM Cosa: command. Tor <n <ton ‘A LOAD AND ARM command which drives a counter to TC generates the same sequence of operations as execution of a Description: The initial output level for TC Toggle mode is LOAD command and then an ARM command. In modes which Cleared (LOW) for counter N selected by N4, N2, N1 = 001 disarm on TC (Modes A~C and N- O, and Modes G-1andS (Counter 1) thru 101 (Counter 5) respectively. This command it the current TC is the second in the cycle), the ARM part of conditions the TC Toggle flip-lop (see Figure 17) but does not the LOAD AND ARM command will re-enable counting for appear at the counter output unless TC Toggle mode (CM2, another cycle. In modes which alternate reload sources CM1, CMO = 010) is selected. (Modes G = L), the ARMing operation will cause the next TC to reload from the HOLD register, irrespective of which reload Step Counter Stns cored ahold nat Tesasaa a] “Ths command should not be used ding asynctronous Cog: 2 | operations. (oren <1 Disarm Counters Description: Counter Nis incremented or decremented by one, oting depending on its operating configuration. If the Counter Mode register associated with the selected counter has its CMG bit cleared to zero, this command will cause the counter to Description: Any combination of counters, as specified by the decrement by one. If CM3 is set to a logic high, this command S field, wll be disabled from counting. A disarmed counter will _will increment the counter by one. The STEP command will cease all counting independent of other conditions. The only _take effect even on a disarmed counter. exception to this is that a counter in the TC state will always count once, in order to leave TC, before DISARMing. This Load Data Pointer Register count may be generated by a source edge, by a LOAD or LOAD AND ARM command (the LOAD AND ARM command Code will negate the DISARM command) or by a STEP command. A disarmed counter may be updated using the LOAD command (Ga, G2, G1 #000, #110) land may be read using the SAVE command. A count Process Description: Bits in the E and G fiolds will be transferred into may be resumed using an ARM command, See the ARM the corresponding Element and Group fields of the Data command description for further details. Pointer register as shown in Figure 7. The Byte Pointer bit in Save Counters the Data Pointer register is set. Transfers into the Data Pointer only occur for G field values of 001, 010, 011, 100, 101 and Coding: 111. Values of 000 and 110 for G should not be used. See the “Setting the Data Pointor Register” section of this document {for additional details. Description: Any combination of counters, as specified by S field, will have their contents transferred into their associated -—-Disable Data Pointer Sequencing Hold register. The transfer takes place without interfering with any counting that may be underway. This command. wil Coding overwrite any previous Hold register contents. The SAVE command is designed to allow an accumulated count to be preserved so that ican be read by the host CPU at some later Description: This command sets Master Mode bit 14 without time. affecting other bits in the Master Mode register. MM14 Controls the automatic sequencing of the Data Pointer regis- Disarm and Save Counters ter. Disabling the sequencing allows repetitive host processor access to a given internal location without repetitive updating Coding: of the Data Pointer. MM14 may also be controlled by loading a full word into the Master Mode register. Am9513A 2445
Enable Data Pointer Sequencing cleared, FOUT will become active and will drive out the selected and divided FOUT signal. MM12 may also be coding «(67 G5_ OS Os OS GOLD controlled by loading the full Master Mode register in parallel When FOUT is gated on or off, a transiont pulse may be Description: This command clears Master Mode bit 14 with generated on the FOUT sional iption: This command clears Master 14 without . affecting other bits in the Master Mode register. MMi4 ‘Disable Prefetch for Write Operations controls the automatic sequencing of the Data Pointer regis- (ae ee tor Enabling the sequencing allows sequential host processor Cod access to several internal locations without repetitive updating of the Data Pointer. MM14 may also be controlled by loading a . full word into the Master Mode register. See the "Data Pointer Description: This command disables the pretatch crculty ‘ during Write operations (if does not affect Read operations). Register" section of this document for additonal information Tre 'sequces the write recovery ime and allows the user to on Data Pointer sequencing use block move instructions for initialization of the Ama513A Enable 16-Bit Data Bus registers. Once prefetch is disabled for writing, an Enable Prefetch for Write or a Reset command is necessary to re- Coding: enable the prefetch circuitry for writing, Note: This command is only available in Am9513A de- vices; it is an illegal command in the "non-A" Am9513 Description: This command sets Master Mode bit 13 without device. affecting other bits in the Master Mode register. MM13 controls the multiplexer in the data bus buffer. When MM13 is Enable Prefetch for Write Operations set, no multiplexing takes place and all 16 external data bus lines are used to transfer information into and out of the STC. ° MM13 may also be controlled by loading the full Master Mode register in parallel Description: This command re-enables the prefetch circuitry Enable 8-Bit Data Bus for Write operations. It is used only to terminate the Disable Prefetch Command. Coxing: Note: This command is only available in Am9513A de- vices; it is an illegal command in the “non-A” Am9513 device. Description: This command clears Master Mode bit 13 without affecting other bits in the Master Mode register. MMig ‘Master Reset controls the multiplexer in the data bus buffer. When MM13 is Coding: cleared, the multiplexer is enabled and 16-bit internal informa- Go] tion is transferred eight bits at a time to the eight low-order external data bus lines. MM13 may also be controlled by Description: The Master Reset command duplicates the action loading the full Master Mode register in parallel. of the power-on reset circuitry. It disarms all counters, enters ouT 0000 in the Master Mode, Load and Hold registers and enters Gate oft F 0800 (hex) in the Counter Mode registers. a command should be applied to all the counters to clear any that may be in a TC state. The Data Pointer register should Description: This command sets Master Mode bit 12 without —_aiso be set to a legal value, since reset does not initialize it. A affecting other bits in the Master Mode register. MM12 Complete reset operation follows controls the output state of the FOUT signal. When gates off, 7 the FOUT line will exhibit a low-impedance to ground. MM12 1. Using the procedure given in the "Command Initiation’: may also be controlled by loading the full Master Mode section of this document, enter the FF (hex) command to register in parallel. Perform a software reset. 2. Using the "Command Initiation” procedure, enter the Gate On FOUT LOAD command for all counters, opcode 5F (hex) (ae aw as a] 3. Using the procedure given in the "Setting the Data con et certain mene Data Pointer to a valid code. The legal Data Pointer Description: This command clears Master Mode bit 12 without codes are givan in Figure 8. affecting other bits in the Master Mode register. MM12 ‘The Master Mode, Counter Mode, Load and Hold registers controls the output status of the FOUT signal. When MM12 is can now be initialized to the desired valves. 2-146 ‘Am9513A
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES o o ‘Commercial (C) Devices All Signal Voltages with Respect to VSS oo... -05 V to +7.0 V Industrial (I) Devices 7 Power Dissipitation (Package Limitation)... SW Temperature (Ta) . -40 to +85°C Supply Voltage (Voc) 5 V +5% Stresses above those listed under ABSOLUTE MAXIMUM Military (M) Devices at or above these limits is not implied. Exposure to absolute Supply Voltage (Vcc) ves cece V 5% roabity. ratings for extended periods may affect device Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified, [_ Parameters _| Description Test Conditions [min [Max [units | [ Aioae tome [dt S05 [oe | “ Woot tow Vota? iets [oe | NO xe eet 8 ver [witout aterosis (GRC and GATE inpats Om) ets [vou J ouput Low votage | mama CTT | [vor | Owput High Votage |= -200 AT we | ts ee [vss <vn<voo [io wk [Lon Garant x2 |v vIn VOGT 00 wa [6c Wo Sippy Carrot Bioady Stata) Tar [oN [trout Capacitance py ae fins not ender tess ao v |__| 18" [ 20" | [Tor 20] * Guaranteed by design. SWITCHING TEST INPUT/OUTPUT WAVEFORMS Pa ‘TepF av Bae aa 5 0.8 = )——~ 0.8. x csv rows 2 Wroo4810 =” re002000 Crystal is fundamental mode paral! resonant 32 pF load capactance less than 100 £1 ESA Go less than 100 oF Am9513A 2-147
The second and fourth letters designate the reference states rameter represents the minimum setup or hold times to of the signals named in the first and third letters respectively, ‘ensure that the Gate input is seen at the intended level on Using the following abbreviations. the active source edge and the counter may be off by one H= HIGH count. L=Low 10. This parameter assumes that the GATENA input is unused V= VALID (16-bit bus mode) or is tied high. In cases where the X= Unknown or Don't care GATENA input is used, this timing specification must bo Z = High-impedance met by both the GATE and GATENA inputs. 2. Any input transition that occurs before this minimum setup _14. Signals F1- FS cannot be directly monitored by the user. fequirement will be reflected in the contents read trom the The phase difference between these signals will manifest status register. itself by causing counters using two different F signals to 3. Any input transition that occurs before this minimum setup ‘count at different times on nominally simultaneous transi- requirement will act on the counter before the execution of tions in the F signals. F1 = X2. the operation initiated by the write and the counter may be 42. This timing specification assumes that CS is active when- of by one count. ‘ever RD or WH are active. CS may be held active 4, Any input transition that occurs after this minimum hold time. indefinitely. is guaranteed to not influence the contents read from the status register on the current read operation. 8 wa ete’ acumes X28 from an extemal gate 5. Any input transition that occurs after this minimum hold time is guarantoed tobe soon bythe counter as occuring after __'%- TRS parameter assumes that the wie operation i to the the action initiated by the write operation and the counter ‘command regis may be off by one count. 15. This timing specification applies to single-action com- 6. Te paramotr aps 1 cease nora he wna operation TAC ommend such as LOAD AND APM and DISARM " AND SAVE, TWHEH minimum = 700 ns. 7.The enabled count source is one of F1-F5, TCN-1 SRC1~SRC5 or GATE1-GATE 5, as selected in the 16.In short data write mode, TWHRL and TWHWL mini- applicable Counter Mode register. The timing diagram ‘mum = 1000 ne. assumes the counter counts on rising source edges. The 47. This parameter applies to the hardware retrigger/save timing specifications are the same for faling-edge counting. modes N, O, Q, R, and X (CM7 = 1 and CM15 ~CM13 <> 8. This parameter applies to edge gating (CM15 -CM13 = 110 (000). This parameter ensures that the gating pulse initiates ‘or 111) and gating when both CM7=1 and CM15~ a hardware retrigger/save operation. CM13 #000. This parameter represents the minimum i GATE pulse width needed to ensure thatthe pulse niiatos 1 Ts Parameley apaes fo harsuawe loot sou The counting or courier reloeding Parameter represents the minimum hold time to ensure 9.This parameter epplios to both edge and level gating that the GATE input selects the comect load source on the (CM15~CM13 = 001 through 111 and CM7 = 0). This pa- active source edge. 2-148 ‘Am9513A
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (Note 1) roe [| nt | meen omen Pe | [cravat [CB vans toFeedtowSSSSSOSOSSSSSCSSCCCCTCSCS a [Tavwe | G7 Vat to Write High fro fs [TCHCH [x2 High to X2 High (2 Period) (Noto 13) ae as [ns | [TenGt [Xe High to X2 Low (2 High Pulse Wiamy Woe Ti | 0 [Toto] Xe tow to ¥2 High 0 Low Pulse Wish) (ote 15) i ef 0 fd [TOVWH ‘Data in Vaid to Wate High eo fe [“TEHEH | Count Source High to Count Source High (Source Gycie Time) (Nowe 7) Tae as as | THEE [contac re oommoeP T | [“Tenev | Gooni Source High to FOUT Vand (oie 80 ["Tenav—| Count Source High to Gate Vaid (vel Gaing Hod Time) (woes 870) ——SiY ee || | | TERAL | Count Source High to Reed Low (Setup Time) (Notes 2,7) at a90 fT ns | “TeRWH [Count Source High to Write High (Setup Time) (Notes 7) Tat fro Ts [7 Cupra 800 | TEHYV | Count Source High to Out Valid (Note 7) [Immediate or Delayed Toggle Outpt [22 [| 300 | [Comparator Ouist dee tC C8 (Nain vee —CS ae | [TGVEH | Gate Vaid to Gouni Source High (Level Gating Setup Tene) (Notes 7.8.10) | af xoo [ns | [Tavev | Gate Vaid to Gate Vaid (Gato Pulse Ouation) (Notes 8 10) ae tas [ns [revwit | Gate Vaid wo Write High Wotes 1) sf 100 [Tawax —[ Read righ to C78 Dont care a | TRHEH | Read High to Count Source High (Notes 47) fs [Tanax—[ Reed Pion to Daa Outivats—S | [TRHOZ | Read High to Data Out at Highimpodance (ata Bus Release Time) [arf es Tons | ead High to Read Low (Read Recovery Time) [21 {000 [ns [TRHSH | Read High to ©S High (Note 12) ao [CTRHWL | Read High to Wie Low (Read Resoven Tine) | ef 0 os [CTRLQV—[ Read_tow fo Dats Oa Vals Sos | [TRLGX | Read Low to Data Bus Driven (Data Bus Dive Tima Pa 20s [TRLRH —[ Read Low to Read Fgh (Road Purse Owratony Wore 1a) et r00 fo | [CTSA [EE tow we Road tow Wow] [TSLWH [CS Low to Wnte High Nott io Ts | [twriax—[ write High to C7 Don't Gave [TWox | wrt High to Dala in Dont Care a2 [TWHEH | Write High to Count Source High (Notes 571415) a sso fs [TWHGW | Write High to Gate Vaid (Notes 5,10, 14) a fas fos [wit —] Write Hig to Road Low (Wirte Recovery Tana) Wate 1) ar ro | [crwash [write High to CS High Rowe 8s | Twewt | Write High to Wrie Low (Write Recovery Time) (Note 16) a goon fs [WHY | Wiite High to Out Vato (Notes & 1) a 0s ns [iwiwi—[ Wire Low to Write High (Write Puise Owaton) Wie 1) Os | [TavEH2 | Gate Vaid to Count Source High (Specal Gate) (Notes 10.117) ae 200 [Ts [~TenGv2 | Count Source High to Gate Vaid (Special Gate) (Notes 10, 19,16) Tae eo J ns Notes: (Enabled counter source input) = SRC1 - SRCS5, 1. Abbreviations used forthe switching parameter symbols are CATEL GATES, F1-FS.TON given as the letter T followed by four or five characters. - . P first and third characters represent the signal names on $ ote oe GATES, TON which the measurements start and end. Signal abbrevia- R (Read) = FO tions used are: S (Chip Select) = TS A (Address) = C/D W (Write) = WR © (Clock) = x2 Y (Output) = OUT - OUTS D (Data In) = 0B0-DB15 ‘Am9513A 2-149
SWITCHING CHARACTERISTICS over MILITARY operating range (for SMD/DESC and APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) [_amesisa_] veer | ea Symbol [_TavAL {G/B Vat to Read Low ss | | TavWH [7B Valid to Write High ro | |_TOHCH | x2 High to X2 High (x2 Period) (Note 49) as [Foner [x2 High to X2 Low 0x2 High Puse width) (Note 9) oe [Touch [x2 Low to X2 High (X2 Low Pulse Width) (Note Yay oes | [ToWwH [Data In Valid to Write High eo eT ste minaenee eT | |_ isk [coer sonce ram Ovntinwen Te Tt [TERY [Count Source High to FOUT Vaid (Note 7) 000 fe | [eer [saa errant tenet | [-TeHAL [Count Source High to Read Low (Setup Time) (Notes 27) 90 fos [_TEHWH [Count Source High to Write High (Setup Time) (Notes 9.7) 00 Fes [¥C Output TT 900 TeHw Count Source High to Out Valié (Note 7) [immediate or Delayed Topple Ouiput_ | 900 | [Comparator Output TT 380 [TEN | FN High to FN Vaid (Note ty ass Tee [serine ene weer mem ef | | ravav [Gate Vaid io Gate Vaid (Gate Pulse Duration) (Notes 6 yo) as re | Tavwe [Gate Vaid to Write High (Notes 9. 90) 100 Ts | TRHAX | "Read High to G/B Don't Care os | TaHEH | Read High to Count Source High (Notes 47) ns [TRHGX [Read High to Data Out invaig os [wer amiraaragrers Te Pe [TRHRL [Read High to Read Low (Read Recovery Time) 0 i000 fe [TRHSH [Read High to CS High (Nowe 2) [_TRHWL | "Read High to Wits Low (Read Recovery Time) UT TT oo fe [ Trav [Read Low to Data Out Vaid oe [_TRLOX [Read Low to Data Bus Deven (Data Bus Drive Timey oe [TRLRH | Read Low to Read High (Read Pulse Duration) (Note 12) veo Tne [TStRL | TS tow to Read Low (Note 92) [_Tsuwi [ES tow to Write High (Note 42) 0 io fee [TWHAX | "Wate High to G7 Don't Gare eo [- TwHox [Write High to Oata in Don't Gare eo fe [TWHEH [Wate High to Count Source High (Notes 5,7, 14,6) eso fe) | Twrav [Write High to Gate Vaid (Notes 6, 10.94) as Tne | TWHRL [Wate High to Read Low (wite Recovery Time) (Note 16) 800 [ns [Twos | write High to GS High (Note 42) eo TO [Tweewe | Wirte High to Write Low (Wite Recovery Time) (Note Ye) soo fe [TwHvv | Write High to Out Valid (Notes 64) eso | [TWLwH [Write Low to Write High (Write Pulse Duration) (Note ¥2) as fs [_TGveHi2 | Gate Valid to Count Source High (Special Gate) (Notes 10.19.17) 20 ns | [ TenGve [Count Source High to Gate Valid (Special Gato) (Notes 10, 19, 18) Tens Notes: E (Enabled counter source input) = SRC1 - SRC5, 1. Atbrviaions used forthe swichng parameter symbolsare——_«, GATES ~GATES, 1 ~FS,TCN given as the letter T followed by four or five characters. The G (Counter gate input) = GATE! - GATES, TCN-1 first and third characters represent the signal names on © (Oata Oub = DB0- B15 which the measurements start and end. Signal abbrevia- R (Read) = AD tions used are: S (Chip Select) = CS A (Address) = C/D W (Write) = WR © (Clock) = x2 Y (Output) = OUT - OUTS © (Data tn) = DBO~ DB1S (2-150 Am9513A
The second and fourth letters designate the reference states rameter represents the minimum setup or hold times to of the signals named in the first and third letters respectively, ‘ensure that the Gate input is seen at the intended level on using the following abbreviations. the active source edge and the counter may be off by one ing H=HIGH count. L=LOw 10. This parameter assumes that the GATENA input is unused V=VALIO (16-bit bus mode) or is tied high. in cases where the X= Unknown or Don't care GATENA input is used, this timing specification must be Z = High-Impedance met by both the GATE and GATENA inputs. 2. Any input transition that ocours before this minimum setup 44, Signals F1-F5 cannot be directly monitored by the user. requirement will be reflected in the contents read from the ‘The phase difference between these signals will manifest status register. itself by causing counters using two different F signals to 4. Any input transition that occurs before this minimum setup count at different times on nominally simultaneous transi- requirement will act on the counter before the execution of tions in the F signals. F1 = x2. the operation initiated by the write and the counter may be 12. This timing specification assumes that CS is active when- off by one count, ever FID or WR are active. CS may be held active 4. Any input transition that occurs after this minimum hold time indefinitely. is guaranteed to not influence the contents read from the 43. This parameter assumes X2is driven from an external gate status register on the current read operation. with a square wave. 5. Any input transition that occurs after this minimum hold time is guarartood fo be seen bythe counters occurtng ater 14 TNS parameter assumes that the wite operation is to the the action initiated by the write operation and the counter command register. may be off by one count. 15. This timing specification applies to single-action com- causes a change in the output 6 oper action commands such as LOAD AND ARM and DISARM ‘AND SAVE, TWHEH minimum = 700 ns. 7.The enabled count source is one of F1-F5, TON- SRC1_SRCS or GATE1_GATE 5, as selected in the 16.In short data write mode, TWHRL and TWHWL mini- applicable Counter Mode register. The timing diagram mum = 1000 ns. ‘assumes the counter counts on rising source edges. The 47. This s ve parameter applies to the hardware retrigger/save timing specifications are the same for faling-edge counting. ‘modes N, O, Q, R, and X (CM7 = 1 and CM15 —CM13 <> 8, This paramater applies to edge gating (CM15 -CM13 = 110 000). This parameter ensures that the gating pulse initiates of 111) and gating when both CM7=1 and CM15~ a hardware retriggor/save operation. M13 #000. This parameter represents the minimum GATE pulse width needed to ensue that the pulse initates "© TN Darema apmes fo Nuite loa so Ths counting or counter reloading. . parameter represents the minimum hold time to ensure 9. This parameter applies to both edge and level gating that the GATE input selects the correct load source on the (CM15-CM13 = 001 through 111 and CM7 = 0). This pa- active source edge SWITCHING TEST CIRCUIT ox Q vieuy . ° © 3 t = 0068 + 200F Q on ‘To009883 This test circuit is the dynamic load of a Teradyne J941 Am9513A 2-451
Design Hints 10) Timing parameters TEHWH and TGVWH are specified as 1)When a crystal is not being used, X1 and X2 should be Cagative. Te diagrams in Figure AG show the relationship connected as shown for TTL input (Figure At) and no input ‘on (Figure A2). 11) In mode X the counter will count all qualified source edges 2) Recommended oscillator capacitor values are 18 pF on X1 ‘until the second (not the first) TC and then stop. and X2. 12)A TC can occur when the counters are loaded if the 3) Unused inputs should be tied to VCC. counter was stopped at FFFF} or 999910 in the count up 4) The TC output can glitch when the counter is loaded. For mode or at count 0001 when counting down. mie because an internal TC is generated which forces TC to be this reason this output should not be connected to edge erated on the next count pulse sensitive interrupts. The counter output should be set or gen Pulse. cleared after the LOAD command. 13) 1n modes that alternate the reload source between the 5, The two most significant bits of the status register are not load and the hold registers (0.g., mode J), if the counter is. specified. They may be zero or one. disarmed at 00011 for down counting or 999939 for BCD ; Lup counting or FFFF} for binary up counting and rearmed, 6. The mode register should not be modified when the counter the reload source after the first TC will be the load register is armed. instead of the hold register. To avoid this, issue a software 7. The LOAD and HOLD registers should not be changed "dummy" load to the counter immediately after the disarm during TC. Command. 8. When using the different clocks for different counters be 14) In the down counting mode of the Am9513A, i a 0001 is aware that there is a 75 ns skew betwoen Ft, F2, F3, F4 loaded into the counter and another LOAD COUNTER and FS. ‘command is issued, the TC of that counter will go active. If ive i the load register contents are subsequently changed, and 8, The TC output will remain inactive If programmed to be in the counter armed, the first clock edge will cause the new the TC TOGGLE mode and the step command is used to ‘ load register contents to transfer into the counter and the increment or decrement the counter. The output will go into et rial detec the counter andra t TC if programmed to be in the active High or active Low ent corn 0099 rement the counter and make it go terminal count modes. The only two ways out of TC in this out of case are: 16) Glitches on CS just before the AD or WA pulse may cause —Arming the counter and having an active source con- the part to behave incorrectly. nected to it. 16) Timing parameters TGVEH & TEHGV must not be vio- —ssuing another step command. lated; Figure A4 shows a method. Troubleshooting (Symptom: Solution) 4) Registers not being programmed correctly: Check READ or WRITE recovery time. 2) Setup and hold problems observed in synchronous systems: Try switching from positive edge to negative edge triggering. Yoo x1 (OUTPUT) Yoo Ama613A Re DAVER x2 @euT) crcurry To004080 Ri = 68 k& £10% R2 Is a function of Driver Circuitry to meet x2 VIH=38 V x2 vil=08V Figure A1. Crystal Input Configuration Am9513A 24153
n ‘V80F v a aa rein Figure A2. Crystal Input Configuration oan as Tew " Ete, | rose Figure A3. TEHWH/TGVWH Timing Diagram - | - Cu ~ we ren Figure A4. GATE/SRC Configuration Suggestion 2-154 Am9513A